ArmPlatformPkg: Introduce Primary core macros

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibCTA9x4 / CTA9x4Boot.S

//\r
//  Copyright (c) 2011, ARM Limited. All rights reserved.\r
//\r
//  This program and the accompanying materials\r
//  are licensed and made available under the terms and conditions of the BSD License\r
//  which accompanies this distribution.  The full text of the license may be found at\r
//  http://opensource.org/licenses/bsd-license.php\r
//\r
//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
//\r
//\r
\r
#include <AsmMacroIoLib.h>\r
#include <Base.h>\r
#include <Library/ArmPlatformLib.h>\r
#include <Drivers/PL35xSmc.h>\r
#include <ArmPlatform.h>\r
#include <AutoGen.h>\r
\r
.text\r
.align 3\r
\r
GCC_ASM_EXPORT(ArmPlatformInitializeBootMemory)\r
GCC_ASM_IMPORT(PL35xSmcInitialize)\r
\r
//\r
// For each Chip Select: ChipSelect / SetCycle / SetOpMode\r
//\r
VersatileExpressSmcConfiguration:\r
    // NOR Flash 0\r
    .word     PL350_SMC_DIRECT_CMD_ADDR_CS(0)\r
    .word     PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
    .word     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV\r
\r
    // NOR Flash 1\r
    .word     PL350_SMC_DIRECT_CMD_ADDR_CS(4)\r
    .word     PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
    .word     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV\r
\r
    // SRAM\r
    .word     PL350_SMC_DIRECT_CMD_ADDR_CS(2)\r
    .word     PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
    .word     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_ADV\r
\r
    // Usb/Eth/VRAM\r
    .word     PL350_SMC_DIRECT_CMD_ADDR_CS(3)\r
    .word     PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)\r
    .word     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
\r
    // Memory Mapped Peripherals\r
    .word     PL350_SMC_DIRECT_CMD_ADDR_CS(7)\r
    .word     PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
    .word     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
\r
    // VRAM\r
    .word     PL350_SMC_DIRECT_CMD_ADDR_CS(1)\r
    .word     0x00049249\r
    .word     PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
VersatileExpressSmcConfigurationEnd:\r
\r
/**\r
  Initialize the memory where the initial stacks will reside\r
\r
  This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
  In some platform, this region is already initialized and the implementation of this function can\r
  do nothing. This memory can also represent the Secure RAM.\r
  This function is called before the satck has been set up. Its implementation must ensure the stack\r
  pointer is not used (probably required to use assembly language)\r
\r
**/\r
ASM_PFX(ArmPlatformInitializeBootMemory):\r
  mov   r5, lr\r
\r
  //\r
  // Initialize PL354 SMC\r
  //\r
  LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)\r
  LoadConstantToReg (VersatileExpressSmcConfiguration, r2)\r
  LoadConstantToReg (VersatileExpressSmcConfigurationEnd, r3)\r
  blx   ASM_PFX(PL35xSmcInitialize)\r
\r
  //\r
  // Page mode setup for VRAM\r
  //\r
  LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)\r
\r
  // Read current state\r
  ldr     r0, [r2, #0]\r
  ldr     r0, [r2, #0]\r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0]\r
  ldr     r0, [r2, #0]\r
\r
  // Enable page mode\r
  ldr     r0, [r2, #0]\r
  ldr     r0, [r2, #0]\r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0]\r
  LoadConstantToReg (0x00900090, r0)\r
  str     r0, [r2, #0]\r
\r
  // Confirm page mode enabled\r
  ldr     r0, [r2, #0]\r
  ldr     r0, [r2, #0]\r
  ldr     r0, = 0x00000000\r
  str     r0, [r2, #0]\r
  ldr     r0, [r2, #0]\r
\r
  bx    r5\r