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1 | /** @file\r |
2 | *\r | |
214698e7 | 3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
f9cec5f1 HL |
4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include <Library/ArmPlatformLib.h>\r | |
16 | #include <Library/DebugLib.h>\r | |
214698e7 | 17 | #include <Library/HobLib.h>\r |
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18 | #include <Library/PcdLib.h>\r |
19 | #include <Library/IoLib.h>\r | |
20 | #include <Library/MemoryAllocationLib.h>\r | |
21 | #include <ArmPlatform.h>\r | |
22 | \r | |
214698e7 OM |
23 | // Number of Virtual Memory Map Descriptors\r |
24 | #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5\r | |
f9cec5f1 HL |
25 | \r |
26 | // DDR attributes\r | |
27 | #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r | |
28 | #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED\r | |
29 | \r | |
30 | /**\r | |
31 | Return the Virtual Memory Map of your platform\r | |
32 | \r | |
33 | This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.\r | |
34 | \r | |
35 | @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-\r | |
36 | Virtual Memory mapping. This array must be ended by a zero-filled\r | |
37 | entry\r | |
38 | \r | |
39 | **/\r | |
40 | VOID\r | |
41 | ArmPlatformGetVirtualMemoryMap (\r | |
42 | IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap\r | |
43 | )\r | |
44 | {\r | |
45 | ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;\r | |
214698e7 | 46 | EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;\r |
f9cec5f1 HL |
47 | UINTN Index = 0;\r |
48 | ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;\r | |
214698e7 OM |
49 | EFI_VIRTUAL_ADDRESS SparseMemoryBase;\r |
50 | UINT64 SparseMemorySize;\r | |
f9cec5f1 HL |
51 | \r |
52 | ASSERT(VirtualMemoryMap != NULL);\r | |
53 | \r | |
214698e7 OM |
54 | ResourceAttributes =\r |
55 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
56 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
57 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
58 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
59 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
60 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
61 | EFI_RESOURCE_ATTRIBUTE_TESTED;\r | |
62 | \r | |
63 | // Declared the additional DRAM from 2GB to 8GB\r | |
64 | SparseMemoryBase = 0x0880000000;\r | |
65 | SparseMemorySize = SIZE_2GB + SIZE_4GB;\r | |
66 | \r | |
67 | BuildResourceDescriptorHob (\r | |
68 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
69 | ResourceAttributes,\r | |
70 | SparseMemoryBase,\r | |
71 | SparseMemorySize);\r | |
72 | \r | |
f9cec5f1 HL |
73 | VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));\r |
74 | if (VirtualMemoryTable == NULL) {\r | |
75 | return;\r | |
76 | }\r | |
77 | \r | |
78 | if (FeaturePcdGet(PcdCacheEnable) == TRUE) {\r | |
79 | CacheAttributes = DDR_ATTRIBUTES_CACHED;\r | |
80 | } else {\r | |
81 | CacheAttributes = DDR_ATTRIBUTES_UNCACHED;\r | |
82 | }\r | |
83 | \r | |
84 | // DDR\r | |
85 | VirtualMemoryTable[Index].PhysicalBase = ARM_VE_DRAM_BASE;\r | |
86 | VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;\r | |
87 | VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;\r | |
88 | VirtualMemoryTable[Index].Attributes = CacheAttributes;\r | |
89 | \r | |
90 | // CPU peripherals. TRM. Manual says not all of them are implemented.\r | |
91 | VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r | |
92 | VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;\r | |
93 | VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;\r | |
94 | VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r | |
95 | \r | |
96 | // Peripheral CS2 and CS3\r | |
97 | VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;\r | |
98 | VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;\r | |
99 | VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;\r | |
100 | VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r | |
101 | \r | |
214698e7 OM |
102 | // Map sparse memory region if present\r |
103 | VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;\r | |
104 | VirtualMemoryTable[Index].VirtualBase = SparseMemoryBase;\r | |
105 | VirtualMemoryTable[Index].Length = SparseMemorySize;\r | |
106 | VirtualMemoryTable[Index].Attributes = CacheAttributes;\r | |
107 | \r | |
f9cec5f1 HL |
108 | // End of Table\r |
109 | VirtualMemoryTable[++Index].PhysicalBase = 0;\r | |
110 | VirtualMemoryTable[Index].VirtualBase = 0;\r | |
111 | VirtualMemoryTable[Index].Length = 0;\r | |
112 | VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;\r | |
113 | \r | |
114 | *VirtualMemoryMap = VirtualMemoryTable;\r | |
115 | }\r |