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1e57a462 | 1 | /** @file\r |
2 | *\r | |
e700a1fc | 3 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
1e57a462 | 4 | *\r |
75f63034 OM |
5 | * This program and the accompanying materials\r |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
1e57a462 | 12 | *\r |
13 | **/\r | |
14 | \r | |
15 | #include <Library/IoLib.h>\r | |
75f63034 | 16 | #include <Library/ArmGicLib.h>\r |
1e57a462 | 17 | #include <Library/ArmPlatformLib.h>\r |
18 | #include <Library/DebugLib.h>\r | |
19 | #include <Library/PcdLib.h>\r | |
20 | \r | |
21 | #include <Drivers/PL310L2Cache.h>\r | |
22 | #include <Drivers/SP804Timer.h>\r | |
23 | \r | |
24 | #include <ArmPlatform.h>\r | |
25 | \r | |
75f63034 OM |
26 | // Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet\r |
27 | VOID\r | |
28 | InitializeGicV3 (\r | |
29 | VOID\r | |
30 | );\r | |
31 | \r | |
1e57a462 | 32 | /**\r |
33 | Initialize the Secure peripherals and memory regions\r | |
34 | \r | |
35 | If Trustzone is supported by your platform then this function makes the required initialization\r | |
36 | of the secure peripherals and memory regions.\r | |
37 | \r | |
38 | **/\r | |
39 | VOID\r | |
40 | ArmPlatformSecTrustzoneInit (\r | |
41 | IN UINTN MpId\r | |
42 | )\r | |
43 | {\r | |
44 | // No TZPC or TZASC on RTSM to initialize\r | |
45 | }\r | |
46 | \r | |
47 | /**\r | |
48 | Initialize controllers that must setup at the early stage\r | |
49 | \r | |
50 | Some peripherals must be initialized in Secure World.\r | |
51 | For example, some L2x0 requires to be initialized in Secure World\r | |
52 | \r | |
53 | **/\r | |
54 | RETURN_STATUS\r | |
55 | ArmPlatformSecInitialize (\r | |
56 | IN UINTN MpId\r | |
57 | )\r | |
58 | {\r | |
75f63034 OM |
59 | UINT32 Identification;\r |
60 | \r | |
1e57a462 | 61 | // If it is not the primary core then there is nothing to do\r |
bebda7ce | 62 | if (!ArmPlatformIsPrimaryCore (MpId)) {\r |
1e57a462 | 63 | return RETURN_SUCCESS;\r |
64 | }\r | |
65 | \r | |
66 | // Configure periodic timer (TIMER0) for 1MHz operation\r | |
67 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);\r | |
68 | // Configure 1MHz clock\r | |
69 | MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);\r | |
70 | // Configure SP810 to use 1MHz clock and disable\r | |
71 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r | |
72 | // Configure SP810 to use 1MHz clock and disable\r | |
73 | MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r | |
74 | \r | |
75f63034 | 75 | // Read the GIC Identification Register\r |
e700a1fc | 76 | Identification = ArmGicGetInterfaceIdentification (PcdGet32 (PcdGicInterruptInterfaceBase));\r |
75f63034 OM |
77 | \r |
78 | // Check if we are GICv3\r | |
e700a1fc | 79 | if (ARM_GIC_ICCIIDR_GET_ARCH_VERSION(Identification) >= 0x3) {\r |
75f63034 OM |
80 | InitializeGicV3 ();\r |
81 | }\r | |
82 | \r | |
1e57a462 | 83 | return RETURN_SUCCESS;\r |
84 | }\r | |
85 | \r | |
86 | /**\r | |
87 | Call before jumping to Normal World\r | |
88 | \r | |
89 | This function allows the firmware platform to do extra actions before\r | |
90 | jumping to the Normal World\r | |
91 | \r | |
92 | **/\r | |
93 | VOID\r | |
94 | ArmPlatformSecExtraAction (\r | |
95 | IN UINTN MpId,\r | |
96 | OUT UINTN* JumpAddress\r | |
97 | )\r | |
98 | {\r | |
99 | *JumpAddress = PcdGet32(PcdFvBaseAddress);\r | |
100 | }\r |