[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Scripts / uefi-aarch64-bootstrap / boot.S

/*\r
 * boot.S - simple register setup code for junping to a second stage bootloader\r
 *\r
 * Copyright (C) 2011-2013 ARM Limited.\r
 * All rights reserved.\r
 *\r
 * Redistribution and use in source and binary forms, with or without\r
 * modification, are permitted provided that the following conditions are\r
 * met:\r
 *\r
 *     * Redistributions of source code must retain the above copyright\r
 *        notice, this list of conditions and the following disclaimer.\r
 *     * Redistributions in binary form must reproduce the above copyright\r
 *       notice, this list of conditions and the following disclaimer in\r
 *       the documentation and/or other materials provided with the\r
 *       distribution.\r
 *     * Neither the name of ARM nor the names of its contributors may be\r
 *       used to endorse or promote products derived from this software\r
 *       without specific prior written permission.\r
 *\r
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS\r
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
 *\r
 * This license can also be found in the LICENSE.TXT file.\r
 */\r
\r
	.text\r
\r
	.globl	_start\r
\r
.set LED_ADDR, 0x1c010008\r
\r
_start:\r
	/*\r
	 * EL3 initialisation\r
	 */\r
\r
	// Set LED to show progress.\r
	ldr	x1, =LED_ADDR\r
	mov	w0, #0x1\r
	str	w0, [x1]\r
        dsb	sy\r
\r
#if defined START_EL2\r
\r
	mrs	x0, CurrentEL\r
	cmp	x0, #0xc			// EL3?\r
	b.ne	start_ns			// skip EL3 initialisation\r
\r
	mov	x0, #0x30			// RES1\r
	orr	x0, x0, #(1 << 0)		// Non-secure bit\r
	orr	x0, x0, #(1 << 8)		// HVC enable\r
	orr	x0, x0, #(1 << 10)		// 64-bit EL2\r
	msr	scr_el3, x0\r
\r
	msr	cptr_el3, xzr			// Disable copro. traps to EL3\r
\r
	ldr	x0, =CNTFRQ\r
	msr	cntfrq_el0, x0\r
\r
	/*\r
	 * Check for the primary CPU to avoid a race on the distributor\r
	 * registers.\r
	 */\r
	mrs	x0, mpidr_el1\r
	tst	x0, #15\r
	b.ne	1f				// secondary CPU\r
\r
	ldr	x1, =GIC_DIST_BASE		// GICD_CTLR\r
	mov	w0, #3				// EnableGrp0 | EnableGrp1\r
	str	w0, [x1]\r
\r
1:	ldr	x1, =GIC_DIST_BASE + 0x80	// GICD_IGROUPR\r
	mov	w0, #~0				// Grp1 interrupts\r
	str	w0, [x1], #4\r
	b.ne	2f				// Only local interrupts for secondary CPUs\r
	str	w0, [x1], #4\r
	str	w0, [x1], #4\r
\r
2:	ldr	x1, =GIC_CPU_BASE		// GICC_CTLR\r
	ldr	w0, [x1]\r
	orr	w0, w0, #3			// EnableGrp0 | EnableGrp1\r
	str	w0, [x1]\r
\r
	mov	w0, #1 << 7			// allow NS access to GICC_PMR\r
	str	w0, [x1, #4]			// GICC_PMR\r
\r
	msr	sctlr_el2, xzr\r
\r
#if defined START_EL1\r
\r
	/* Now setup our EL1. Controlled by EL2 config on Model */\r
	mrs	x0, hcr_el2			// Read EL2 Hypervisor configuration Register\r
	orr	x0, x0, #(1 << 31)		// Set EL1 to be 64bit\r
\r
	// Send all interrupts to their respective Exception levels for EL2\r
	bic	x0, x0, #(1 << 3)		// Disable virtual FIQ\r
	bic	x0, x0, #(1 << 4)		// Disable virtual IRQ\r
	bic	x0, x0, #(1 << 5)		// Disable virtual SError and Abort\r
	msr	hcr_el2, x0			// Write back our settings\r
\r
	/*\r
	 * Enable architected timer access\r
	 */\r
	mrs	x0, cnthctl_el2\r
	orr	x0, x0, #3			// Enable EL1 access to timers\r
	msr	cnthctl_el2, x0\r
\r
	mrs	x0, cntkctl_el1\r
	orr	x0, x0, #3			// EL0 access to counters\r
	msr	cntkctl_el1, x0\r
\r
	/* Set ID regs */\r
	mrs	x0, midr_el1\r
	mrs	x1, mpidr_el1\r
	msr	vpidr_el2, x0\r
	msr	vmpidr_el2, x1\r
\r
	/* Coprocessor traps. */\r
	mov	x0, #0x33ff\r
	msr	cptr_el2, x0			// Disable copro. traps to EL2\r
\r
	msr	hstr_el2, xzr			// Disable CP15 traps to EL2\r
\r
#endif // START_EL1\r
\r
        /* Configure UART. Primary CPU only */\r
	mrs     x4, mpidr_el1\r
	tst     x4, #15\r
	b.ne    1f\r
\r
	/*\r
	 * UART initialisation (38400 8N1)\r
	 */\r
	ldr     x4, =UART_BASE                  // UART base\r
	mov     w5, #0x10                       // ibrd\r
	str     w5, [x4, #0x24]\r
	mov     w5, #0xc300\r
	orr     w5, w5, #0x0001                 // cr\r
	str     w5, [x4, #0x30]\r
\r
	/*\r
	 * Prepare the switch to the EL2_SP2 mode from EL3\r
	 */\r
1:	ldr	x0, =start_ns			// Return after mode switch\r
#if defined START_EL1\r
	mov	x1, #0x3c5			// EL1_SP1 | D | A | I | F\r
#else\r
	mov	x1, #0x3c9			// EL2_SP2 | D | A | I | F\r
#endif\r
\r
	msr	elr_el3, x0\r
	msr	spsr_el3, x1\r
	eret\r
\r
#endif // START_EL2\r
\r
\r
start_ns:\r
\r
/*\r
 * We do not have NOR flash on the Foundation model. So run UEFI from RAM.\r
 * On the full model we use the NOR FLASH to store UEFI, so start there.\r
 */\r
#if defined FOUNDATION_MODEL\r
	mov	x0, #0xa0000000\r
#else\r
	mov	x0, #0x0\r
#endif\r
	br	x0\r
\r
	.ltorg\r
\r
	.org	0x200\r
Commit	Line	Data
e6f3ed43 LL	1	/*\r
	2	* boot.S - simple register setup code for junping to a second stage bootloader\r
	3	*\r
	4	* Copyright (C) 2011-2013 ARM Limited.\r
	5	* All rights reserved.\r
	6	*\r
	7	* Redistribution and use in source and binary forms, with or without\r
	8	* modification, are permitted provided that the following conditions are\r
	9	* met:\r
	10	*\r
	11	* * Redistributions of source code must retain the above copyright\r
	12	* notice, this list of conditions and the following disclaimer.\r
	13	* * Redistributions in binary form must reproduce the above copyright\r
	14	* notice, this list of conditions and the following disclaimer in\r
	15	* the documentation and/or other materials provided with the\r
	16	* distribution.\r
	17	* * Neither the name of ARM nor the names of its contributors may be\r
	18	* used to endorse or promote products derived from this software\r
	19	* without specific prior written permission.\r
	20	*\r
	21	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS\r
	22	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
	23	* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
	24	* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
	25	* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
	26	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
	27	* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
	28	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
	29	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
	30	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
	31	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
	32	*\r
	33	* This license can also be found in the LICENSE.TXT file.\r
	34	*/\r
	35	\r
	36	.text\r
	37	\r
	38	.globl _start\r
	39	\r
	40	.set LED_ADDR, 0x1c010008\r
	41	\r
	42	_start:\r
	43	/*\r
	44	* EL3 initialisation\r
	45	*/\r
	46	\r
	47	// Set LED to show progress.\r
	48	ldr x1, =LED_ADDR\r
	49	mov w0, #0x1\r
	50	str w0, [x1]\r
	51	dsb sy\r
	52	\r
	53	#if defined START_EL2\r
	54	\r
	55	mrs x0, CurrentEL\r
	56	cmp x0, #0xc // EL3?\r
	57	b.ne start_ns // skip EL3 initialisation\r
	58	\r
	59	mov x0, #0x30 // RES1\r
	60	orr x0, x0, #(1 << 0) // Non-secure bit\r
	61	orr x0, x0, #(1 << 8) // HVC enable\r
	62	orr x0, x0, #(1 << 10) // 64-bit EL2\r
	63	msr scr_el3, x0\r
	64	\r
65	msr cptr_el3, xzr // Disable copro. traps to EL3\r
66	\r
67	ldr x0, =CNTFRQ\r
68	msr cntfrq_el0, x0\r
69	\r
70	/*\r
71	* Check for the primary CPU to avoid a race on the distributor\r
72	* registers.\r
73	*/\r
74	mrs x0, mpidr_el1\r
75	tst x0, #15\r
76	b.ne 1f // secondary CPU\r
77	\r
78	ldr x1, =GIC_DIST_BASE // GICD_CTLR\r
79	mov w0, #3 // EnableGrp0 \| EnableGrp1\r
80	str w0, [x1]\r
81	\r
82	1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR\r
83	mov w0, #~0 // Grp1 interrupts\r
84	str w0, [x1], #4\r
85	b.ne 2f // Only local interrupts for secondary CPUs\r
86	str w0, [x1], #4\r
87	str w0, [x1], #4\r
88	\r
89	2: ldr x1, =GIC_CPU_BASE // GICC_CTLR\r
90	ldr w0, [x1]\r
91	orr w0, w0, #3 // EnableGrp0 \| EnableGrp1\r
92	str w0, [x1]\r
93	\r
94	mov w0, #1 << 7 // allow NS access to GICC_PMR\r
95	str w0, [x1, #4] // GICC_PMR\r
96	\r
97	msr sctlr_el2, xzr\r
98	\r
99	#if defined START_EL1\r
100	\r
101	/* Now setup our EL1. Controlled by EL2 config on Model */\r
102	mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
103	orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
104	\r
105	// Send all interrupts to their respective Exception levels for EL2\r
106	bic x0, x0, #(1 << 3) // Disable virtual FIQ\r
107	bic x0, x0, #(1 << 4) // Disable virtual IRQ\r
108	bic x0, x0, #(1 << 5) // Disable virtual SError and Abort\r
109	msr hcr_el2, x0 // Write back our settings\r
110	\r
111	/*\r
112	* Enable architected timer access\r
113	*/\r
114	mrs x0, cnthctl_el2\r
115	orr x0, x0, #3 // Enable EL1 access to timers\r
116	msr cnthctl_el2, x0\r
117	\r
118	mrs x0, cntkctl_el1\r
119	orr x0, x0, #3 // EL0 access to counters\r
120	msr cntkctl_el1, x0\r
121	\r
122	/* Set ID regs */\r
123	mrs x0, midr_el1\r
124	mrs x1, mpidr_el1\r
125	msr vpidr_el2, x0\r
126	msr vmpidr_el2, x1\r
127	\r
128	/* Coprocessor traps. */\r
129	mov x0, #0x33ff\r
130	msr cptr_el2, x0 // Disable copro. traps to EL2\r
131	\r
132	msr hstr_el2, xzr // Disable CP15 traps to EL2\r
133	\r
134	#endif // START_EL1\r
135	\r
136	/* Configure UART. Primary CPU only */\r
137	mrs x4, mpidr_el1\r
138	tst x4, #15\r
139	b.ne 1f\r
140	\r
141	/*\r
142	* UART initialisation (38400 8N1)\r
143	*/\r
144	ldr x4, =UART_BASE // UART base\r
145	mov w5, #0x10 // ibrd\r
146	str w5, [x4, #0x24]\r
147	mov w5, #0xc300\r
148	orr w5, w5, #0x0001 // cr\r
149	str w5, [x4, #0x30]\r
150	\r
151	/*\r
152	* Prepare the switch to the EL2_SP2 mode from EL3\r
153	*/\r
154	1: ldr x0, =start_ns // Return after mode switch\r
155	#if defined START_EL1\r
156	mov x1, #0x3c5 // EL1_SP1 \| D \| A \| I \| F\r
157	#else\r
158	mov x1, #0x3c9 // EL2_SP2 \| D \| A \| I \| F\r
159	#endif\r
160	\r
161	msr elr_el3, x0\r
162	msr spsr_el3, x1\r
163	eret\r
164	\r
165	#endif // START_EL2\r
166	\r
167	\r
168	start_ns:\r
169	\r
170	/*\r
171	* We do not have NOR flash on the Foundation model. So run UEFI from RAM.\r
172	* On the full model we use the NOR FLASH to store UEFI, so start there.\r
173	*/\r
174	#if defined FOUNDATION_MODEL\r
175	mov x0, #0xa0000000\r
176	#else\r
177	mov x0, #0x0\r
178	#endif\r
179	br x0\r
180	\r
181	.ltorg\r
182	\r
183	.org 0x200\r