projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| a36d531f MC |
1 | #\r |
| 2 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r | |
| 3 | #\r | |
| 4 | # This program and the accompanying materials\r | |
| 5 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 6 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 7 | # http://opensource.org/licenses/bsd-license.php\r | |
| 8 | #\r | |
| 9 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 10 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 11 | #\r | |
| 12 | #\r | |
| 13 | \r | |
| 14 | #include <AsmMacroIoLibV8.h>\r | |
| 15 | #include <Base.h>\r | |
| 16 | #include <Library/ArmLib.h>\r | |
| 17 | #include <Library/PcdLib.h>\r | |
| 18 | #include <AutoGen.h>\r | |
| 19 | \r | |
| 20 | .text\r | |
| 21 | .align 2\r | |
| 22 | \r | |
| 23 | GCC_ASM_EXPORT(ArmPlatformPeiBootAction)\r | |
| 24 | GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore)\r | |
| 25 | GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId)\r | |
| 26 | GCC_ASM_EXPORT(ArmPlatformGetCorePosition)\r | |
| 27 | GCC_ASM_EXPORT(ArmGetPhysAddrTop)\r | |
| 28 | \r | |
| 29 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCore)\r | |
| 30 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask)\r | |
| 31 | GCC_ASM_IMPORT(_gPcd_FixedAtBuild_PcdCoreCount)\r | |
| 32 | \r | |
| 33 | ASM_PFX(ArmPlatformPeiBootAction):\r | |
| 34 | ret\r | |
| 35 | \r | |
| 36 | //UINTN\r | |
| 37 | //ArmPlatformGetPrimaryCoreMpId (\r | |
| 38 | // VOID\r | |
| 39 | // );\r | |
| 40 | ASM_PFX(ArmPlatformGetPrimaryCoreMpId):\r | |
| 41 | LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, x0)\r | |
| 42 | ldrh w0, [x0]\r | |
| 43 | ret\r | |
| 44 | \r | |
| 45 | //UINTN\r | |
| 46 | //ArmPlatformIsPrimaryCore (\r | |
| 47 | // IN UINTN MpId\r | |
| 48 | // );\r | |
| 49 | ASM_PFX(ArmPlatformIsPrimaryCore):\r | |
| 50 | mov x0, #1\r | |
| 51 | ret\r | |
| 52 | \r | |
| 53 | //UINTN\r | |
| 54 | //ArmPlatformGetCorePosition (\r | |
| 55 | // IN UINTN MpId\r | |
| 56 | // );\r | |
| 57 | // With this function: CorePos = (ClusterId * 4) + CoreId\r | |
| 58 | ASM_PFX(ArmPlatformGetCorePosition):\r | |
| 59 | and x1, x0, #ARM_CORE_MASK\r | |
| 60 | and x0, x0, #ARM_CLUSTER_MASK\r | |
| 61 | add x0, x1, x0, LSR #6\r | |
| 62 | ret\r | |
| 63 | \r | |
| 64 | //EFI_PHYSICAL_ADDRESS\r | |
| 65 | //GetPhysAddrTop (\r | |
| 66 | // VOID\r | |
| 67 | // );\r | |
| 68 | ASM_PFX(ArmGetPhysAddrTop):\r | |
| 69 | mrs x0, id_aa64mmfr0_el1\r | |
| 70 | adr x1, .LPARanges\r | |
| 71 | and x0, x0, #7\r | |
| 72 | ldrb w1, [x1, x0]\r | |
| 73 | mov x0, #1\r | |
| 74 | lsl x0, x0, x1\r | |
| 75 | ret\r | |
| 76 | \r | |
| 77 | //\r | |
| 78 | // Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the\r | |
| 79 | // physical address space support on this CPU:\r | |
| 80 | // 0 == 32 bits, 1 == 36 bits, etc etc\r | |
| 81 | // 6 and 7 are reserved\r | |
| 82 | //\r | |
| 83 | .LPARanges:\r | |
| 84 | .byte 32, 36, 40, 42, 44, 48, -1, -1\r | |
| 85 | \r | |
| 86 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |