projects / mirror_edk2.git / blame
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| 9595e3cd | 1 | /** @file\r |
| d1c561f9 | 2 | The Header file of the Pci Host Bridge Driver\r |
| 9595e3cd LE |
3 | \r |
| 4 | Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR>\r | |
| 5 | This program and the accompanying materials are\r | |
| 6 | licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | http://opensource.org/licenses/bsd-license.php\r | |
| d1c561f9 | 9 | \r |
| 9595e3cd LE |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | \r | |
| d1c561f9 | 13 | **/\r |
| 9595e3cd LE |
14 | \r |
| 15 | #ifndef _PCI_HOST_BRIDGE_H_\r | |
| 16 | #define _PCI_HOST_BRIDGE_H_\r | |
| 17 | \r | |
| 18 | #include <PiDxe.h>\r | |
| 19 | \r | |
| 20 | #include <IndustryStandard/Pci.h>\r | |
| 21 | #include <IndustryStandard/Acpi.h>\r | |
| 22 | \r | |
| 23 | #include <Protocol/PciHostBridgeResourceAllocation.h>\r | |
| 24 | #include <Protocol/PciRootBridgeIo.h>\r | |
| 25 | #include <Protocol/Metronome.h>\r | |
| 26 | #include <Protocol/DevicePath.h>\r | |
| 27 | \r | |
| 28 | \r | |
| 29 | #include <Library/BaseLib.h>\r | |
| 30 | #include <Library/DebugLib.h>\r | |
| 31 | #include <Library/BaseMemoryLib.h>\r | |
| 32 | #include <Library/MemoryAllocationLib.h>\r | |
| 33 | #include <Library/UefiLib.h>\r | |
| 34 | #include <Library/UefiBootServicesTableLib.h>\r | |
| 35 | #include <Library/DxeServicesTableLib.h>\r | |
| 36 | #include <Library/DevicePathLib.h>\r | |
| 37 | #include <Library/IoLib.h>\r | |
| 38 | #include <Library/PciLib.h>\r | |
| aca7e8b6 | 39 | #include <Library/PcdLib.h>\r |
| 9595e3cd LE |
40 | \r |
| 41 | //\r | |
| 42 | // Hard code the host bridge number in the platform.\r | |
| 43 | // In this chipset, there is only one host bridge.\r | |
| 44 | //\r | |
| 45 | #define HOST_BRIDGE_NUMBER 1\r | |
| 46 | \r | |
| 47 | #define MAX_PCI_DEVICE_NUMBER 31\r | |
| 48 | #define MAX_PCI_FUNCTION_NUMBER 7\r | |
| e1ec934c | 49 | #define MAX_PCI_REG_ADDRESS (SIZE_4KB - 1)\r |
| 9595e3cd LE |
50 | \r |
| 51 | typedef enum {\r | |
| 52 | IoOperation,\r | |
| 53 | MemOperation,\r | |
| 54 | PciOperation\r | |
| 55 | } OPERATION_TYPE;\r | |
| 56 | \r | |
| 57 | #define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')\r | |
| 58 | typedef struct {\r | |
| 59 | UINTN Signature;\r | |
| 60 | EFI_HANDLE HostBridgeHandle;\r | |
| 61 | UINTN RootBridgeNumber;\r | |
| 62 | LIST_ENTRY Head;\r | |
| d1c561f9 OM |
63 | BOOLEAN ResourceSubmited;\r |
| 64 | BOOLEAN CanRestarted;\r | |
| 9595e3cd LE |
65 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;\r |
| 66 | } PCI_HOST_BRIDGE_INSTANCE;\r | |
| 67 | \r | |
| 68 | #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \\r | |
| 69 | CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)\r | |
| d1c561f9 | 70 | \r |
| 9595e3cd LE |
71 | //\r |
| 72 | // HostBridge Resource Allocation interface\r | |
| 73 | //\r | |
| 74 | \r | |
| 75 | /**\r | |
| 76 | These are the notifications from the PCI bus driver that it is about to enter a certain\r | |
| 77 | phase of the PCI enumeration process.\r | |
| 78 | \r | |
| 79 | This member function can be used to notify the host bridge driver to perform specific actions,\r | |
| 80 | including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r | |
| 81 | Eight notification points are defined at this time. See belows:\r | |
| 82 | EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r | |
| 83 | structures. The PCI enumerator should issue this notification\r | |
| 84 | before starting a fresh enumeration process. Enumeration cannot\r | |
| 85 | be restarted after sending any other notification such as\r | |
| 86 | EfiPciHostBridgeBeginBusAllocation.\r | |
| 87 | EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r | |
| 88 | required here. This notification can be used to perform any\r | |
| 89 | chipset-specific programming.\r | |
| 90 | EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r | |
| 91 | specific action is required here. This notification can be used to\r | |
| 92 | perform any chipset-specific programming.\r | |
| 93 | EfiPciHostBridgeBeginResourceAllocation\r | |
| 94 | The resource allocation phase is about to begin. No specific\r | |
| 95 | action is required here. This notification can be used to perform\r | |
| 96 | any chipset-specific programming.\r | |
| 97 | EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r | |
| 98 | root bridges. These resource settings are returned on the next call to\r | |
| 99 | GetProposedResources(). Before calling NotifyPhase() with a Phase of\r | |
| 100 | EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r | |
| 101 | for gathering I/O and memory requests for\r | |
| 102 | all the PCI root bridges and submitting these requests using\r | |
| 103 | SubmitResources(). This function pads the resource amount\r | |
| 104 | to suit the root bridge hardware, takes care of dependencies between\r | |
| 105 | the PCI root bridges, and calls the Global Coherency Domain (GCD)\r | |
| 106 | with the allocation request. In the case of padding, the allocated range\r | |
| 107 | could be bigger than what was requested.\r | |
| 108 | EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r | |
| 109 | resources (proposed resources) for all the PCI root bridges. After the\r | |
| 110 | hardware is programmed, reassigning resources will not be supported.\r | |
| 111 | The bus settings are not affected.\r | |
| 112 | EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r | |
| 113 | root bridges and resets the I/O and memory apertures to their initial\r | |
| 114 | state. The bus settings are not affected. If the request to allocate\r | |
| 115 | resources fails, the PCI enumerator can use this notification to\r | |
| 116 | deallocate previous resources, adjust the requests, and retry\r | |
| 117 | allocation.\r | |
| 118 | EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r | |
| 119 | required here. This notification can be used to perform any chipsetspecific\r | |
| 120 | programming.\r | |
| 121 | \r | |
| 122 | @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 123 | @param[in] Phase The phase during enumeration\r | |
| 124 | \r | |
| 125 | @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r | |
| 126 | is valid for a Phase of EfiPciHostBridgeAllocateResources if\r | |
| 127 | SubmitResources() has not been called for one or more\r | |
| 128 | PCI root bridges before this call\r | |
| 129 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r | |
| 130 | for a Phase of EfiPciHostBridgeSetResources.\r | |
| 131 | @retval EFI_INVALID_PARAMETER Invalid phase parameter\r | |
| 132 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
| 133 | This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r | |
| 134 | previously submitted resource requests cannot be fulfilled or\r | |
| 135 | were only partially fulfilled.\r | |
| 136 | @retval EFI_SUCCESS The notification was accepted without any errors.\r | |
| 137 | \r | |
| 138 | **/\r | |
| 139 | EFI_STATUS\r | |
| 140 | EFIAPI\r | |
| 141 | NotifyPhase(\r | |
| 142 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 143 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r | |
| 144 | );\r | |
| 145 | \r | |
| 146 | /**\r | |
| 147 | Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r | |
| 148 | \r | |
| 149 | This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r | |
| 150 | are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r | |
| 151 | root bridges. On each call, the handle that was returned by the previous call is passed into the\r | |
| 152 | interface, and on output the interface returns the device handle of the next PCI root bridge. The\r | |
| 153 | caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
| 154 | for that root bridge. When there are no more PCI root bridges to report, the interface returns\r | |
| 155 | EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r | |
| 156 | are returned by this function.\r | |
| 157 | For D945 implementation, there is only one root bridge in PCI host bridge.\r | |
| 158 | \r | |
| 159 | @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 160 | @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r | |
| d1c561f9 | 161 | \r |
| 9595e3cd | 162 | @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r |
| d1c561f9 | 163 | specific Host bridge and return EFI_SUCCESS.\r |
| 9595e3cd LE |
164 | @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.\r |
| 165 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r | |
| 166 | returned on a previous call to GetNextRootBridge().\r | |
| 167 | **/\r | |
| 168 | EFI_STATUS\r | |
| 169 | EFIAPI\r | |
| 170 | GetNextRootBridge(\r | |
| 171 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 172 | IN OUT EFI_HANDLE *RootBridgeHandle\r | |
| 173 | );\r | |
| d1c561f9 | 174 | \r |
| 9595e3cd LE |
175 | /**\r |
| 176 | Returns the allocation attributes of a PCI root bridge.\r | |
| 177 | \r | |
| 178 | The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r | |
| 179 | from one PCI root bridge to another. These attributes are different from the decode-related\r | |
| 180 | attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r | |
| 181 | RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r | |
| 182 | handles of all the root bridges that are associated with this host bridge must be obtained by calling\r | |
| 183 | GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r | |
| 184 | after the enumeration process. The hardware may provide mechanisms to change the attributes on\r | |
| d1c561f9 | 185 | the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is\r |
| 9595e3cd LE |
186 | installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r |
| 187 | "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r | |
| d1c561f9 OM |
188 | For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to\r |
| 189 | include requests for the prefetchable memory in the nonprefetchable memory pool and not request any\r | |
| 9595e3cd LE |
190 | prefetchable memory.\r |
| 191 | Attribute Description\r | |
| 192 | ------------------------------------ ----------------------------------------------------------------------\r | |
| 193 | EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate\r | |
| 194 | windows for nonprefetchable and prefetchable memory. A PCI bus\r | |
| 195 | driver needs to include requests for prefetchable memory in the\r | |
| 196 | nonprefetchable memory pool.\r | |
| 197 | \r | |
| 198 | EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory\r | |
| 199 | windows. If this bit is not set, the PCI bus driver needs to include\r | |
| 200 | requests for a 64-bit memory address in the corresponding 32-bit\r | |
| 201 | memory pool.\r | |
| 202 | \r | |
| 203 | @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
| 204 | @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type\r | |
| 205 | EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r | |
| 206 | @param[out] Attributes The pointer to attribte of root bridge, it is output parameter\r | |
| d1c561f9 | 207 | \r |
| 9595e3cd LE |
208 | @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r |
| 209 | @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r | |
| 210 | @retval EFI_SUCCESS Success to get attribute of interested root bridge.\r | |
| 211 | \r | |
| d1c561f9 | 212 | **/\r |
| 9595e3cd LE |
213 | EFI_STATUS\r |
| 214 | EFIAPI\r | |
| 215 | GetAttributes(\r | |
| 216 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 217 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 218 | OUT UINT64 *Attributes\r | |
| 219 | );\r | |
| d1c561f9 | 220 | \r |
| 9595e3cd LE |
221 | /**\r |
| 222 | Sets up the specified PCI root bridge for the bus enumeration process.\r | |
| 223 | \r | |
| 224 | This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r | |
| 225 | over which the search should be performed in ACPI 2.0 resource descriptor format.\r | |
| 226 | \r | |
| 227 | @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r | |
| 228 | @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r | |
| 229 | @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r | |
| d1c561f9 | 230 | \r |
| 9595e3cd LE |
231 | @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r |
| 232 | @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r | |
| 233 | @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r | |
| 234 | \r | |
| 235 | **/\r | |
| 236 | EFI_STATUS\r | |
| 237 | EFIAPI\r | |
| 238 | StartBusEnumeration(\r | |
| 239 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 240 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 241 | OUT VOID **Configuration\r | |
| 242 | );\r | |
| d1c561f9 | 243 | \r |
| 9595e3cd LE |
244 | /**\r |
| 245 | Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r | |
| 246 | \r | |
| 247 | This member function programs the specified PCI root bridge to decode the bus range that is\r | |
| 248 | specified by the input parameter Configuration.\r | |
| 249 | The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r | |
| 250 | \r | |
| 251 | @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r | |
| 252 | @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed\r | |
| 253 | @param[in] Configuration The pointer to the PCI bus resource descriptor\r | |
| d1c561f9 | 254 | \r |
| 9595e3cd LE |
255 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r |
| 256 | @retval EFI_INVALID_PARAMETER Configuration is NULL.\r | |
| 257 | @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r | |
| 258 | @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r | |
| d1c561f9 | 259 | @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than\r |
| 9595e3cd LE |
260 | bus descriptors.\r |
| 261 | @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.\r | |
| 262 | @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r | |
| 263 | @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r | |
| 264 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r | |
| 265 | @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r | |
| 266 | \r | |
| 267 | **/\r | |
| 268 | EFI_STATUS\r | |
| 269 | EFIAPI\r | |
| 270 | SetBusNumbers(\r | |
| 271 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 272 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 273 | IN VOID *Configuration\r | |
| 274 | );\r | |
| d1c561f9 | 275 | \r |
| 9595e3cd LE |
276 | /**\r |
| 277 | Submits the I/O and memory resource requirements for the specified PCI root bridge.\r | |
| 278 | \r | |
| 279 | This function is used to submit all the I/O and memory resources that are required by the specified\r | |
| 280 | PCI root bridge. The input parameter Configuration is used to specify the following:\r | |
| 281 | - The various types of resources that are required\r | |
| 282 | - The associated lengths in terms of ACPI 2.0 resource descriptor format\r | |
| 283 | \r | |
| 284 | @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r | |
| 285 | @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.\r | |
| 286 | @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r | |
| d1c561f9 | 287 | \r |
| 9595e3cd LE |
288 | @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.\r |
| 289 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r | |
| 290 | @retval EFI_INVALID_PARAMETER Configuration is NULL.\r | |
| 291 | @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r | |
| d1c561f9 OM |
292 | @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are\r |
| 293 | not supported by this PCI root bridge. This error will happen if the caller\r | |
| 9595e3cd LE |
294 | did not combine resources according to Attributes that were returned by\r |
| 295 | GetAllocAttributes().\r | |
| 296 | @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r | |
| 297 | @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r | |
| 298 | @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r | |
| 299 | \r | |
| 300 | **/\r | |
| 301 | EFI_STATUS\r | |
| 302 | EFIAPI\r | |
| 303 | SubmitResources(\r | |
| 304 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 305 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 306 | IN VOID *Configuration\r | |
| 307 | );\r | |
| d1c561f9 | 308 | \r |
| 9595e3cd LE |
309 | /**\r |
| 310 | Returns the proposed resource settings for the specified PCI root bridge.\r | |
| 311 | \r | |
| 312 | This member function returns the proposed resource settings for the specified PCI root bridge. The\r | |
| 313 | proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r | |
| 314 | EfiPciHostBridgeAllocateResources. The output parameter Configuration\r | |
| 315 | specifies the following:\r | |
| 316 | - The various types of resources, excluding bus resources, that are allocated\r | |
| 317 | - The associated lengths in terms of ACPI 2.0 resource descriptor format\r | |
| 318 | \r | |
| 319 | @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r | |
| 320 | @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r | |
| 321 | @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r | |
| d1c561f9 | 322 | \r |
| 9595e3cd LE |
323 | @retval EFI_SUCCESS The requested parameters were returned.\r |
| 324 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r | |
| 325 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r | |
| 326 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
| 327 | \r | |
| 328 | **/\r | |
| 329 | EFI_STATUS\r | |
| 330 | EFIAPI\r | |
| 331 | GetProposedResources(\r | |
| 332 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 333 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 334 | OUT VOID **Configuration\r | |
| 335 | );\r | |
| 336 | \r | |
| 337 | /**\r | |
| 338 | Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r | |
| 339 | stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r | |
| 340 | PCI controllers before enumeration.\r | |
| 341 | \r | |
| 342 | This function is called during the PCI enumeration process. No specific action is expected from this\r | |
| 343 | member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r | |
| 344 | enumeration.\r | |
| 345 | \r | |
| 346 | @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r | |
| 347 | @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r | |
| 348 | InstallProtocolInterface() in the UEFI 2.0 Specification.\r | |
| 349 | @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the\r | |
| 350 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r | |
| 351 | configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r | |
| 352 | the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r | |
| d1c561f9 OM |
353 | @param Phase The phase of the PCI device enumeration.\r |
| 354 | \r | |
| 9595e3cd LE |
355 | @retval EFI_SUCCESS The requested parameters were returned.\r |
| 356 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r | |
| 357 | @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r | |
| 358 | EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r | |
| 359 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r | |
| 360 | not enumerate this device, including its child devices if it is a PCI-to-PCI\r | |
| 361 | bridge.\r | |
| 362 | \r | |
| 363 | **/\r | |
| 364 | EFI_STATUS\r | |
| 365 | EFIAPI\r | |
| 366 | PreprocessController (\r | |
| 367 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
| 368 | IN EFI_HANDLE RootBridgeHandle,\r | |
| 369 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r | |
| 370 | IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r | |
| 371 | );\r | |
| 372 | \r | |
| 373 | \r | |
| 374 | //\r | |
| d1c561f9 | 375 | // Define resource status constant\r |
| 9595e3cd LE |
376 | //\r |
| 377 | #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL\r | |
| 378 | #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL\r | |
| 379 | \r | |
| 380 | \r | |
| 381 | //\r | |
| 382 | // Driver Instance Data Prototypes\r | |
| 383 | //\r | |
| 384 | \r | |
| 385 | typedef struct {\r | |
| 386 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r | |
| 387 | UINTN NumberOfBytes;\r | |
| 388 | UINTN NumberOfPages;\r | |
| 389 | EFI_PHYSICAL_ADDRESS HostAddress;\r | |
| 390 | EFI_PHYSICAL_ADDRESS MappedHostAddress;\r | |
| 391 | } MAP_INFO;\r | |
| 392 | \r | |
| 393 | typedef struct {\r | |
| 394 | ACPI_HID_DEVICE_PATH AcpiDevicePath;\r | |
| 395 | EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r | |
| 396 | } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;\r | |
| 397 | \r | |
| 398 | typedef struct {\r | |
| 399 | UINT64 BusBase;\r | |
| d1c561f9 OM |
400 | UINT64 BusLimit;\r |
| 401 | \r | |
| 402 | UINT64 MemBase;\r | |
| 403 | UINT64 MemLimit;\r | |
| 404 | \r | |
| 405 | UINT64 IoBase;\r | |
| 406 | UINT64 IoLimit;\r | |
| aca7e8b6 | 407 | UINT64 IoTranslation;\r |
| 9595e3cd LE |
408 | } PCI_ROOT_BRIDGE_RESOURCE_APERTURE;\r |
| 409 | \r | |
| 410 | typedef enum {\r | |
| 411 | TypeIo = 0,\r | |
| 412 | TypeMem32,\r | |
| 413 | TypePMem32,\r | |
| 414 | TypeMem64,\r | |
| 415 | TypePMem64,\r | |
| 416 | TypeBus,\r | |
| 417 | TypeMax\r | |
| 418 | } PCI_RESOURCE_TYPE;\r | |
| 419 | \r | |
| 420 | typedef enum {\r | |
| 421 | ResNone = 0,\r | |
| 422 | ResSubmitted,\r | |
| 423 | ResRequested,\r | |
| 424 | ResAllocated,\r | |
| 425 | ResStatusMax\r | |
| 426 | } RES_STATUS;\r | |
| 427 | \r | |
| 428 | typedef struct {\r | |
| 429 | PCI_RESOURCE_TYPE Type;\r | |
| 430 | UINT64 Base;\r | |
| 431 | UINT64 Length;\r | |
| 432 | UINT64 Alignment;\r | |
| 433 | RES_STATUS Status;\r | |
| 434 | } PCI_RES_NODE;\r | |
| 435 | \r | |
| 436 | #define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')\r | |
| 437 | \r | |
| 438 | typedef struct {\r | |
| 439 | UINT32 Signature;\r | |
| 440 | LIST_ENTRY Link;\r | |
| 441 | EFI_HANDLE Handle;\r | |
| 442 | UINT64 RootBridgeAttrib;\r | |
| 443 | UINT64 Attributes;\r | |
| 444 | UINT64 Supports;\r | |
| d1c561f9 | 445 | \r |
| 9595e3cd LE |
446 | //\r |
| 447 | // Specific for this memory controller: Bus, I/O, Mem\r | |
| 448 | //\r | |
| 449 | PCI_RES_NODE ResAllocNode[6];\r | |
| d1c561f9 | 450 | \r |
| 9595e3cd LE |
451 | //\r |
| 452 | // Addressing for Memory and I/O and Bus arrange\r | |
| 453 | //\r | |
| 454 | UINT64 BusBase;\r | |
| d1c561f9 OM |
455 | UINT64 MemBase;\r |
| 456 | UINT64 IoBase;\r | |
| 457 | UINT64 BusLimit;\r | |
| 458 | UINT64 MemLimit;\r | |
| 459 | UINT64 IoLimit;\r | |
| 1275aaf4 | 460 | UINT64 IoTranslation;\r |
| 9595e3cd LE |
461 | \r |
| 462 | EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r | |
| 463 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r | |
| 464 | \r | |
| 465 | } PCI_ROOT_BRIDGE_INSTANCE;\r | |
| 466 | \r | |
| 467 | \r | |
| 468 | //\r | |
| 469 | // Driver Instance Data Macros\r | |
| 470 | //\r | |
| 471 | #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r | |
| 472 | CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)\r | |
| 473 | \r | |
| 474 | \r | |
| 475 | #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \\r | |
| 476 | CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)\r | |
| 477 | \r | |
| 478 | /**\r | |
| 479 | \r | |
| 480 | Construct the Pci Root Bridge Io protocol\r | |
| 481 | \r | |
| 482 | @param Protocol Point to protocol instance\r | |
| 483 | @param HostBridgeHandle Handle of host bridge\r | |
| 484 | @param Attri Attribute of host bridge\r | |
| 485 | @param ResAperture ResourceAperture for host bridge\r | |
| 486 | \r | |
| 487 | @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r | |
| 488 | \r | |
| 489 | **/\r | |
| 490 | EFI_STATUS\r | |
| 491 | RootBridgeConstructor (\r | |
| 492 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r | |
| 493 | IN EFI_HANDLE HostBridgeHandle,\r | |
| 494 | IN UINT64 Attri,\r | |
| 495 | IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture\r | |
| 496 | );\r | |
| 497 | \r | |
| 498 | #endif\r |