[mirror_edk2.git] / ArmPlatformPkg / Drivers / LcdGraphicsOutputDxe / HdLcd.h

/** @file  HDLcd.h\r
\r
 Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
 http://opensource.org/licenses/bsd-license.php\r
\r
 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
 **/\r
\r
#ifndef _HDLCD_H_\r
#define _HDLCD_H_\r
\r
//\r
// HDLCD Controller Register Offsets\r
//\r
\r
#define HDLCD_REG_VERSION                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
#define HDLCD_REG_INT_RAWSTAT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
#define HDLCD_REG_INT_CLEAR               ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
#define HDLCD_REG_INT_MASK                ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)\r
#define HDLCD_REG_INT_STATUS              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)\r
#define HDLCD_REG_FB_BASE                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)\r
#define HDLCD_REG_FB_LINE_LENGTH          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)\r
#define HDLCD_REG_FB_LINE_COUNT           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)\r
#define HDLCD_REG_FB_LINE_PITCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)\r
#define HDLCD_REG_BUS_OPTIONS             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)\r
#define HDLCD_REG_V_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)\r
#define HDLCD_REG_V_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)\r
#define HDLCD_REG_V_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)\r
#define HDLCD_REG_V_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)\r
#define HDLCD_REG_H_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)\r
#define HDLCD_REG_H_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)\r
#define HDLCD_REG_H_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)\r
#define HDLCD_REG_H_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)\r
#define HDLCD_REG_POLARITIES              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)\r
#define HDLCD_REG_COMMAND                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)\r
#define HDLCD_REG_PIXEL_FORMAT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)\r
#define HDLCD_REG_RED_SELECT              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)\r
#define HDLCD_REG_GREEN_SELECT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
#define HDLCD_REG_BLUE_SELECT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
\r
\r
//\r
// HDLCD Values of registers\r
//\r
\r
// HDLCD Interrupt mask, clear and status register\r
#define HDLCD_DMA_END                     BIT0    /* DMA has finished reading a frame */\r
#define HDLCD_BUS_ERROR                   BIT1    /* DMA bus error */\r
#define HDLCD_SYNC                        BIT2    /* Vertical sync */\r
#define HDLCD_UNDERRUN                    BIT3    /* No Data available while DATAEN active */\r
\r
// CLCD_CONTROL Control register\r
#define HDLCD_DISABLE                     0\r
#define HDLCD_ENABLE                      BIT0\r
\r
// Bus Options\r
#define HDLCD_BURST_1                     BIT0\r
#define HDLCD_BURST_2                     BIT1\r
#define HDLCD_BURST_4                     BIT2\r
#define HDLCD_BURST_8                     BIT3\r
#define HDLCD_BURST_16                    BIT4\r
\r
// Polarities - HIGH\r
#define HDLCD_VSYNC_HIGH                  BIT0\r
#define HDLCD_HSYNC_HIGH                  BIT1\r
#define HDLCD_DATEN_HIGH                  BIT2\r
#define HDLCD_DATA_HIGH                   BIT3\r
#define HDLCD_PXCLK_HIGH                  BIT4\r
// Polarities - LOW (for completion and for ease of understanding the hardware settings)\r
#define HDLCD_VSYNC_LOW                   0\r
#define HDLCD_HSYNC_LOW                   0\r
#define HDLCD_DATEN_LOW                   0\r
#define HDLCD_DATA_LOW                    0\r
#define HDLCD_PXCLK_LOW                   0\r
\r
// Pixel Format\r
#define HDLCD_LITTLE_ENDIAN              (0 << 31)\r
#define HDLCD_BIG_ENDIAN                 (1 << 31)\r
\r
// Number of bytes per pixel\r
#define HDLCD_4BYTES_PER_PIXEL           ((4 - 1) << 3)\r
\r
#endif /* _HDLCD_H_ */\r
Commit	Line	Data
f8c9f1c1	1	/** @file HDLcd.h\r
	2	\r
	3	Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
	4	\r
	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#ifndef _HDLCD_H_\r
	16	#define _HDLCD_H_\r
	17	\r
	18	//\r
	19	// HDLCD Controller Register Offsets\r
	20	//\r
	21	\r
	22	#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
	23	#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
	24	#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
	25	#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)\r
	26	#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)\r
	27	#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)\r
	28	#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)\r
	29	#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)\r
	30	#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)\r
	31	#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)\r
	32	#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)\r
	33	#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)\r
	34	#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)\r
	35	#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)\r
	36	#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)\r
	37	#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)\r
	38	#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)\r
	39	#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)\r
	40	#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)\r
	41	#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)\r
	42	#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)\r
	43	#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)\r
	44	#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
	45	#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
	46	\r
	47	\r
	48	//\r
	49	// HDLCD Values of registers\r
	50	//\r
	51	\r
	52	// HDLCD Interrupt mask, clear and status register\r
	53	#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */\r
	54	#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */\r
	55	#define HDLCD_SYNC BIT2 /* Vertical sync */\r
	56	#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */\r
	57	\r
	58	// CLCD_CONTROL Control register\r
	59	#define HDLCD_DISABLE 0\r
	60	#define HDLCD_ENABLE BIT0\r
	61	\r
	62	// Bus Options\r
	63	#define HDLCD_BURST_1 BIT0\r
	64	#define HDLCD_BURST_2 BIT1\r
65	#define HDLCD_BURST_4 BIT2\r
66	#define HDLCD_BURST_8 BIT3\r
67	#define HDLCD_BURST_16 BIT4\r
68	\r
69	// Polarities - HIGH\r
70	#define HDLCD_VSYNC_HIGH BIT0\r
71	#define HDLCD_HSYNC_HIGH BIT1\r
72	#define HDLCD_DATEN_HIGH BIT2\r
73	#define HDLCD_DATA_HIGH BIT3\r
74	#define HDLCD_PXCLK_HIGH BIT4\r
75	// Polarities - LOW (for completion and for ease of understanding the hardware settings)\r
76	#define HDLCD_VSYNC_LOW 0\r
77	#define HDLCD_HSYNC_LOW 0\r
78	#define HDLCD_DATEN_LOW 0\r
79	#define HDLCD_DATA_LOW 0\r
80	#define HDLCD_PXCLK_LOW 0\r
81	\r
82	// Pixel Format\r
83	#define HDLCD_LITTLE_ENDIAN (0 << 31)\r
84	#define HDLCD_BIG_ENDIAN (1 << 31)\r
85	\r
86	// Number of bytes per pixel\r
87	#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)\r
88	\r
89	#endif /* _HDLCD_H_ */\r