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[mirror_edk2.git] / ArmPlatformPkg / Drivers / NorFlashDxe / NorFlashDxe.h
CommitLineData
1d5d0ae9 1/** @file NorFlashDxe.h
2
68dda854 3 Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>
4
1d5d0ae9 5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15#ifndef __NOR_FLASH_DXE_H__
16#define __NOR_FLASH_DXE_H__
17
18
19#include <Base.h>
20#include <PiDxe.h>
21
22#include <Protocol/BlockIo.h>
23#include <Protocol/FirmwareVolumeBlock.h>
24
d5e12da4 25#include <Library/DebugLib.h>
26#include <Library/IoLib.h>
27#include <Library/NorFlashPlatformLib.h>
28#include <Library/UefiLib.h>
29
68dda854 30#define NOR_FLASH_ERASE_RETRY 10
1d5d0ae9 31
1d5d0ae9 32// Device access macros
33// These are necessary because we use 2 x 16bit parts to make up 32bit data
34
68dda854 35#define HIGH_16_BITS 0xFFFF0000
36#define LOW_16_BITS 0x0000FFFF
37#define LOW_8_BITS 0x000000FF
38
1d5d0ae9 39#define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16_BITS ) )
40
41#define GET_LOW_BYTE(value) ( value & LOW_8_BITS )
42#define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) )
43
44// Each command must be sent simultaneously to both chips,
45// i.e. at the lower 16 bits AND at the higher 16 bits
d5e12da4 46#define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ((BaseAddr) + ((OffsetAddr) << 2))
1d5d0ae9 47#define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd & LOW_16_BITS) )
68dda854 48#define SEND_NOR_COMMAND(BaseAddr,Offset,Cmd) MmioWrite32 (CREATE_NOR_ADDRESS(BaseAddr,Offset), CREATE_DUAL_CMD(Cmd))
d5e12da4 49#define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) )
1d5d0ae9 50
51// Status Register Bits
d5e12da4 52#define P30_SR_BIT_WRITE (BIT7 << 16 | BIT7)
53#define P30_SR_BIT_ERASE_SUSPEND (BIT6 << 16 | BIT6)
54#define P30_SR_BIT_ERASE (BIT5 << 16 | BIT5)
55#define P30_SR_BIT_PROGRAM (BIT4 << 16 | BIT4)
56#define P30_SR_BIT_VPP (BIT3 << 16 | BIT3)
57#define P30_SR_BIT_PROGRAM_SUSPEND (BIT2 << 16 | BIT2)
58#define P30_SR_BIT_BLOCK_LOCKED (BIT1 << 16 | BIT1)
59#define P30_SR_BIT_BEFP (BIT0 << 16 | BIT0)
1d5d0ae9 60
61// Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family
62
63// On chip buffer size for buffered programming operations
64// There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word is 2 bytes.
65// Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes
66#define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128)
67#define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4))
68#define MAX_BUFFERED_PROG_ITERATIONS 10000000
69#define BOUNDARY_OF_32_WORDS 0x7F
70
71// CFI Addresses
72#define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10
73#define P30_CFI_ADDR_VENDOR_ID 0x13
74
75// CFI Data
76#define CFI_QRY 0x00595251
77
78// READ Commands
79#define P30_CMD_READ_DEVICE_ID 0x0090
80#define P30_CMD_READ_STATUS_REGISTER 0x0070
81#define P30_CMD_CLEAR_STATUS_REGISTER 0x0050
82#define P30_CMD_READ_ARRAY 0x00FF
83#define P30_CMD_READ_CFI_QUERY 0x0098
84
85// WRITE Commands
86#define P30_CMD_WORD_PROGRAM_SETUP 0x0040
87#define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010
88#define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8
89#define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0
90#define P30_CMD_BEFP_SETUP 0x0080
91#define P30_CMD_BEFP_CONFIRM 0x00D0
92
93// ERASE Commands
94#define P30_CMD_BLOCK_ERASE_SETUP 0x0020
95#define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0
96
97// SUSPEND Commands
98#define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0
99#define P30_CMD_SUSPEND_RESUME 0x00D0
100
101// BLOCK LOCKING / UNLOCKING Commands
102#define P30_CMD_LOCK_BLOCK_SETUP 0x0060
103#define P30_CMD_LOCK_BLOCK 0x0001
104#define P30_CMD_UNLOCK_BLOCK 0x00D0
105#define P30_CMD_LOCK_DOWN_BLOCK 0x002F
106
107// PROTECTION Commands
108#define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0
109
110// CONFIGURATION Commands
111#define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060
112#define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003
113
114#define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
115#define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
116#define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
117
118typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
119
120typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
121
1d5d0ae9 122typedef struct {
123 VENDOR_DEVICE_PATH Vendor;
124 EFI_DEVICE_PATH_PROTOCOL End;
125} NOR_FLASH_DEVICE_PATH;
126
127struct _NOR_FLASH_INSTANCE {
128 UINT32 Signature;
129 EFI_HANDLE Handle;
130
131 BOOLEAN Initialized;
132 NOR_FLASH_INITIALIZE Initialize;
133
68dda854 134 UINTN DeviceBaseAddress;
135 UINTN RegionBaseAddress;
1d5d0ae9 136 UINTN Size;
d5e12da4 137 EFI_LBA StartLba;
1d5d0ae9 138
139 EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
140 EFI_BLOCK_IO_MEDIA Media;
141
142 BOOLEAN SupportFvb;
143 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
144
145 NOR_FLASH_DEVICE_PATH DevicePath;
146};
147
1d5d0ae9 148EFI_STATUS
149NorFlashReadCfiData (
68dda854 150 IN UINTN DeviceBaseAddress,
151 IN UINTN CFI_Offset,
152 IN UINT32 NumberOfBytes,
1d5d0ae9 153 OUT UINT32 *Data
68dda854 154 );
1d5d0ae9 155
156EFI_STATUS
157NorFlashWriteBuffer (
68dda854 158 IN NOR_FLASH_INSTANCE *Instance,
159 IN UINTN TargetAddress,
160 IN UINTN BufferSizeInBytes,
161 IN UINT32 *Buffer
162 );
1d5d0ae9 163
164//
165// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
166//
167EFI_STATUS
168EFIAPI
169NorFlashBlockIoReset (
170 IN EFI_BLOCK_IO_PROTOCOL *This,
171 IN BOOLEAN ExtendedVerification
172 );
173
174//
175// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
176//
177EFI_STATUS
178EFIAPI
179NorFlashBlockIoReadBlocks (
180 IN EFI_BLOCK_IO_PROTOCOL *This,
181 IN UINT32 MediaId,
182 IN EFI_LBA Lba,
183 IN UINTN BufferSizeInBytes,
184 OUT VOID *Buffer
185);
186
187//
188// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
189//
190EFI_STATUS
191EFIAPI
192NorFlashBlockIoWriteBlocks (
193 IN EFI_BLOCK_IO_PROTOCOL *This,
194 IN UINT32 MediaId,
195 IN EFI_LBA Lba,
196 IN UINTN BufferSizeInBytes,
197 IN VOID *Buffer
198);
199
200//
201// BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
202//
203EFI_STATUS
204EFIAPI
205NorFlashBlockIoFlushBlocks (
206 IN EFI_BLOCK_IO_PROTOCOL *This
207);
208
209
210//
211// NorFlashFvbDxe.c
212//
213
214EFI_STATUS
215EFIAPI
216NorFlashFvbInitialize (
217 IN NOR_FLASH_INSTANCE* Instance
68dda854 218 );
1d5d0ae9 219
220EFI_STATUS
221EFIAPI
222FvbGetAttributes(
223 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
224 OUT EFI_FVB_ATTRIBUTES_2 *Attributes
68dda854 225 );
1d5d0ae9 226
227EFI_STATUS
228EFIAPI
229FvbSetAttributes(
230 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
231 IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
68dda854 232 );
1d5d0ae9 233
234EFI_STATUS
235EFIAPI
236FvbGetPhysicalAddress(
237 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
238 OUT EFI_PHYSICAL_ADDRESS *Address
68dda854 239 );
1d5d0ae9 240
241EFI_STATUS
242EFIAPI
243FvbGetBlockSize(
244 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
245 IN EFI_LBA Lba,
246 OUT UINTN *BlockSize,
247 OUT UINTN *NumberOfBlocks
68dda854 248 );
1d5d0ae9 249
250EFI_STATUS
251EFIAPI
252FvbRead(
253 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
254 IN EFI_LBA Lba,
255 IN UINTN Offset,
256 IN OUT UINTN *NumBytes,
257 IN OUT UINT8 *Buffer
68dda854 258 );
1d5d0ae9 259
260EFI_STATUS
261EFIAPI
262FvbWrite(
263 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
264 IN EFI_LBA Lba,
265 IN UINTN Offset,
266 IN OUT UINTN *NumBytes,
267 IN UINT8 *Buffer
68dda854 268 );
1d5d0ae9 269
270EFI_STATUS
271EFIAPI
272FvbEraseBlocks(
273 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
274 ...
68dda854 275 );
1d5d0ae9 276
277//
278// NorFlashDxe.c
279//
280
281EFI_STATUS
68dda854 282NorFlashUnlockAndEraseSingleBlock (
283 IN NOR_FLASH_INSTANCE *Instance,
284 IN UINTN BlockAddress
285 );
1d5d0ae9 286
287EFI_STATUS
288NorFlashWriteSingleBlock (
68dda854 289 IN NOR_FLASH_INSTANCE *Instance,
290 IN EFI_LBA Lba,
291 IN UINT32 *DataBuffer,
292 IN UINT32 BlockSizeInWords
293 );
1d5d0ae9 294
295EFI_STATUS
296NorFlashWriteBlocks (
297 IN NOR_FLASH_INSTANCE *Instance,
298 IN EFI_LBA Lba,
299 IN UINTN BufferSizeInBytes,
300 IN VOID *Buffer
68dda854 301 );
1d5d0ae9 302
303EFI_STATUS
304NorFlashReadBlocks (
68dda854 305 IN NOR_FLASH_INSTANCE *Instance,
306 IN EFI_LBA Lba,
307 IN UINTN BufferSizeInBytes,
308 OUT VOID *Buffer
309 );
1d5d0ae9 310
311EFI_STATUS
312NorFlashReset (
313 IN NOR_FLASH_INSTANCE *Instance
68dda854 314 );
1d5d0ae9 315
316#endif /* __NOR_FLASH_DXE_H__ */