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0f4386e7 | 1 | /** @file\r |
2 | *\r | |
18ee5b6d | 3 | * Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r |
0f4386e7 | 4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | \r | |
16 | #ifndef __PL031_REAL_TIME_CLOCK_H__\r | |
17 | #define __PL031_REAL_TIME_CLOCK_H__\r | |
18 | \r | |
0f4386e7 | 19 | // PL031 Registers\r |
18ee5b6d OM |
20 | #define PL031_RTC_DR_DATA_REGISTER 0x000\r |
21 | #define PL031_RTC_MR_MATCH_REGISTER 0x004\r | |
22 | #define PL031_RTC_LR_LOAD_REGISTER 0x008\r | |
23 | #define PL031_RTC_CR_CONTROL_REGISTER 0x00C\r | |
24 | #define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010\r | |
25 | #define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014\r | |
26 | #define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018\r | |
27 | #define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C\r | |
28 | #define PL031_RTC_PERIPH_ID0 0xFE0\r | |
29 | #define PL031_RTC_PERIPH_ID1 0xFE4\r | |
30 | #define PL031_RTC_PERIPH_ID2 0xFE8\r | |
31 | #define PL031_RTC_PERIPH_ID3 0xFEC\r | |
32 | #define PL031_RTC_PCELL_ID0 0xFF0\r | |
33 | #define PL031_RTC_PCELL_ID1 0xFF4\r | |
34 | #define PL031_RTC_PCELL_ID2 0xFF8\r | |
35 | #define PL031_RTC_PCELL_ID3 0xFFC\r | |
0f4386e7 | 36 | \r |
37 | // PL031 Values\r | |
38 | #define PL031_RTC_ENABLED 0x00000001\r | |
39 | #define PL031_SET_IRQ_MASK 0x00000001\r | |
40 | #define PL031_IRQ_TRIGGERED 0x00000001\r | |
41 | #define PL031_CLEAR_IRQ 0x00000001\r | |
42 | \r | |
43 | #define PL031_COUNTS_PER_SECOND 1\r | |
44 | \r | |
0f4386e7 | 45 | #endif\r |