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1 | /** @file\r |
| 2 | *\r |
| 3 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 4 | * \r |
| 5 | * This program and the accompanying materials \r |
| 6 | * are licensed and made available under the terms and conditions of the BSD License \r |
| 7 | * which accompanies this distribution. The full text of the license may be found at \r |
| 8 | * http://opensource.org/licenses/bsd-license.php \r |
| 9 | *\r |
| 10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 12 | *\r |
| 13 | **/\r |
| 14 | \r |
| 15 | \r |
| 16 | #ifndef _SP804_TIMER_H__\r |
| 17 | #define _SP804_TIMER_H__\r |
| 18 | \r |
| 19 | // SP804 Timer constants\r |
| 20 | #define SP804_TIMER_LOAD_REG 0x00\r |
| 21 | #define SP804_TIMER_CURRENT_REG 0x04\r |
| 22 | #define SP804_TIMER_CONTROL_REG 0x08\r |
| 23 | #define SP804_TIMER_INT_CLR_REG 0x0C\r |
| 24 | #define SP804_TIMER_RAW_INT_STS_REG 0x10\r |
| 25 | #define SP804_TIMER_MSK_INT_STS_REG 0x14\r |
| 26 | #define SP804_TIMER_BG_LOAD_REG 0x18\r |
| 27 | \r |
| 28 | // Timer control register bit definitions\r |
| 29 | #define SP804_TIMER_CTRL_ONESHOT BIT0\r |
| 30 | #define SP804_TIMER_CTRL_32BIT BIT1\r |
| 31 | #define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)\r |
| 32 | #define SP804_PRESCALE_DIV_1 0\r |
| 33 | #define SP804_PRESCALE_DIV_16 BIT2\r |
| 34 | #define SP804_PRESCALE_DIV_256 BIT3\r |
| 35 | #define SP804_TIMER_CTRL_INT_ENABLE BIT5\r |
| 36 | #define SP804_TIMER_CTRL_PERIODIC BIT6\r |
| 37 | #define SP804_TIMER_CTRL_ENABLE BIT7\r |
| 38 | \r |
| 39 | // SP810 System Controller constants\r |
| 40 | #define SP810_SYS_CTRL_REG 0x00\r |
| 41 | #define SP810_SYS_CTRL_TIMER0_TIMCLK BIT15 // 0=REFCLK, 1=TIMCLK\r |
| 42 | #define SP810_SYS_CTRL_TIMER0_EN BIT16\r |
| 43 | #define SP810_SYS_CTRL_TIMER1_TIMCLK BIT17 // 0=REFCLK, 1=TIMCLK\r |
| 44 | #define SP810_SYS_CTRL_TIMER1_EN BIT18\r |
| 45 | #define SP810_SYS_CTRL_TIMER2_TIMCLK BIT19 // 0=REFCLK, 1=TIMCLK\r |
| 46 | #define SP810_SYS_CTRL_TIMER2_EN BIT20\r |
| 47 | #define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK\r |
| 48 | #define SP810_SYS_CTRL_TIMER3_EN BIT22\r |
| 49 | \r |
| 50 | #endif\r |
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