[mirror_edk2.git] / ArmPlatformPkg / Library / ArmMaliDp / ArmMaliDp.c

/** @file\r
\r
  ARM Mali DP 500/550/650 display controller driver\r
\r
  Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <Library/DebugLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/LcdHwLib.h>\r
#include <Library/LcdPlatformLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
#include "ArmMaliDp.h"\r
\r
// CORE_ID of the MALI DP\r
STATIC UINT32  mDpDeviceId;\r
\r
/** Disable the graphics layer\r
\r
  This is done by clearing the EN bit of the LG_CONTROL register.\r
**/\r
STATIC\r
VOID\r
LayerGraphicsDisable (\r
  VOID\r
  )\r
{\r
  MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE);\r
}\r
\r
/** Enable the graphics layer\r
\r
  This is done by setting the EN bit of the LG_CONTROL register.\r
**/\r
STATIC\r
VOID\r
LayerGraphicsEnable (\r
  VOID\r
  )\r
{\r
  MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE);\r
}\r
\r
/** Set the frame address of the graphics layer.\r
\r
  @param[in]  FrameBaseAddress     Address of the data buffer to be used as\r
                                   a framebuffer.\r
**/\r
STATIC\r
VOID\r
LayerGraphicsSetFrame (\r
  IN CONST EFI_PHYSICAL_ADDRESS  FrameBaseAddress\r
  )\r
{\r
  // Disable the graphics layer.\r
  LayerGraphicsDisable ();\r
\r
  // Set up memory address of the data buffer for graphics layer.\r
  // write lower bits of the address.\r
  MmioWrite32 (\r
    DP_BASE + DP_DE_LG_PTR_LOW,\r
    DP_DE_LG_PTR_LOW_MASK & FrameBaseAddress\r
    );\r
\r
  // Write higher bits of the address.\r
  MmioWrite32 (\r
    DP_BASE + DP_DE_LG_PTR_HIGH,\r
    (UINT32)(FrameBaseAddress >> DP_DE_LG_PTR_HIGH_SHIFT)\r
    );\r
\r
  // Enable the graphics layer.\r
  LayerGraphicsEnable ();\r
}\r
\r
/** Configures various graphics layer characteristics.\r
\r
  @param[in] UefiGfxPixelFormat  This must be either\r
                                 PixelBlueGreenRedReserved8BitPerColor\r
                                 OR\r
                                 PixelRedGreenBlueReserved8BitPerColor\r
  @param[in] HRes                Horizontal resolution of the graphics layer.\r
  @param[in] VRes                Vertical resolution of the graphics layer.\r
**/\r
STATIC\r
VOID\r
LayerGraphicsConfig (\r
  IN CONST EFI_GRAPHICS_PIXEL_FORMAT  UefiGfxPixelFormat,\r
  IN CONST UINT32                     HRes,\r
  IN CONST UINT32                     VRes\r
  )\r
{\r
  UINT32  PixelFormat;\r
\r
  // Disable the graphics layer before configuring any settings.\r
  LayerGraphicsDisable ();\r
\r
  // Setup graphics layer size.\r
  MmioWrite32 (DP_BASE + DP_DE_LG_IN_SIZE, FRAME_IN_SIZE (HRes, VRes));\r
\r
  // Setup graphics layer composition size.\r
  MmioWrite32 (DP_BASE + DP_DE_LG_CMP_SIZE, FRAME_CMP_SIZE (HRes, VRes));\r
\r
  // Setup memory stride (total visible pixels on a line * 4).\r
  MmioWrite32 (DP_BASE + DP_DE_LG_H_STRIDE, (HRes * sizeof (UINT32)));\r
\r
  // Set the format.\r
\r
  // In PixelBlueGreenRedReserved8BitPerColor format, byte 0 represents blue,\r
  // byte 1 represents green, byte 2 represents red, and byte 3 is reserved\r
  // which is equivalent to XRGB format of the DP500/DP550/DP650. Whereas\r
  // PixelRedGreenBlueReserved8BitPerColor is equivalent to XBGR of the\r
  // DP500/DP550/DP650.\r
  if (UefiGfxPixelFormat == PixelBlueGreenRedReserved8BitPerColor) {\r
    PixelFormat = (mDpDeviceId == MALIDP_500) ? DP_PIXEL_FORMAT_DP500_XRGB_8888\r
                     : DP_PIXEL_FORMAT_XRGB_8888;\r
  } else {\r
    PixelFormat = (mDpDeviceId == MALIDP_500) ? DP_PIXEL_FORMAT_DP500_XBGR_8888\r
                     : DP_PIXEL_FORMAT_XBGR_8888;\r
  }\r
\r
  MmioWrite32 (DP_BASE + DP_DE_LG_FORMAT, PixelFormat);\r
\r
  // Enable graphics layer.\r
  LayerGraphicsEnable ();\r
}\r
\r
/** Configure timing information of the display.\r
\r
  @param[in] Horizontal           Pointer to horizontal timing parameters.\r
                                  (Resolution, Sync, Back porch, Front porch)\r
  @param[in] Vertical             Pointer to vertical timing parameters.\r
                                  (Resolution, Sync, Back porch, Front porch)\r
**/\r
STATIC\r
VOID\r
SetDisplayEngineTiming (\r
  IN CONST SCAN_TIMINGS *CONST  Horizontal,\r
  IN CONST SCAN_TIMINGS *CONST  Vertical\r
  )\r
{\r
  UINTN  RegHIntervals;\r
  UINTN  RegVIntervals;\r
  UINTN  RegSyncControl;\r
  UINTN  RegHVActiveSize;\r
\r
  if (mDpDeviceId == MALIDP_500) {\r
    // MALI DP500 timing registers.\r
    RegHIntervals   = DP_BASE + DP_DE_DP500_H_INTERVALS;\r
    RegVIntervals   = DP_BASE + DP_DE_DP500_V_INTERVALS;\r
    RegSyncControl  = DP_BASE + DP_DE_DP500_SYNC_CONTROL;\r
    RegHVActiveSize = DP_BASE + DP_DE_DP500_HV_ACTIVESIZE;\r
  } else {\r
    // MALI DP550/DP650 timing registers.\r
    RegHIntervals   = DP_BASE + DP_DE_H_INTERVALS;\r
    RegVIntervals   = DP_BASE + DP_DE_V_INTERVALS;\r
    RegSyncControl  = DP_BASE + DP_DE_SYNC_CONTROL;\r
    RegHVActiveSize = DP_BASE + DP_DE_HV_ACTIVESIZE;\r
  }\r
\r
  // Horizontal back porch and front porch.\r
  MmioWrite32 (\r
    RegHIntervals,\r
    H_INTERVALS (Horizontal->FrontPorch, Horizontal->BackPorch)\r
    );\r
\r
  // Vertical back porch and front porch.\r
  MmioWrite32 (\r
    RegVIntervals,\r
    V_INTERVALS (Vertical->FrontPorch, Vertical->BackPorch)\r
    );\r
\r
  // Sync control, Horizontal and Vertical sync.\r
  MmioWrite32 (\r
    RegSyncControl,\r
    SYNC_WIDTH (Horizontal->Sync, Vertical->Sync)\r
    );\r
\r
  // Set up Horizontal and Vertical area size.\r
  MmioWrite32 (\r
    RegHVActiveSize,\r
    HV_ACTIVE (Horizontal->Resolution, Vertical->Resolution)\r
    );\r
}\r
\r
/** Return CORE_ID of the ARM Mali DP.\r
\r
  @retval 0xFFF                  No Mali DP found.\r
  @retval 0x500                  Mali DP core id for DP500.\r
  @retval 0x550                  Mali DP core id for DP550.\r
  @retval 0x650                  Mali DP core id for DP650.\r
**/\r
STATIC\r
UINT32\r
ArmMaliDpGetCoreId (\r
  )\r
{\r
  UINT32  DpCoreId;\r
\r
  // First check for DP500 as register offset for DP550/DP650 CORE_ID\r
  // is beyond 3K/4K register space of the DP500.\r
  DpCoreId   = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID);\r
  DpCoreId >>= DP_DE_DP500_CORE_ID_SHIFT;\r
\r
  if (DpCoreId == MALIDP_500) {\r
    return DpCoreId;\r
  }\r
\r
  // Check for DP550 or DP650.\r
  DpCoreId   = MmioRead32 (DP_BASE + DP_DC_CORE_ID);\r
  DpCoreId >>= DP_DC_CORE_ID_SHIFT;\r
\r
  if ((DpCoreId == MALIDP_550) || (DpCoreId == MALIDP_650)) {\r
    return DpCoreId;\r
  }\r
\r
  return MALIDP_NOT_PRESENT;\r
}\r
\r
/** Check for presence of MALI.\r
\r
  This function returns success if the platform implements\r
  DP500/DP550/DP650 ARM Mali display processor.\r
\r
  @retval EFI_SUCCESS           DP500/DP550/DP650 display processor found\r
                                on the platform.\r
  @retval EFI_NOT_FOUND         DP500/DP550/DP650 display processor not found\r
                                on the platform.\r
**/\r
EFI_STATUS\r
LcdIdentify (\r
  VOID\r
  )\r
{\r
  DEBUG ((\r
    DEBUG_WARN,\r
    "Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n",\r
    DP_BASE\r
    ));\r
\r
  if (mDpDeviceId == 0) {\r
    mDpDeviceId = ArmMaliDpGetCoreId ();\r
  }\r
\r
  if (mDpDeviceId == MALIDP_NOT_PRESENT) {\r
    DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n"));\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId));\r
  return EFI_SUCCESS;\r
}\r
\r
/** Initialize platform display.\r
\r
  @param[in]  FrameBaseAddress       Address of the frame buffer.\r
\r
  @retval EFI_SUCCESS                Display initialization successful.\r
  @retval !(EFI_SUCCESS)             Display initialization failure.\r
**/\r
EFI_STATUS\r
LcdInitialize (\r
  IN CONST EFI_PHYSICAL_ADDRESS  FrameBaseAddress\r
  )\r
{\r
  DEBUG ((DEBUG_WARN, "Framebuffer base address = %p\n", FrameBaseAddress));\r
\r
  if (mDpDeviceId == 0) {\r
    mDpDeviceId = ArmMaliDpGetCoreId ();\r
  }\r
\r
  if (mDpDeviceId == MALIDP_NOT_PRESENT) {\r
    DEBUG ((\r
      DEBUG_ERROR,\r
      "ARM Mali DP initialization failed,"\r
      "no ARM Mali DP present\n"\r
      ));\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  // We are using graphics layer of the Mali DP as a main framebuffer.\r
  LayerGraphicsSetFrame (FrameBaseAddress);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/** Set ARM Mali DP in cofiguration mode.\r
\r
  The ARM Mali DP must be in the configuration mode for\r
  configuration of the H_INTERVALS, V_INTERVALS, SYNC_CONTROL\r
  and HV_ACTIVESIZE.\r
**/\r
STATIC\r
VOID\r
SetConfigurationMode (\r
  VOID\r
  )\r
{\r
  // Request configuration Mode.\r
  if (mDpDeviceId == MALIDP_500) {\r
    MmioOr32 (DP_BASE + DP_DE_DP500_CONTROL, DP_DE_DP500_CONTROL_CONFIG_REQ);\r
  } else {\r
    MmioOr32 (DP_BASE + DP_DC_CONTROL, DP_DC_CONTROL_CM_ACTIVE);\r
  }\r
}\r
\r
/** Set ARM Mali DP in normal mode.\r
\r
  Normal mode is the main operating mode of the display processor\r
  in which display layer data is fetched from framebuffer and\r
  displayed.\r
**/\r
STATIC\r
VOID\r
SetNormalMode (\r
  VOID\r
  )\r
{\r
  // Disable configuration Mode.\r
  if (mDpDeviceId == MALIDP_500) {\r
    MmioAnd32 (DP_BASE + DP_DE_DP500_CONTROL, ~DP_DE_DP500_CONTROL_CONFIG_REQ);\r
  } else {\r
    MmioAnd32 (DP_BASE + DP_DC_CONTROL, ~DP_DC_CONTROL_CM_ACTIVE);\r
  }\r
}\r
\r
/** Set the global configuration valid flag.\r
\r
  Any new configuration parameters written to the display engine are not\r
  activated until the global configuration valid flag is set in the\r
  CONFIG_VALID register.\r
**/\r
STATIC\r
VOID\r
SetConfigValid (\r
  VOID\r
  )\r
{\r
  if (mDpDeviceId == MALIDP_500) {\r
    MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID);\r
  } else {\r
    MmioOr32 (DP_BASE + DP_DC_CONFIG_VALID, DP_DC_CONFIG_VALID);\r
  }\r
}\r
\r
/** Set requested mode of the display.\r
\r
  @param[in]  ModeNumber             Display mode number.\r
\r
  @retval EFI_SUCCESS                Display mode set successful.\r
  @retval EFI_DEVICE_ERROR           Display mode not found/supported.\r
**/\r
EFI_STATUS\r
LcdSetMode (\r
  IN CONST UINT32  ModeNumber\r
  )\r
{\r
  EFI_STATUS    Status;\r
  SCAN_TIMINGS  *Horizontal;\r
  SCAN_TIMINGS  *Vertical;\r
\r
  EFI_GRAPHICS_OUTPUT_MODE_INFORMATION  ModeInfo;\r
\r
  // Get the display mode timings and other relevant information.\r
  Status = LcdPlatformGetTimings (\r
             ModeNumber,\r
             &Horizontal,\r
             &Vertical\r
             );\r
  if (EFI_ERROR (Status)) {\r
    ASSERT_EFI_ERROR (Status);\r
    return Status;\r
  }\r
\r
  ASSERT (Horizontal != NULL);\r
  ASSERT (Vertical != NULL);\r
\r
  // Get the pixel format information.\r
  Status = LcdPlatformQueryMode (ModeNumber, &ModeInfo);\r
  if (EFI_ERROR (Status)) {\r
    ASSERT_EFI_ERROR (Status);\r
    return Status;\r
  }\r
\r
  // Request configuration mode.\r
  SetConfigurationMode ();\r
\r
  // Configure the graphics layer.\r
  LayerGraphicsConfig (\r
    ModeInfo.PixelFormat,\r
    Horizontal->Resolution,\r
    Vertical->Resolution\r
    );\r
\r
  // Set the display engine timings.\r
  SetDisplayEngineTiming (Horizontal, Vertical);\r
\r
  // After configuration, set Mali DP in normal mode.\r
  SetNormalMode ();\r
\r
  // Any parameters written to the display engine are not activated until\r
  // CONFIG_VALID is set.\r
  SetConfigValid ();\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/** This function de-initializes the display.\r
\r
**/\r
VOID\r
LcdShutdown (\r
  VOID\r
  )\r
{\r
  // Disable graphics layer.\r
  LayerGraphicsDisable ();\r
}\r
Commit	Line	Data
b99f8126 GP	1	/** @file\r
	2	\r
	3	ARM Mali DP 500/550/650 display controller driver\r
	4	\r
	5	Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>\r
	6	\r
f4dfad05	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
b99f8126 GP	8	\r
	9	**/\r
	10	\r
	11	#include <Library/DebugLib.h>\r
	12	#include <Library/IoLib.h>\r
	13	#include <Library/LcdHwLib.h>\r
	14	#include <Library/LcdPlatformLib.h>\r
	15	#include <Library/MemoryAllocationLib.h>\r
	16	\r
	17	#include "ArmMaliDp.h"\r
	18	\r
	19	// CORE_ID of the MALI DP\r
40b0b23e	20	STATIC UINT32 mDpDeviceId;\r
b99f8126 GP	21	\r
	22	/** Disable the graphics layer\r
	23	\r
	24	This is done by clearing the EN bit of the LG_CONTROL register.\r
	25	**/\r
	26	STATIC\r
	27	VOID\r
40b0b23e MK	28	LayerGraphicsDisable (\r
	29	VOID\r
	30	)\r
b99f8126 GP	31	{\r
	32	MmioAnd32 (DP_BASE + DP_DE_LG_CONTROL, ~DP_DE_LG_ENABLE);\r
	33	}\r
	34	\r
	35	/** Enable the graphics layer\r
	36	\r
	37	This is done by setting the EN bit of the LG_CONTROL register.\r
	38	**/\r
	39	STATIC\r
	40	VOID\r
40b0b23e MK	41	LayerGraphicsEnable (\r
	42	VOID\r
	43	)\r
b99f8126 GP	44	{\r
	45	MmioOr32 (DP_BASE + DP_DE_LG_CONTROL, DP_DE_LG_ENABLE);\r
	46	}\r
	47	\r
	48	/** Set the frame address of the graphics layer.\r
	49	\r
	50	@param[in] FrameBaseAddress Address of the data buffer to be used as\r
	51	a framebuffer.\r
	52	**/\r
	53	STATIC\r
	54	VOID\r
	55	LayerGraphicsSetFrame (\r
40b0b23e	56	IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress\r
b99f8126 GP	57	)\r
	58	{\r
	59	// Disable the graphics layer.\r
	60	LayerGraphicsDisable ();\r
	61	\r
	62	// Set up memory address of the data buffer for graphics layer.\r
	63	// write lower bits of the address.\r
	64	MmioWrite32 (\r
	65	DP_BASE + DP_DE_LG_PTR_LOW,\r
	66	DP_DE_LG_PTR_LOW_MASK & FrameBaseAddress\r
	67	);\r
	68	\r
	69	// Write higher bits of the address.\r
	70	MmioWrite32 (\r
	71	DP_BASE + DP_DE_LG_PTR_HIGH,\r
	72	(UINT32)(FrameBaseAddress >> DP_DE_LG_PTR_HIGH_SHIFT)\r
	73	);\r
	74	\r
	75	// Enable the graphics layer.\r
	76	LayerGraphicsEnable ();\r
	77	}\r
	78	\r
	79	/** Configures various graphics layer characteristics.\r
	80	\r
	81	@param[in] UefiGfxPixelFormat This must be either\r
	82	PixelBlueGreenRedReserved8BitPerColor\r
	83	OR\r
	84	PixelRedGreenBlueReserved8BitPerColor\r
	85	@param[in] HRes Horizontal resolution of the graphics layer.\r
	86	@param[in] VRes Vertical resolution of the graphics layer.\r
	87	**/\r
	88	STATIC\r
	89	VOID\r
	90	LayerGraphicsConfig (\r
40b0b23e MK	91	IN CONST EFI_GRAPHICS_PIXEL_FORMAT UefiGfxPixelFormat,\r
	92	IN CONST UINT32 HRes,\r
	93	IN CONST UINT32 VRes\r
b99f8126 GP	94	)\r
b99f8126 GP	95	{\r
40b0b23e	96	UINT32 PixelFormat;\r
b99f8126 GP	97	\r
	98	// Disable the graphics layer before configuring any settings.\r
	99	LayerGraphicsDisable ();\r
	100	\r
	101	// Setup graphics layer size.\r
	102	MmioWrite32 (DP_BASE + DP_DE_LG_IN_SIZE, FRAME_IN_SIZE (HRes, VRes));\r
	103	\r
	104	// Setup graphics layer composition size.\r
	105	MmioWrite32 (DP_BASE + DP_DE_LG_CMP_SIZE, FRAME_CMP_SIZE (HRes, VRes));\r
	106	\r
	107	// Setup memory stride (total visible pixels on a line * 4).\r
	108	MmioWrite32 (DP_BASE + DP_DE_LG_H_STRIDE, (HRes * sizeof (UINT32)));\r
	109	\r
	110	// Set the format.\r
	111	\r
	112	// In PixelBlueGreenRedReserved8BitPerColor format, byte 0 represents blue,\r
	113	// byte 1 represents green, byte 2 represents red, and byte 3 is reserved\r
	114	// which is equivalent to XRGB format of the DP500/DP550/DP650. Whereas\r
	115	// PixelRedGreenBlueReserved8BitPerColor is equivalent to XBGR of the\r
	116	// DP500/DP550/DP650.\r
	117	if (UefiGfxPixelFormat == PixelBlueGreenRedReserved8BitPerColor) {\r
	118	PixelFormat = (mDpDeviceId == MALIDP_500) ? DP_PIXEL_FORMAT_DP500_XRGB_8888\r
	119	: DP_PIXEL_FORMAT_XRGB_8888;\r
	120	} else {\r
	121	PixelFormat = (mDpDeviceId == MALIDP_500) ? DP_PIXEL_FORMAT_DP500_XBGR_8888\r
	122	: DP_PIXEL_FORMAT_XBGR_8888;\r
	123	}\r
	124	\r
	125	MmioWrite32 (DP_BASE + DP_DE_LG_FORMAT, PixelFormat);\r
	126	\r
	127	// Enable graphics layer.\r
	128	LayerGraphicsEnable ();\r
	129	}\r
	130	\r
	131	/** Configure timing information of the display.\r
	132	\r
	133	@param[in] Horizontal Pointer to horizontal timing parameters.\r
	134	(Resolution, Sync, Back porch, Front porch)\r
	135	@param[in] Vertical Pointer to vertical timing parameters.\r
	136	(Resolution, Sync, Back porch, Front porch)\r
	137	**/\r
	138	STATIC\r
	139	VOID\r
	140	SetDisplayEngineTiming (\r
40b0b23e MK	141	IN CONST SCAN_TIMINGS *CONST Horizontal,\r
40b0b23e MK	142	IN CONST SCAN_TIMINGS *CONST Vertical\r
b99f8126 GP	143	)\r
b99f8126 GP	144	{\r
40b0b23e MK	145	UINTN RegHIntervals;\r
	146	UINTN RegVIntervals;\r
	147	UINTN RegSyncControl;\r
	148	UINTN RegHVActiveSize;\r
b99f8126 GP	149	\r
	150	if (mDpDeviceId == MALIDP_500) {\r
	151	// MALI DP500 timing registers.\r
40b0b23e MK	152	RegHIntervals = DP_BASE + DP_DE_DP500_H_INTERVALS;\r
	153	RegVIntervals = DP_BASE + DP_DE_DP500_V_INTERVALS;\r
	154	RegSyncControl = DP_BASE + DP_DE_DP500_SYNC_CONTROL;\r
b99f8126 GP	155	RegHVActiveSize = DP_BASE + DP_DE_DP500_HV_ACTIVESIZE;\r
	156	} else {\r
	157	// MALI DP550/DP650 timing registers.\r
40b0b23e MK	158	RegHIntervals = DP_BASE + DP_DE_H_INTERVALS;\r
	159	RegVIntervals = DP_BASE + DP_DE_V_INTERVALS;\r
	160	RegSyncControl = DP_BASE + DP_DE_SYNC_CONTROL;\r
b99f8126 GP	161	RegHVActiveSize = DP_BASE + DP_DE_HV_ACTIVESIZE;\r
	162	}\r
	163	\r
	164	// Horizontal back porch and front porch.\r
	165	MmioWrite32 (\r
	166	RegHIntervals,\r
	167	H_INTERVALS (Horizontal->FrontPorch, Horizontal->BackPorch)\r
	168	);\r
	169	\r
	170	// Vertical back porch and front porch.\r
	171	MmioWrite32 (\r
	172	RegVIntervals,\r
	173	V_INTERVALS (Vertical->FrontPorch, Vertical->BackPorch)\r
	174	);\r
	175	\r
	176	// Sync control, Horizontal and Vertical sync.\r
	177	MmioWrite32 (\r
	178	RegSyncControl,\r
	179	SYNC_WIDTH (Horizontal->Sync, Vertical->Sync)\r
	180	);\r
	181	\r
	182	// Set up Horizontal and Vertical area size.\r
	183	MmioWrite32 (\r
	184	RegHVActiveSize,\r
	185	HV_ACTIVE (Horizontal->Resolution, Vertical->Resolution)\r
	186	);\r
	187	}\r
	188	\r
	189	/** Return CORE_ID of the ARM Mali DP.\r
	190	\r
	191	@retval 0xFFF No Mali DP found.\r
	192	@retval 0x500 Mali DP core id for DP500.\r
	193	@retval 0x550 Mali DP core id for DP550.\r
	194	@retval 0x650 Mali DP core id for DP650.\r
	195	**/\r
	196	STATIC\r
	197	UINT32\r
	198	ArmMaliDpGetCoreId (\r
	199	)\r
	200	{\r
40b0b23e	201	UINT32 DpCoreId;\r
b99f8126 GP	202	\r
	203	// First check for DP500 as register offset for DP550/DP650 CORE_ID\r
	204	// is beyond 3K/4K register space of the DP500.\r
40b0b23e	205	DpCoreId = MmioRead32 (DP_BASE + DP_DE_DP500_CORE_ID);\r
b99f8126 GP	206	DpCoreId >>= DP_DE_DP500_CORE_ID_SHIFT;\r
	207	\r
	208	if (DpCoreId == MALIDP_500) {\r
	209	return DpCoreId;\r
	210	}\r
	211	\r
	212	// Check for DP550 or DP650.\r
40b0b23e	213	DpCoreId = MmioRead32 (DP_BASE + DP_DC_CORE_ID);\r
b99f8126 GP	214	DpCoreId >>= DP_DC_CORE_ID_SHIFT;\r
	215	\r
	216	if ((DpCoreId == MALIDP_550) \|\| (DpCoreId == MALIDP_650)) {\r
	217	return DpCoreId;\r
	218	}\r
	219	\r
	220	return MALIDP_NOT_PRESENT;\r
	221	}\r
	222	\r
	223	/** Check for presence of MALI.\r
	224	\r
	225	This function returns success if the platform implements\r
	226	DP500/DP550/DP650 ARM Mali display processor.\r
	227	\r
	228	@retval EFI_SUCCESS DP500/DP550/DP650 display processor found\r
	229	on the platform.\r
	230	@retval EFI_NOT_FOUND DP500/DP550/DP650 display processor not found\r
	231	on the platform.\r
	232	**/\r
	233	EFI_STATUS\r
40b0b23e MK	234	LcdIdentify (\r
	235	VOID\r
	236	)\r
b99f8126	237	{\r
40b0b23e MK	238	DEBUG ((\r
40b0b23e MK	239	DEBUG_WARN,\r
b99f8126 GP	240	"Probing ARM Mali DP500/DP550/DP650 at base address 0x%p\n",\r
	241	DP_BASE\r
	242	));\r
	243	\r
	244	if (mDpDeviceId == 0) {\r
	245	mDpDeviceId = ArmMaliDpGetCoreId ();\r
	246	}\r
	247	\r
	248	if (mDpDeviceId == MALIDP_NOT_PRESENT) {\r
40b0b23e MK	249	DEBUG ((DEBUG_WARN, "ARM Mali DP not found...\n"));\r
40b0b23e MK	250	return EFI_NOT_FOUND;\r
b99f8126 GP	251	}\r
	252	\r
	253	DEBUG ((DEBUG_WARN, "Found ARM Mali DP %x\n", mDpDeviceId));\r
	254	return EFI_SUCCESS;\r
	255	}\r
	256	\r
	257	/** Initialize platform display.\r
	258	\r
	259	@param[in] FrameBaseAddress Address of the frame buffer.\r
	260	\r
	261	@retval EFI_SUCCESS Display initialization successful.\r
	262	@retval !(EFI_SUCCESS) Display initialization failure.\r
	263	**/\r
	264	EFI_STATUS\r
	265	LcdInitialize (\r
40b0b23e	266	IN CONST EFI_PHYSICAL_ADDRESS FrameBaseAddress\r
b99f8126 GP	267	)\r
	268	{\r
	269	DEBUG ((DEBUG_WARN, "Framebuffer base address = %p\n", FrameBaseAddress));\r
	270	\r
	271	if (mDpDeviceId == 0) {\r
	272	mDpDeviceId = ArmMaliDpGetCoreId ();\r
	273	}\r
	274	\r
	275	if (mDpDeviceId == MALIDP_NOT_PRESENT) {\r
40b0b23e MK	276	DEBUG ((\r
	277	DEBUG_ERROR,\r
	278	"ARM Mali DP initialization failed,"\r
	279	"no ARM Mali DP present\n"\r
	280	));\r
b99f8126 GP	281	return EFI_NOT_FOUND;\r
	282	}\r
	283	\r
	284	// We are using graphics layer of the Mali DP as a main framebuffer.\r
	285	LayerGraphicsSetFrame (FrameBaseAddress);\r
	286	\r
	287	return EFI_SUCCESS;\r
	288	}\r
	289	\r
	290	/** Set ARM Mali DP in cofiguration mode.\r
	291	\r
	292	The ARM Mali DP must be in the configuration mode for\r
	293	configuration of the H_INTERVALS, V_INTERVALS, SYNC_CONTROL\r
	294	and HV_ACTIVESIZE.\r
	295	**/\r
	296	STATIC\r
	297	VOID\r
40b0b23e MK	298	SetConfigurationMode (\r
	299	VOID\r
	300	)\r
b99f8126 GP	301	{\r
	302	// Request configuration Mode.\r
	303	if (mDpDeviceId == MALIDP_500) {\r
	304	MmioOr32 (DP_BASE + DP_DE_DP500_CONTROL, DP_DE_DP500_CONTROL_CONFIG_REQ);\r
	305	} else {\r
	306	MmioOr32 (DP_BASE + DP_DC_CONTROL, DP_DC_CONTROL_CM_ACTIVE);\r
	307	}\r
	308	}\r
	309	\r
	310	/** Set ARM Mali DP in normal mode.\r
	311	\r
	312	Normal mode is the main operating mode of the display processor\r
	313	in which display layer data is fetched from framebuffer and\r
	314	displayed.\r
	315	**/\r
	316	STATIC\r
	317	VOID\r
40b0b23e MK	318	SetNormalMode (\r
	319	VOID\r
	320	)\r
b99f8126 GP	321	{\r
	322	// Disable configuration Mode.\r
	323	if (mDpDeviceId == MALIDP_500) {\r
	324	MmioAnd32 (DP_BASE + DP_DE_DP500_CONTROL, ~DP_DE_DP500_CONTROL_CONFIG_REQ);\r
	325	} else {\r
	326	MmioAnd32 (DP_BASE + DP_DC_CONTROL, ~DP_DC_CONTROL_CM_ACTIVE);\r
	327	}\r
	328	}\r
	329	\r
	330	/** Set the global configuration valid flag.\r
	331	\r
	332	Any new configuration parameters written to the display engine are not\r
	333	activated until the global configuration valid flag is set in the\r
	334	CONFIG_VALID register.\r
	335	**/\r
	336	STATIC\r
	337	VOID\r
40b0b23e MK	338	SetConfigValid (\r
	339	VOID\r
	340	)\r
b99f8126 GP	341	{\r
	342	if (mDpDeviceId == MALIDP_500) {\r
	343	MmioOr32 (DP_BASE + DP_DP500_CONFIG_VALID, DP_DC_CONFIG_VALID);\r
	344	} else {\r
	345	MmioOr32 (DP_BASE + DP_DC_CONFIG_VALID, DP_DC_CONFIG_VALID);\r
	346	}\r
	347	}\r
	348	\r
	349	/** Set requested mode of the display.\r
	350	\r
	351	@param[in] ModeNumber Display mode number.\r
	352	\r
	353	@retval EFI_SUCCESS Display mode set successful.\r
	354	@retval EFI_DEVICE_ERROR Display mode not found/supported.\r
	355	**/\r
	356	EFI_STATUS\r
	357	LcdSetMode (\r
	358	IN CONST UINT32 ModeNumber\r
	359	)\r
	360	{\r
	361	EFI_STATUS Status;\r
	362	SCAN_TIMINGS *Horizontal;\r
	363	SCAN_TIMINGS *Vertical;\r
	364	\r
	365	EFI_GRAPHICS_OUTPUT_MODE_INFORMATION ModeInfo;\r
	366	\r
	367	// Get the display mode timings and other relevant information.\r
	368	Status = LcdPlatformGetTimings (\r
	369	ModeNumber,\r
	370	&Horizontal,\r
	371	&Vertical\r
	372	);\r
	373	if (EFI_ERROR (Status)) {\r
	374	ASSERT_EFI_ERROR (Status);\r
	375	return Status;\r
	376	}\r
	377	\r
	378	ASSERT (Horizontal != NULL);\r
	379	ASSERT (Vertical != NULL);\r
	380	\r
	381	// Get the pixel format information.\r
	382	Status = LcdPlatformQueryMode (ModeNumber, &ModeInfo);\r
	383	if (EFI_ERROR (Status)) {\r
	384	ASSERT_EFI_ERROR (Status);\r
	385	return Status;\r
	386	}\r
	387	\r
	388	// Request configuration mode.\r
	389	SetConfigurationMode ();\r
	390	\r
	391	// Configure the graphics layer.\r
	392	LayerGraphicsConfig (\r
	393	ModeInfo.PixelFormat,\r
	394	Horizontal->Resolution,\r
	395	Vertical->Resolution\r
	396	);\r
	397	\r
	398	// Set the display engine timings.\r
	399	SetDisplayEngineTiming (Horizontal, Vertical);\r
	400	\r
	401	// After configuration, set Mali DP in normal mode.\r
	402	SetNormalMode ();\r
	403	\r
	404	// Any parameters written to the display engine are not activated until\r
405	// CONFIG_VALID is set.\r
406	SetConfigValid ();\r
407	\r
408	return EFI_SUCCESS;\r
409	}\r
410	\r
411	/** This function de-initializes the display.\r
412	\r
413	**/\r
414	VOID\r
40b0b23e MK	415	LcdShutdown (\r
	416	VOID\r
	417	)\r
b99f8126 GP	418	{\r
	419	// Disable graphics layer.\r
	420	LayerGraphicsDisable ();\r
	421	}\r