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a6caee65 1/** @file\r
2*\r
4c19ece3 3* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
a6caee65 4*\r
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12*\r
13**/\r
14\r
15#include <PiPei.h>\r
16\r
0787bc61 17#include <Library/ArmLib.h>\r
55a0d64b 18#include <Library/ArmGicLib.h>\r
2575b726 19#include <Library/ArmPlatformSecLib.h>\r
a6caee65 20#include <Library/DebugLib.h>\r
21#include <Library/PcdLib.h>\r
22#include <Library/PrintLib.h>\r
23#include <Library/SerialPortLib.h>\r
a6caee65 24\r
886f97c8 25#include <Chipset/ArmV7.h>\r
a6caee65 26\r
27// When the firmware is built as not Standalone, the secondary cores need to wait the firmware\r
28// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.\r
29VOID\r
30NonSecureWaitForFirmware (\r
31 VOID\r
32 )\r
33{\r
34 VOID (*secondary_start)(VOID);\r
35\r
36 // The secondary cores will execute the firmware once wake from WFI.\r
f92b93c9 37 secondary_start = (VOID (*)())PcdGet32(PcdFvBaseAddress);\r
a6caee65 38\r
39 ArmCallWFI();\r
40\r
41 // Acknowledge the interrupt and send End of Interrupt signal.\r
315649cd 42 ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);\r
a6caee65 43\r
44 // Jump to secondary core entry point.\r
45 secondary_start ();\r
46\r
47 // PEI Core should always load and never return\r
48 ASSERT (FALSE);\r
49}\r
50\r
51/**\r
52 Call before jumping to Normal World\r
53\r
54 This function allows the firmware platform to do extra actions before\r
55 jumping to the Normal World\r
56\r
57**/\r
58VOID\r
59ArmPlatformSecExtraAction (\r
0787bc61 60 IN UINTN MpId,\r
a6caee65 61 OUT UINTN* JumpAddress\r
62 )\r
63{\r
64 CHAR8 Buffer[100];\r
65 UINTN CharCount;\r
66\r
67 if (FeaturePcdGet (PcdStandalone) == FALSE) {\r
cfe1bb17 68\r
69 //\r
70 // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib\r
71 //\r
72\r
0787bc61 73 if (IS_PRIMARY_CORE(MpId)) {\r
f92b93c9 74 UINTN* StartAddress = (UINTN*)PcdGet32(PcdFvBaseAddress);\r
a6caee65 75\r
76 // Patch the DRAM to make an infinite loop at the start address\r
77 *StartAddress = 0xEAFFFFFE; // opcode for while(1)\r
78\r
79 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Waiting for firmware at 0x%08X ...\n\r",StartAddress);\r
80 SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
81\r
f92b93c9 82 *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
a6caee65 83 } else {\r
84 // When the primary core is stopped by the hardware debugger to copy the firmware\r
85 // into DRAM. The secondary cores are still running. As soon as the first bytes of\r
86 // the firmware are written into DRAM, the secondary cores will start to execute the\r
87 // code even if the firmware is not entirely written into the memory.\r
88 // That's why the secondary cores need to be parked in WFI and wake up once the\r
89 // firmware is ready.\r
90\r
91 *JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
92 }\r
93 } else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {\r
cfe1bb17 94\r
95 //\r
96 // Warning: This code assumes the DRAM has already been initialized by ArmPlatformSecLib\r
97 //\r
98\r
0787bc61 99 if (IS_PRIMARY_CORE(MpId)) {\r
a6caee65 100 // Signal the secondary cores they can jump to PEI phase\r
4c19ece3 101 ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
a6caee65 102\r
103 // To enter into Non Secure state, we need to make a return from exception\r
f92b93c9 104 *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
a6caee65 105 } else {\r
106 // We wait for the primary core to finish to initialize the System Memory. Otherwise the secondary\r
107 // cores would make crash the system by setting their stacks in DRAM before the primary core has not\r
108 // finished to initialize the system memory.\r
109 *JumpAddress = (UINTN)NonSecureWaitForFirmware;\r
110 }\r
111 } else {\r
f92b93c9 112 *JumpAddress = PcdGet32(PcdFvBaseAddress);\r
a6caee65 113 }\r
114}\r