[mirror_edk2.git] / ArmPlatformPkg / Library / HdLcd / HdLcd.h

/** @file\r
\r
 Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r
\r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
 **/\r
\r
#ifndef HDLCD_H_\r
#define HDLCD_H_\r
\r
// HDLCD Controller Register Offsets\r
#define HDLCD_REG_VERSION         ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
#define HDLCD_REG_INT_RAWSTAT     ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
#define HDLCD_REG_INT_CLEAR       ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
#define HDLCD_REG_INT_MASK        ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)\r
#define HDLCD_REG_INT_STATUS      ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)\r
#define HDLCD_REG_FB_BASE         ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)\r
#define HDLCD_REG_FB_LINE_LENGTH  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)\r
#define HDLCD_REG_FB_LINE_COUNT   ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)\r
#define HDLCD_REG_FB_LINE_PITCH   ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)\r
#define HDLCD_REG_BUS_OPTIONS     ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)\r
#define HDLCD_REG_V_SYNC          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)\r
#define HDLCD_REG_V_BACK_PORCH    ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)\r
#define HDLCD_REG_V_DATA          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)\r
#define HDLCD_REG_V_FRONT_PORCH   ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)\r
#define HDLCD_REG_H_SYNC          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)\r
#define HDLCD_REG_H_BACK_PORCH    ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)\r
#define HDLCD_REG_H_DATA          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)\r
#define HDLCD_REG_H_FRONT_PORCH   ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)\r
#define HDLCD_REG_POLARITIES      ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)\r
#define HDLCD_REG_COMMAND         ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)\r
#define HDLCD_REG_PIXEL_FORMAT    ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)\r
#define HDLCD_REG_RED_SELECT      ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)\r
#define HDLCD_REG_GREEN_SELECT    ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
#define HDLCD_REG_BLUE_SELECT     ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
\r
// HDLCD Values of registers\r
\r
// HDLCD Interrupt mask, clear and status register\r
#define HDLCD_DMA_END    BIT0                     /* DMA has finished reading a frame */\r
#define HDLCD_BUS_ERROR  BIT1                     /* DMA bus error */\r
#define HDLCD_SYNC       BIT2                     /* Vertical sync */\r
#define HDLCD_UNDERRUN   BIT3                     /* No Data available while DATAEN active */\r
\r
// CLCD_CONTROL Control register\r
#define HDLCD_DISABLE  0\r
#define HDLCD_ENABLE   BIT0\r
\r
// Bus Options\r
#define HDLCD_BURST_1   BIT0\r
#define HDLCD_BURST_2   BIT1\r
#define HDLCD_BURST_4   BIT2\r
#define HDLCD_BURST_8   BIT3\r
#define HDLCD_BURST_16  BIT4\r
\r
// Polarities - HIGH\r
#define HDLCD_VSYNC_HIGH  BIT0\r
#define HDLCD_HSYNC_HIGH  BIT1\r
#define HDLCD_DATEN_HIGH  BIT2\r
#define HDLCD_DATA_HIGH   BIT3\r
#define HDLCD_PXCLK_HIGH  BIT4\r
// Polarities - LOW (for completion and for ease of understanding the hardware settings)\r
#define HDLCD_VSYNC_LOW  0\r
#define HDLCD_HSYNC_LOW  0\r
#define HDLCD_DATEN_LOW  0\r
#define HDLCD_DATA_LOW   0\r
#define HDLCD_PXCLK_LOW  0\r
\r
// Default polarities\r
#define HDLCD_DEFAULT_POLARITIES  (HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH |        \\r
                                    HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW |      \\r
                                    HDLCD_VSYNC_HIGH)\r
\r
// Pixel Format\r
#define HDLCD_LITTLE_ENDIAN  (0 << 31)\r
#define HDLCD_BIG_ENDIAN     (1 << 31)\r
\r
// Number of bytes per pixel\r
#define HDLCD_4BYTES_PER_PIXEL  ((4 - 1) << 3)\r
\r
#define HDLCD_PRODUCT_ID  0x1CDC\r
\r
#endif /* HDLCD_H_ */\r
Commit	Line	Data
b1b69d26	1	/** @file\r
3e7105bb	2	\r
b1b69d26	3	Copyright (c) 2011-2018, ARM Ltd. All rights reserved.<BR>\r
3e7105bb	4	\r
f4dfad05	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
3e7105bb AB	6	\r
	7	**/\r
	8	\r
b1b69d26 GP	9	#ifndef HDLCD_H_\r
b1b69d26 GP	10	#define HDLCD_H_\r
3e7105bb	11	\r
3e7105bb	12	// HDLCD Controller Register Offsets\r
40b0b23e MK	13	#define HDLCD_REG_VERSION ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
	14	#define HDLCD_REG_INT_RAWSTAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
	15	#define HDLCD_REG_INT_CLEAR ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
	16	#define HDLCD_REG_INT_MASK ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)\r
	17	#define HDLCD_REG_INT_STATUS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)\r
	18	#define HDLCD_REG_FB_BASE ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)\r
	19	#define HDLCD_REG_FB_LINE_LENGTH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)\r
	20	#define HDLCD_REG_FB_LINE_COUNT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)\r
	21	#define HDLCD_REG_FB_LINE_PITCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)\r
	22	#define HDLCD_REG_BUS_OPTIONS ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)\r
	23	#define HDLCD_REG_V_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)\r
	24	#define HDLCD_REG_V_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)\r
	25	#define HDLCD_REG_V_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)\r
	26	#define HDLCD_REG_V_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)\r
	27	#define HDLCD_REG_H_SYNC ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)\r
	28	#define HDLCD_REG_H_BACK_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)\r
	29	#define HDLCD_REG_H_DATA ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)\r
	30	#define HDLCD_REG_H_FRONT_PORCH ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)\r
	31	#define HDLCD_REG_POLARITIES ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)\r
	32	#define HDLCD_REG_COMMAND ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)\r
	33	#define HDLCD_REG_PIXEL_FORMAT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)\r
	34	#define HDLCD_REG_RED_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)\r
	35	#define HDLCD_REG_GREEN_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
	36	#define HDLCD_REG_BLUE_SELECT ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
3e7105bb	37	\r
3e7105bb	38	// HDLCD Values of registers\r
3e7105bb AB	39	\r
3e7105bb AB	40	// HDLCD Interrupt mask, clear and status register\r
40b0b23e MK	41	#define HDLCD_DMA_END BIT0 /* DMA has finished reading a frame */\r
	42	#define HDLCD_BUS_ERROR BIT1 /* DMA bus error */\r
	43	#define HDLCD_SYNC BIT2 /* Vertical sync */\r
	44	#define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */\r
3e7105bb AB	45	\r
3e7105bb AB	46	// CLCD_CONTROL Control register\r
40b0b23e MK	47	#define HDLCD_DISABLE 0\r
40b0b23e MK	48	#define HDLCD_ENABLE BIT0\r
3e7105bb AB	49	\r
3e7105bb AB	50	// Bus Options\r
40b0b23e MK	51	#define HDLCD_BURST_1 BIT0\r
	52	#define HDLCD_BURST_2 BIT1\r
	53	#define HDLCD_BURST_4 BIT2\r
	54	#define HDLCD_BURST_8 BIT3\r
	55	#define HDLCD_BURST_16 BIT4\r
3e7105bb AB	56	\r
3e7105bb AB	57	// Polarities - HIGH\r
40b0b23e MK	58	#define HDLCD_VSYNC_HIGH BIT0\r
	59	#define HDLCD_HSYNC_HIGH BIT1\r
	60	#define HDLCD_DATEN_HIGH BIT2\r
	61	#define HDLCD_DATA_HIGH BIT3\r
	62	#define HDLCD_PXCLK_HIGH BIT4\r
3e7105bb	63	// Polarities - LOW (for completion and for ease of understanding the hardware settings)\r
40b0b23e MK	64	#define HDLCD_VSYNC_LOW 0\r
	65	#define HDLCD_HSYNC_LOW 0\r
	66	#define HDLCD_DATEN_LOW 0\r
	67	#define HDLCD_DATA_LOW 0\r
	68	#define HDLCD_PXCLK_LOW 0\r
3e7105bb	69	\r
b1b69d26	70	// Default polarities\r
40b0b23e	71	#define HDLCD_DEFAULT_POLARITIES (HDLCD_PXCLK_LOW \| HDLCD_DATA_HIGH \| \\r
b1b69d26 GP	72	HDLCD_DATEN_HIGH \| HDLCD_HSYNC_LOW \| \\r
	73	HDLCD_VSYNC_HIGH)\r
	74	\r
3e7105bb	75	// Pixel Format\r
40b0b23e MK	76	#define HDLCD_LITTLE_ENDIAN (0 << 31)\r
40b0b23e MK	77	#define HDLCD_BIG_ENDIAN (1 << 31)\r
3e7105bb AB	78	\r
3e7105bb AB	79	// Number of bytes per pixel\r
40b0b23e	80	#define HDLCD_4BYTES_PER_PIXEL ((4 - 1) << 3)\r
3e7105bb	81	\r
40b0b23e	82	#define HDLCD_PRODUCT_ID 0x1CDC\r
c18ef81e	83	\r
b1b69d26	84	#endif /* HDLCD_H_ */\r