projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 0f4386e7 | 1 | /** @file\r |
| 5a5440d0 PG |
2 | \r |
| 3 | Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r | |
| 4 | \r | |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
| 6 | \r | |
| 0f4386e7 | 7 | **/\r |
| 8 | \r | |
| 0f4386e7 | 9 | #ifndef __PL031_REAL_TIME_CLOCK_H__\r |
| 10 | #define __PL031_REAL_TIME_CLOCK_H__\r | |
| 11 | \r | |
| 0f4386e7 | 12 | // PL031 Registers\r |
| 40b0b23e MK |
13 | #define PL031_RTC_DR_DATA_REGISTER 0x000\r |
| 14 | #define PL031_RTC_MR_MATCH_REGISTER 0x004\r | |
| 15 | #define PL031_RTC_LR_LOAD_REGISTER 0x008\r | |
| 16 | #define PL031_RTC_CR_CONTROL_REGISTER 0x00C\r | |
| 17 | #define PL031_RTC_IMSC_IRQ_MASK_SET_CLEAR_REGISTER 0x010\r | |
| 18 | #define PL031_RTC_RIS_RAW_IRQ_STATUS_REGISTER 0x014\r | |
| 19 | #define PL031_RTC_MIS_MASKED_IRQ_STATUS_REGISTER 0x018\r | |
| 20 | #define PL031_RTC_ICR_IRQ_CLEAR_REGISTER 0x01C\r | |
| 21 | #define PL031_RTC_PERIPH_ID0 0xFE0\r | |
| 22 | #define PL031_RTC_PERIPH_ID1 0xFE4\r | |
| 23 | #define PL031_RTC_PERIPH_ID2 0xFE8\r | |
| 24 | #define PL031_RTC_PERIPH_ID3 0xFEC\r | |
| 25 | #define PL031_RTC_PCELL_ID0 0xFF0\r | |
| 26 | #define PL031_RTC_PCELL_ID1 0xFF4\r | |
| 27 | #define PL031_RTC_PCELL_ID2 0xFF8\r | |
| 28 | #define PL031_RTC_PCELL_ID3 0xFFC\r | |
| 0f4386e7 | 29 | \r |
| 30 | // PL031 Values\r | |
| 40b0b23e MK |
31 | #define PL031_RTC_ENABLED 0x00000001\r |
| 32 | #define PL031_SET_IRQ_MASK 0x00000001\r | |
| 33 | #define PL031_IRQ_TRIGGERED 0x00000001\r | |
| 34 | #define PL031_CLEAR_IRQ 0x00000001\r | |
| 0f4386e7 | 35 | \r |
| 40b0b23e | 36 | #define PL031_COUNTS_PER_SECOND 1\r |
| 0f4386e7 | 37 | \r |
| 0f4386e7 | 38 | #endif\r |