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1d5d0ae9 | 1 | /** @file |
2 | ||
3 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR> | |
2dde40b1 | 4 | Copyright (c) 2011, ARM Limited. All rights reserved. |
1d5d0ae9 | 5 | |
6 | This program and the accompanying materials | |
7 | are licensed and made available under the terms and conditions of the BSD License | |
8 | which accompanies this distribution. The full text of the license may be found at | |
9 | http://opensource.org/licenses/bsd-license.php | |
10 | ||
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. | |
13 | ||
14 | **/ | |
15 | ||
16 | #include <Base.h> | |
17 | ||
18 | #include <Library/BaseLib.h> | |
19 | #include <Library/TimerLib.h> | |
20 | #include <Library/DebugLib.h> | |
21 | #include <Library/PcdLib.h> | |
22 | #include <Library/IoLib.h> | |
23 | #include <Drivers/SP804Timer.h> | |
5cc45b70 | 24 | |
9e4a626c | 25 | #define SP804_TIMER_METRONOME_BASE ((UINTN)PcdGet32 (PcdSP804TimerMetronomeBase)) |
26 | #define SP804_TIMER_PERFORMANCE_BASE ((UINTN)PcdGet32 (PcdSP804TimerPerformanceBase)) | |
1d5d0ae9 | 27 | |
28 | // Setup SP810's Timer2 for managing delay functions. And Timer3 for Performance counter | |
29 | // Note: ArmVE's Timer0 and Timer1 are used by TimerDxe. | |
30 | RETURN_STATUS | |
31 | EFIAPI | |
32 | TimerConstructor ( | |
33 | VOID | |
34 | ) | |
35 | { | |
9e4a626c | 36 | // Check if the Metronome Timer is already initialized |
5cc45b70 | 37 | if (MmioRead32(SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { |
23792dea | 38 | return RETURN_SUCCESS; |
39 | } else { | |
2dde40b1 | 40 | // Configure the Metronome Timer for free running operation, 32 bits, no prescaler, and interrupt disabled |
41 | MmioWrite32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); | |
1d5d0ae9 | 42 | |
2dde40b1 | 43 | // Start the Metronome Timer ticking |
5cc45b70 | 44 | MmioOr32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); |
23792dea | 45 | } |
1d5d0ae9 | 46 | |
9e4a626c | 47 | // Check if the Performance Timer is already initialized |
5cc45b70 | 48 | if (MmioRead32(SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG) & SP804_TIMER_CTRL_ENABLE) { |
23792dea | 49 | return RETURN_SUCCESS; |
50 | } else { | |
9e4a626c | 51 | // Configure the Performance timer for free running operation, 32 bits, no prescaler, interrupt disabled |
2dde40b1 | 52 | MmioWrite32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_32BIT | SP804_PRESCALE_DIV_1); |
1d5d0ae9 | 53 | |
9e4a626c | 54 | // Start the Performance Timer ticking |
5cc45b70 | 55 | MmioOr32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CONTROL_REG, SP804_TIMER_CTRL_ENABLE); |
23792dea | 56 | } |
1d5d0ae9 | 57 | |
23792dea | 58 | return RETURN_SUCCESS; |
1d5d0ae9 | 59 | } |
60 | ||
61 | /** | |
62 | Stalls the CPU for at least the given number of microseconds. | |
63 | ||
64 | Stalls the CPU for the number of microseconds specified by MicroSeconds. | |
2dde40b1 | 65 | The hardware timer is 32 bits. |
66 | The maximum possible delay is (0xFFFFFFFF / TimerFrequencyMHz), i.e. ([32bits] / FreqInMHz) | |
67 | For example: | |
68 | +----------------+------------+----------+----------+ | |
69 | | TimerFrequency | MaxDelay | MaxDelay | MaxDelay | | |
70 | | (MHz) | (us) | (s) | (min) | | |
71 | +----------------+------------+----------+----------+ | |
72 | | 1 | 0xFFFFFFFF | 4294 | 71.5 | | |
73 | | 5 | 0x33333333 | 859 | 14.3 | | |
74 | | 10 | 0x19999999 | 429 | 7.2 | | |
75 | | 50 | 0x051EB851 | 86 | 1.4 | | |
76 | +----------------+------------+----------+----------+ | |
77 | If it becomes necessary to support higher delays, then consider using the | |
78 | real time clock. | |
79 | ||
80 | During this delay, the cpu is not yielded to any other process, with one exception: | |
81 | events that are triggered off a timer and which execute at a higher TPL than | |
82 | this function. These events may call MicroSecondDelay (or NanoSecondDelay) to | |
83 | fulfil their own needs. | |
84 | Therefore, this function must be re-entrant, as it may be interrupted and re-started. | |
1d5d0ae9 | 85 | |
86 | @param MicroSeconds The minimum number of microseconds to delay. | |
87 | ||
88 | @return The value of MicroSeconds inputted. | |
89 | ||
90 | **/ | |
91 | UINTN | |
92 | EFIAPI | |
93 | MicroSecondDelay ( | |
94 | IN UINTN MicroSeconds | |
95 | ) | |
96 | { | |
2dde40b1 | 97 | UINT64 DelayTicks64; // Convert from microseconds to timer ticks, more bits to detect over-range conditions. |
98 | UINTN DelayTicks; // Convert from microseconds to timer ticks, native size for general calculations. | |
99 | UINTN StartTicks; // Timer value snapshot at the start of the delay | |
100 | UINTN TargetTicks; // Timer value to signal the end of the delay | |
101 | UINTN CurrentTicks; // Current value of the 64-bit timer value at any given moment | |
102 | ||
103 | // If we snapshot the timer at the start of the delay function then we minimise unaccounted overheads. | |
104 | StartTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG); | |
105 | ||
106 | // We are operating at the limit of 32bits. For the range checking work in 64 bits to avoid overflows. | |
107 | DelayTicks64 = MultU64x32((UINT64)MicroSeconds, PcdGet32(PcdSP804TimerFrequencyInMHz)); | |
108 | ||
109 | // We are limited to 32 bits. | |
110 | // If the specified delay is exactly equal to the max range of the timer, | |
111 | // then the start will be equal to the stop plus one timer overflow (wrap-around). | |
112 | // To avoid having to check for that, reduce the maximum acceptable range by 1 tick, | |
113 | // i.e. reject delays equal or greater than the max range of the timer. | |
114 | if (DelayTicks64 >= (UINT64)SP804_MAX_TICKS) { | |
115 | DEBUG((EFI_D_ERROR,"MicroSecondDelay: ERROR: MicroSeconds=%d exceed SP804 count range. Max MicroSeconds=%d\n", | |
116 | MicroSeconds, | |
117 | ((UINTN)SP804_MAX_TICKS/PcdGet32(PcdSP804TimerFrequencyInMHz)))); | |
118 | } | |
119 | ASSERT(DelayTicks64 < (UINT64)SP804_MAX_TICKS); | |
120 | ||
121 | // From now on do calculations only in native bit size. | |
122 | DelayTicks = (UINTN)DelayTicks64; | |
123 | ||
124 | // Calculate the target value of the timer. | |
125 | ||
126 | //Note: SP804 timer is counting down | |
127 | if (StartTicks >= DelayTicks) { | |
128 | // In this case we do not expect a wrap-around of the timer to occur. | |
129 | // CurrentTicks must be less than StartTicks and higher than TargetTicks. | |
130 | // If this is not the case, then the delay has been reached and may even have been exceeded if this | |
131 | // function was suspended by a higher priority interrupt. | |
1d5d0ae9 | 132 | |
2dde40b1 | 133 | TargetTicks = StartTicks - DelayTicks; |
ce9cc403 | 134 | |
2dde40b1 | 135 | do { |
136 | CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG); | |
137 | } while ((CurrentTicks > TargetTicks) && (CurrentTicks <= StartTicks)); | |
138 | ||
139 | } else { | |
140 | // In this case TargetTicks is larger than StartTicks. | |
141 | // This means we expect a wrap-around of the timer to occur and we must wait for it. | |
142 | // Before the wrap-around, CurrentTicks must be less than StartTicks and less than TargetTicks. | |
143 | // After the wrap-around, CurrentTicks must be larger than StartTicks and larger than TargetTicks. | |
144 | // If this is not the case, then the delay has been reached and may even have been exceeded if this | |
145 | // function was suspended by a higher priority interrupt. | |
146 | ||
147 | // The order of operations is essential to avoid arithmetic overflow problems | |
148 | TargetTicks = ((UINTN)SP804_MAX_TICKS - DelayTicks) + StartTicks; | |
149 | ||
150 | // First wait for the wrap-around to occur | |
151 | do { | |
152 | CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG); | |
153 | } while (CurrentTicks <= StartTicks); | |
154 | ||
155 | // Then wait for the target | |
156 | do { | |
157 | CurrentTicks = MmioRead32 (SP804_TIMER_METRONOME_BASE + SP804_TIMER_CURRENT_REG); | |
158 | } while (CurrentTicks > TargetTicks); | |
1d5d0ae9 | 159 | } |
160 | ||
161 | return MicroSeconds; | |
162 | } | |
163 | ||
164 | /** | |
165 | Stalls the CPU for at least the given number of nanoseconds. | |
166 | ||
167 | Stalls the CPU for the number of nanoseconds specified by NanoSeconds. | |
168 | ||
2dde40b1 | 169 | When the timer frequency is 1MHz, each tick corresponds to 1 microsecond. |
170 | Therefore, the nanosecond delay will be rounded up to the nearest 1 microsecond. | |
171 | ||
1d5d0ae9 | 172 | @param NanoSeconds The minimum number of nanoseconds to delay. |
173 | ||
174 | @return The value of NanoSeconds inputted. | |
175 | ||
176 | **/ | |
177 | UINTN | |
178 | EFIAPI | |
179 | NanoSecondDelay ( | |
180 | IN UINTN NanoSeconds | |
181 | ) | |
182 | { | |
2dde40b1 | 183 | UINTN MicroSeconds; |
1d5d0ae9 | 184 | |
185 | // Round up to 1us Tick Number | |
2dde40b1 | 186 | MicroSeconds = NanoSeconds / 1000; |
187 | MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1; | |
1d5d0ae9 | 188 | |
2dde40b1 | 189 | MicroSecondDelay (MicroSeconds); |
1d5d0ae9 | 190 | |
1d5d0ae9 | 191 | return NanoSeconds; |
192 | } | |
193 | ||
194 | /** | |
195 | Retrieves the current value of a 64-bit free running performance counter. | |
196 | ||
197 | The counter can either count up by 1 or count down by 1. If the physical | |
198 | performance counter counts by a larger increment, then the counter values | |
199 | must be translated. The properties of the counter can be retrieved from | |
200 | GetPerformanceCounterProperties(). | |
201 | ||
202 | @return The current value of the free running performance counter. | |
203 | ||
204 | **/ | |
205 | UINT64 | |
206 | EFIAPI | |
207 | GetPerformanceCounter ( | |
208 | VOID | |
209 | ) | |
210 | { | |
211 | // Free running 64-bit/32-bit counter is needed here. | |
212 | // Don't think we need this to boot, just to do performance profile | |
23792dea | 213 | UINT64 Value; |
5cc45b70 | 214 | Value = MmioRead32 (SP804_TIMER_PERFORMANCE_BASE + SP804_TIMER_CURRENT_REG); |
23792dea | 215 | return Value; |
1d5d0ae9 | 216 | } |
217 | ||
218 | ||
219 | /** | |
220 | Retrieves the 64-bit frequency in Hz and the range of performance counter | |
221 | values. | |
222 | ||
223 | If StartValue is not NULL, then the value that the performance counter starts | |
224 | with immediately after is it rolls over is returned in StartValue. If | |
225 | EndValue is not NULL, then the value that the performance counter end with | |
226 | immediately before it rolls over is returned in EndValue. The 64-bit | |
227 | frequency of the performance counter in Hz is always returned. If StartValue | |
228 | is less than EndValue, then the performance counter counts up. If StartValue | |
229 | is greater than EndValue, then the performance counter counts down. For | |
230 | example, a 64-bit free running counter that counts up would have a StartValue | |
231 | of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter | |
232 | that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. | |
233 | ||
234 | @param StartValue The value the performance counter starts with when it | |
235 | rolls over. | |
236 | @param EndValue The value that the performance counter ends with before | |
237 | it rolls over. | |
238 | ||
239 | @return The frequency in Hz. | |
240 | ||
241 | **/ | |
242 | UINT64 | |
243 | EFIAPI | |
244 | GetPerformanceCounterProperties ( | |
245 | OUT UINT64 *StartValue, OPTIONAL | |
246 | OUT UINT64 *EndValue OPTIONAL | |
247 | ) | |
248 | { | |
249 | if (StartValue != NULL) { | |
250 | // Timer starts with the reload value | |
bcd8fa79 | 251 | *StartValue = 0xFFFFFFFF; |
1d5d0ae9 | 252 | } |
253 | ||
254 | if (EndValue != NULL) { | |
bcd8fa79 | 255 | // Timer counts down to 0x0 |
256 | *EndValue = (UINT64)0ULL; | |
1d5d0ae9 | 257 | } |
258 | ||
ce9cc403 | 259 | return PcdGet64 (PcdEmbeddedPerformanceCounterFrequencyInHz); |
1d5d0ae9 | 260 | } |