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ARM Packages: use GCC_ASM_EXPORT to export functions
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1#========================================================================================\r
2# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
3#\r
4# This program and the accompanying materials\r
5# are licensed and made available under the terms and conditions of the BSD License\r
6# which accompanies this distribution. The full text of the license may be found at\r
7# http:#opensource.org/licenses/bsd-license.php\r
8#\r
9# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11#\r
12#=======================================================================================\r
13\r
14#include <AsmMacroIoLibV8.h>\r
15#include <Chipset/AArch64.h>\r
16\r
17#start of the code section\r
18.text\r
19.align 3\r
20\r
919a3a02
BJ
21GCC_ASM_EXPORT(SetupExceptionLevel1)\r
22GCC_ASM_EXPORT(SetupExceptionLevel2)\r
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23\r
24// Setup EL1 while in EL1\r
25ASM_PFX(SetupExceptionLevel1):\r
26 mov x5, x30 // Save LR\r
27\r
28 mov x0, #CPACR_CP_FULL_ACCESS\r
29 bl ASM_PFX(ArmWriteCpacr) // Disable copro traps to EL1\r
30\r
31 ret x5\r
32\r
33// Setup EL2 while in EL2\r
34ASM_PFX(SetupExceptionLevel2):\r
35 msr sctlr_el2, xzr\r
36 mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
37\r
38 // Send all interrupts to their respective Exception levels for EL2\r
39 orr x0, x0, #(1 << 3) // Enable EL2 FIQ\r
40 orr x0, x0, #(1 << 4) // Enable EL2 IRQ\r
41 orr x0, x0, #(1 << 5) // Enable EL2 SError and Abort\r
42 msr hcr_el2, x0 // Write back our settings\r
43\r
44 msr cptr_el2, xzr // Disable copro traps to EL2\r
45\r
46 ret\r
47\r
1bc83266 48ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r