projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 1d5d0ae9 | 1 | /** @file\r |
| 5a5440d0 PG |
2 | \r |
| 3 | Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r | |
| 4 | \r | |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
| 6 | \r | |
| 1d5d0ae9 | 7 | **/\r |
| 8 | \r | |
| f598bf12 | 9 | #include "PrePeiCore.h"\r |
| 10 | \r | |
| 1d5d0ae9 | 11 | VOID\r |
| 12 | EFIAPI\r | |
| f598bf12 | 13 | SecondaryMain (\r |
| 40b0b23e | 14 | IN UINTN MpId\r |
| f598bf12 | 15 | )\r |
| 1d5d0ae9 | 16 | {\r |
| 40b0b23e | 17 | ASSERT (FALSE);\r |
| 1d5d0ae9 | 18 | }\r |
| 19 | \r | |
| f598bf12 | 20 | VOID\r |
| 21 | EFIAPI\r | |
| 22 | PrimaryMain (\r | |
| 1d5d0ae9 | 23 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
| 24 | )\r | |
| 25 | {\r | |
| 40b0b23e MK |
26 | EFI_SEC_PEI_HAND_OFF SecCoreData;\r |
| 27 | UINTN PpiListSize;\r | |
| 28 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
| 29 | UINTN TemporaryRamBase;\r | |
| 30 | UINTN TemporaryRamSize;\r | |
| f598bf12 | 31 | \r |
| 77de7e53 | 32 | CreatePpiList (&PpiListSize, &PpiList);\r |
| 33 | \r | |
| 34 | // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r | |
| 35 | // the base of the primary core stack\r | |
| 40b0b23e | 36 | PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);\r |
| bb5420bb | 37 | TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r |
| 77de7e53 | 38 | TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r |
| f598bf12 | 39 | \r |
| 40 | //\r | |
| 41 | // Bind this information into the SEC hand-off state\r | |
| 42 | // Note: this must be in sync with the stuff in the asm file\r | |
| 43 | // Note also: HOBs (pei temp ram) MUST be above stack\r | |
| 44 | //\r | |
| 40b0b23e | 45 | SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);\r |
| bb5420bb | 46 | SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r |
| f92b93c9 | 47 | SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r |
| 77de7e53 | 48 | SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r |
| 49 | SecCoreData.TemporaryRamSize = TemporaryRamSize;\r | |
| 50 | SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r | |
| 7945b29c | 51 | SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r |
| bc299a9f | 52 | SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r |
| 3222e7b1 | 53 | SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r |
| f598bf12 | 54 | \r |
| 77de7e53 | 55 | // Jump to PEI core entry point\r |
| 56 | (PeiCoreEntryPoint)(&SecCoreData, PpiList);\r | |
| 1d5d0ae9 | 57 | }\r |