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1 | /** @file\r |
| 2 | * Main file supporting the transition to PEI Core in Normal World for Versatile Express\r |
| 3 | *\r |
| 4 | * Copyright (c) 2011, ARM Limited. All rights reserved.\r |
| 5 | *\r |
| 6 | * This program and the accompanying materials\r |
| 7 | * are licensed and made available under the terms and conditions of the BSD License\r |
| 8 | * which accompanies this distribution. The full text of the license may be found at\r |
| 9 | * http://opensource.org/licenses/bsd-license.php\r |
| 10 | *\r |
| 11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | *\r |
| 14 | **/\r |
| 15 | #ifndef __PREPEICORE_H_\r |
| 16 | #define __PREPEICORE_H_\r |
| 17 | \r |
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18 | #include <Library/ArmLib.h>\r |
| 19 | #include <Library/ArmPlatformLib.h>\r |
| 20 | #include <Library/BaseMemoryLib.h>\r |
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21 | #include <Library/DebugLib.h>\r |
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22 | #include <Library/IoLib.h>\r |
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23 | #include <Library/PcdLib.h>\r |
| 24 | \r |
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25 | #include <PiPei.h>\r |
| 26 | #include <Ppi/TemporaryRamSupport.h>\r |
| 27 | \r |
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28 | VOID\r |
| 29 | CreatePpiList (\r |
| 30 | OUT UINTN *PpiListSize,\r |
| 31 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r |
| 32 | );\r |
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33 | \r |
| 34 | EFI_STATUS\r |
| 35 | EFIAPI\r |
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36 | PrePeiCoreTemporaryRamSupport (\r |
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37 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
| 38 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r |
| 39 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r |
| 40 | IN UINTN CopySize\r |
| 41 | );\r |
| 42 | \r |
| 43 | VOID\r |
| 44 | SecSwitchStack (\r |
| 45 | INTN StackDelta\r |
| 46 | );\r |
| 47 | \r |
| 48 | // Vector Table for Pei Phase\r |
| 49 | VOID PeiVectorTable (VOID);\r |
| 50 | \r |
| 51 | VOID\r |
| 52 | EFIAPI\r |
| 53 | PrimaryMain (\r |
| 54 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
| 55 | );\r |
| 56 | \r |
| 57 | /*\r |
| 58 | * This is the main function for secondary cores. They loop around until a non Null value is written to\r |
| 59 | * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r |
| 60 | * Note:The secondary cores, while executing secondary_main, assumes that:\r |
| 61 | * : SGI 0 is configured as Non-secure interrupt\r |
| 62 | * : Priority Mask is configured to allow SGI 0\r |
| 63 | * : Interrupt Distributor and CPU interfaces are enabled\r |
| 64 | *\r |
| 65 | */\r |
| 66 | VOID\r |
| 67 | EFIAPI\r |
| 68 | SecondaryMain (\r |
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69 | IN UINTN MpId\r |
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70 | );\r |
| 71 | \r |
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72 | VOID\r |
| 73 | PeiCommonExceptionEntry (\r |
| 74 | IN UINT32 Entry,\r |
| 75 | IN UINTN LR\r |
| 76 | );\r |
| 77 | \r |
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78 | #endif\r |
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