]> git.proxmox.com Git - mirror_edk2.git/blame - ArmPlatformPkg/PrePi/Arm/ModuleEntryPoint.S
ArmPlatformPkg/PrePi: avoid global variable write to mSystemMemoryEnd
[mirror_edk2.git] / ArmPlatformPkg / PrePi / Arm / ModuleEntryPoint.S
CommitLineData
cd872e40 1//\r
5dbacdb2 2// Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
cd872e40 3//\r
4// This program and the accompanying materials\r
5// are licensed and made available under the terms and conditions of the BSD License\r
6// which accompanies this distribution. The full text of the license may be found at\r
7// http://opensource.org/licenses/bsd-license.php\r
8//\r
9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11//\r
12//\r
13\r
14#include <AsmMacroIoLib.h>\r
cd872e40 15\r
063ad84e 16#include <Chipset/ArmV7.h>\r
17\r
d2fa09a1 18ASM_FUNC(_ModuleEntryPoint)\r
b5a57223 19 // Do early platform specific actions\r
20 bl ASM_PFX(ArmPlatformPeiBootAction)\r
21\r
0787bc61 22 // Get ID of this CPU in Multicore system\r
23 bl ASM_PFX(ArmReadMpidr)\r
bebda7ce 24 // Keep a copy of the MpId register value\r
c2d87a49 25 mov r8, r0\r
cd872e40 26\r
d269095b 27_SetSVCMode:\r
99565b88 28 // Enter SVC mode, Disable FIQ and IRQ\r
063ad84e 29 mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ)\r
d269095b 30 msr CPSR_c, r1\r
31\r
2dbcb8f0 32// Check if we can install the stack at the top of the System Memory or if we need\r
d269095b 33// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
34// at the top of the DRAM)\r
5dbacdb2 35_SystemMemoryEndInit:\r
4aae7419
AB
36 ADRL (r1, mSystemMemoryEnd)\r
37 ldrd r2, r3, [r1]\r
38 teq r3, #0\r
39 moveq r1, r2\r
40 mvnne r1, #0\r
5dbacdb2
OM
41\r
42_SetupStackPosition:\r
43 // r1 = SystemMemoryTop\r
cd872e40 44\r
d269095b 45 // Calculate Top of the Firmware Device\r
d2fa09a1
AB
46 MOV32 (r2, FixedPcdGet32(PcdFdBaseAddress))\r
47 MOV32 (r3, FixedPcdGet32(PcdFdSize) - 1)\r
7defe7b3 48 add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
d269095b 49\r
50 // UEFI Memory Size (stacks are allocated in this region)\r
d2fa09a1 51 MOV32 (r4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize))\r
d269095b 52\r
53 //\r
54 // Reserve the memory for the UEFI region (contain stacks on its top)\r
55 //\r
56\r
57 // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
91c38d4e
RC
58 subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
59 bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
60 cmp r0, r4\r
61 bge _SetupStack\r
d269095b 62\r
63 // Case the top of stacks is the FdBaseAddress\r
91c38d4e 64 mov r1, r2\r
cd872e40 65\r
66_SetupStack:\r
2dbcb8f0 67 // r1 contains the top of the stack (and the UEFI Memory)\r
d269095b 68\r
2569b068 69 // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
70 // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
71 // top of the memory space)\r
c2d87a49 72 adds r9, r1, #1\r
2569b068 73 bcs _SetupOverflowStack\r
74\r
75_SetupAlignedStack:\r
c2d87a49 76 mov r1, r9\r
2569b068 77 b _GetBaseUefiMemory\r
78\r
79_SetupOverflowStack:\r
80 // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
81 // aligned (4KB)\r
d2fa09a1
AB
82 MOV32 (r9, ~EFI_PAGE_MASK & 0xFFFFFFFF)\r
83 and r1, r1, r9\r
2569b068 84\r
85_GetBaseUefiMemory:\r
d269095b 86 // Calculate the Base of the UEFI Memory\r
c2d87a49 87 sub r9, r1, r4\r
cd872e40 88\r
2dbcb8f0 89_GetStackBase:\r
1377db63 90 // r1 = The top of the Mpcore Stacks\r
2dbcb8f0 91 // Stack for the primary core = PrimaryCoreStack\r
d2fa09a1 92 MOV32 (r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))\r
c2d87a49 93 sub r10, r1, r2\r
17839a45 94\r
95 // Stack for the secondary core = Number of Cores - 1\r
570e7cd4 96 MOV32 (r1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSecondaryStackSize))\r
c2d87a49 97 sub r10, r10, r1\r
17839a45 98\r
c2d87a49 99 // r10 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
91c38d4e
RC
100 mov r0, r10\r
101 mov r1, r8\r
17839a45 102 //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
d2fa09a1
AB
103 MOV32 (r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize))\r
104 MOV32 (r3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize))\r
91c38d4e 105 bl ASM_PFX(ArmPlatformStackSet)\r
2dbcb8f0 106\r
107 // Is it the Primary Core ?\r
c2d87a49 108 mov r0, r8\r
bebda7ce 109 bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
110 cmp r0, #1\r
cd872e40 111 bne _PrepareArguments\r
112\r
cd872e40 113_PrepareArguments:\r
c2d87a49
OM
114 mov r0, r8\r
115 mov r1, r9\r
116 mov r2, r10\r
c524ffbb 117 mov r3, sp\r
118\r
cd872e40 119 // Move sec startup address into a data register\r
120 // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
d2fa09a1 121 ldr r4, =ASM_PFX(CEntryPoint)\r
cd872e40 122\r
d269095b 123 // Jump to PrePiCore C code\r
0787bc61 124 // r0 = MpId\r
cd872e40 125 // r1 = UefiMemoryBase\r
c524ffbb 126 // r2 = StacksBase\r
c524ffbb 127 blx r4\r
cd872e40 128\r
2dbcb8f0 129_NeverReturn:\r
130 b _NeverReturn\r