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cd872e40 1//\r
c2d87a49 2// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
cd872e40 3//\r
4// This program and the accompanying materials\r
5// are licensed and made available under the terms and conditions of the BSD License\r
6// which accompanies this distribution. The full text of the license may be found at\r
7// http://opensource.org/licenses/bsd-license.php\r
8//\r
9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11//\r
12//\r
13\r
14#include <AsmMacroIoLib.h>\r
15#include <Base.h>\r
16#include <Library/PcdLib.h>\r
17#include <AutoGen.h>\r
18\r
063ad84e 19#include <Chipset/ArmV7.h>\r
20\r
cd872e40 21.text\r
22.align 3\r
23\r
cd872e40 24GCC_ASM_IMPORT(CEntryPoint)\r
bebda7ce 25GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
0787bc61 26GCC_ASM_IMPORT(ArmReadMpidr)\r
b5a57223 27GCC_ASM_IMPORT(ArmPlatformPeiBootAction)\r
17839a45 28GCC_ASM_IMPORT(ArmPlatformStackSet)\r
d269095b 29GCC_ASM_EXPORT(_ModuleEntryPoint)\r
cd872e40 30\r
31StartupAddr: .word CEntryPoint\r
32\r
cd872e40 33\r
34ASM_PFX(_ModuleEntryPoint):\r
b5a57223 35 // Do early platform specific actions\r
36 bl ASM_PFX(ArmPlatformPeiBootAction)\r
37\r
0787bc61 38 // Get ID of this CPU in Multicore system\r
39 bl ASM_PFX(ArmReadMpidr)\r
bebda7ce 40 // Keep a copy of the MpId register value\r
c2d87a49 41 mov r8, r0\r
cd872e40 42\r
d269095b 43_SetSVCMode:\r
99565b88 44 // Enter SVC mode, Disable FIQ and IRQ\r
063ad84e 45 mov r1, #(CPSR_MODE_SVC | CPSR_IRQ | CPSR_FIQ)\r
d269095b 46 msr CPSR_c, r1\r
47\r
2dbcb8f0 48// Check if we can install the stack at the top of the System Memory or if we need\r
d269095b 49// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
50// at the top of the DRAM)\r
51_SetupStackPosition:\r
cd872e40 52 // Compute Top of System Memory\r
c357fd6a
OM
53 LoadConstantToReg (FixedPcdGet64 (PcdSystemMemoryBase), r1)\r
54 LoadConstantToReg (FixedPcdGet64 (PcdSystemMemorySize), r2)\r
2569b068 55 sub r2, r2, #1\r
cd872e40 56 add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
cd872e40 57\r
d269095b 58 // Calculate Top of the Firmware Device\r
f92b93c9 59 LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r
60 LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r
2569b068 61 sub r3, r3, #1\r
7defe7b3 62 add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
d269095b 63\r
64 // UEFI Memory Size (stacks are allocated in this region)\r
65 LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r
66\r
67 //\r
68 // Reserve the memory for the UEFI region (contain stacks on its top)\r
69 //\r
70\r
71 // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
91c38d4e
RC
72 subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
73 bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
74 cmp r0, r4\r
75 bge _SetupStack\r
d269095b 76\r
77 // Case the top of stacks is the FdBaseAddress\r
91c38d4e 78 mov r1, r2\r
cd872e40 79\r
80_SetupStack:\r
2dbcb8f0 81 // r1 contains the top of the stack (and the UEFI Memory)\r
d269095b 82\r
2569b068 83 // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
84 // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
85 // top of the memory space)\r
c2d87a49 86 adds r9, r1, #1\r
2569b068 87 bcs _SetupOverflowStack\r
88\r
89_SetupAlignedStack:\r
c2d87a49 90 mov r1, r9\r
2569b068 91 b _GetBaseUefiMemory\r
92\r
93_SetupOverflowStack:\r
94 // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
95 // aligned (4KB)\r
c2d87a49
OM
96 LoadConstantToReg (EFI_PAGE_MASK, r9)\r
97 and r9, r9, r1\r
98 sub r1, r1, r9\r
2569b068 99\r
100_GetBaseUefiMemory:\r
d269095b 101 // Calculate the Base of the UEFI Memory\r
c2d87a49 102 sub r9, r1, r4\r
cd872e40 103\r
2dbcb8f0 104_GetStackBase:\r
1377db63 105 // r1 = The top of the Mpcore Stacks\r
2dbcb8f0 106 // Stack for the primary core = PrimaryCoreStack\r
107 LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
c2d87a49 108 sub r10, r1, r2\r
17839a45 109\r
110 // Stack for the secondary core = Number of Cores - 1\r
111 LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
91c38d4e 112 sub r0, r0, #1\r
17839a45 113 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
114 mul r1, r1, r0\r
c2d87a49 115 sub r10, r10, r1\r
17839a45 116\r
c2d87a49 117 // r10 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
91c38d4e
RC
118 mov r0, r10\r
119 mov r1, r8\r
17839a45 120 //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
1377db63 121 LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
17839a45 122 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
91c38d4e 123 bl ASM_PFX(ArmPlatformStackSet)\r
2dbcb8f0 124\r
125 // Is it the Primary Core ?\r
c2d87a49 126 mov r0, r8\r
bebda7ce 127 bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
128 cmp r0, #1\r
cd872e40 129 bne _PrepareArguments\r
130\r
17839a45 131_ReserveGlobalVariable:\r
132 LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0)\r
133 // InitializePrimaryStack($GlobalVariableSize, $Tmp1)\r
134 InitializePrimaryStack(r0, r1)\r
2dbcb8f0 135\r
cd872e40 136_PrepareArguments:\r
c2d87a49
OM
137 mov r0, r8\r
138 mov r1, r9\r
139 mov r2, r10\r
c524ffbb 140 mov r3, sp\r
141\r
cd872e40 142 // Move sec startup address into a data register\r
143 // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
c524ffbb 144 ldr r4, StartupAddr\r
cd872e40 145\r
d269095b 146 // Jump to PrePiCore C code\r
0787bc61 147 // r0 = MpId\r
cd872e40 148 // r1 = UefiMemoryBase\r
c524ffbb 149 // r2 = StacksBase\r
150 // r3 = GlobalVariableBase\r
151 blx r4\r
cd872e40 152\r
2dbcb8f0 153_NeverReturn:\r
154 b _NeverReturn\r
155\r