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cd872e40 | 1 | /** @file\r |
2 | *\r | |
4c19ece3 | 3 | * Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
cd872e40 | 4 | *\r |
5 | * This program and the accompanying materials\r | |
6 | * are licensed and made available under the terms and conditions of the BSD License\r | |
7 | * which accompanies this distribution. The full text of the license may be found at\r | |
8 | * http://opensource.org/licenses/bsd-license.php\r | |
9 | *\r | |
10 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | *\r | |
13 | **/\r | |
14 | \r | |
15 | #include "PrePi.h"\r | |
16 | \r | |
55a0d64b | 17 | #include <Library/ArmGicLib.h>\r |
cd872e40 | 18 | \r |
99565b88 | 19 | #include <Ppi/ArmMpCoreInfo.h>\r |
20 | \r | |
21 | EFI_STATUS\r | |
22 | GetPlatformPpi (\r | |
23 | IN EFI_GUID *PpiGuid,\r | |
24 | OUT VOID **Ppi\r | |
25 | )\r | |
26 | {\r | |
27 | UINTN PpiListSize;\r | |
28 | UINTN PpiListCount;\r | |
29 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
30 | UINTN Index;\r | |
31 | \r | |
32 | PpiListSize = 0;\r | |
33 | ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r | |
34 | PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r | |
35 | for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r | |
36 | if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r | |
37 | *Ppi = PpiList->Ppi;\r | |
38 | return EFI_SUCCESS;\r | |
39 | }\r | |
40 | }\r | |
41 | \r | |
42 | return EFI_NOT_FOUND;\r | |
43 | }\r | |
44 | \r | |
cd872e40 | 45 | VOID\r |
46 | PrimaryMain (\r | |
47 | IN UINTN UefiMemoryBase,\r | |
c524ffbb | 48 | IN UINTN StacksBase,\r |
49 | IN UINTN GlobalVariableBase,\r | |
cd872e40 | 50 | IN UINT64 StartTimeStamp\r |
51 | )\r | |
52 | {\r | |
99565b88 | 53 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r |
54 | DEBUG_CODE_BEGIN();\r | |
55 | EFI_STATUS Status;\r | |
56 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
57 | \r | |
58 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r | |
59 | ASSERT_EFI_ERROR (Status);\r | |
60 | DEBUG_CODE_END();\r | |
61 | \r | |
315649cd | 62 | // Check PcdGicPrimaryCoreId has been set in case the Primary Core is not the core 0 of Cluster 0\r |
63 | DEBUG_CODE_BEGIN();\r | |
64 | if ((PcdGet32(PcdArmPrimaryCore) != 0) && (PcdGet32 (PcdGicPrimaryCoreId) == 0)) {\r | |
65 | DEBUG((EFI_D_WARN,"Warning: the PCD PcdGicPrimaryCoreId does not seem to be set up for the configuration.\n"));\r | |
66 | }\r | |
67 | DEBUG_CODE_END();\r | |
68 | \r | |
55a0d64b | 69 | // Enable the GIC Distributor\r |
70 | ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r | |
cd872e40 | 71 | \r |
d269095b | 72 | // In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r |
73 | if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r | |
cd872e40 | 74 | // Sending SGI to all the Secondary CPU interfaces\r |
4c19ece3 | 75 | ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r |
cd872e40 | 76 | }\r |
77 | \r | |
c524ffbb | 78 | PrePiMain (UefiMemoryBase, StacksBase, GlobalVariableBase, StartTimeStamp);\r |
cd872e40 | 79 | \r |
80 | // We must never return\r | |
81 | ASSERT(FALSE);\r | |
82 | }\r | |
83 | \r | |
84 | VOID\r | |
85 | SecondaryMain (\r | |
0787bc61 | 86 | IN UINTN MpId\r |
cd872e40 | 87 | )\r |
88 | {\r | |
99565b88 | 89 | EFI_STATUS Status;\r |
90 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
91 | UINTN Index;\r | |
92 | UINTN ArmCoreCount;\r | |
93 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
94 | UINT32 ClusterId;\r | |
95 | UINT32 CoreId;\r | |
96 | VOID (*SecondaryStart)(VOID);\r | |
97 | UINTN SecondaryEntryAddr;\r | |
315649cd | 98 | UINTN AcknowledgedCoreId;\r |
99565b88 | 99 | \r |
100 | ClusterId = GET_CLUSTER_ID(MpId);\r | |
101 | CoreId = GET_CORE_ID(MpId);\r | |
102 | \r | |
103 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r | |
104 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r | |
105 | ASSERT_EFI_ERROR (Status);\r | |
106 | \r | |
107 | ArmCoreCount = 0;\r | |
108 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
109 | ASSERT_EFI_ERROR (Status);\r | |
110 | \r | |
111 | // Find the core in the ArmCoreTable\r | |
112 | for (Index = 0; Index < ArmCoreCount; Index++) {\r | |
113 | if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r | |
114 | break;\r | |
115 | }\r | |
116 | }\r | |
117 | \r | |
118 | // The ARM Core Info Table must define every core\r | |
119 | ASSERT (Index != ArmCoreCount);\r | |
cd872e40 | 120 | \r |
121 | // Clear Secondary cores MailBox\r | |
99565b88 | 122 | MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r |
cd872e40 | 123 | \r |
315649cd | 124 | do {\r |
99565b88 | 125 | ArmCallWFI ();\r |
315649cd | 126 | \r |
127 | // Read the Mailbox\r | |
128 | SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r | |
129 | \r | |
cd872e40 | 130 | // Acknowledge the interrupt and send End of Interrupt signal.\r |
315649cd | 131 | ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), &AcknowledgedCoreId, NULL);\r |
132 | } while ((SecondaryEntryAddr == 0) && (AcknowledgedCoreId != PcdGet32 (PcdGicPrimaryCoreId)));\r | |
cd872e40 | 133 | \r |
cd872e40 | 134 | // Jump to secondary core entry point.\r |
99565b88 | 135 | SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r |
136 | SecondaryStart();\r | |
cd872e40 | 137 | \r |
138 | // The secondaries shouldn't reach here\r | |
139 | ASSERT(FALSE);\r | |
140 | }\r |