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cd872e40 | 1 | //\r |
2569b068 | 2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
cd872e40 | 3 | //\r |
4 | // This program and the accompanying materials\r | |
5 | // are licensed and made available under the terms and conditions of the BSD License\r | |
6 | // which accompanies this distribution. The full text of the license may be found at\r | |
7 | // http://opensource.org/licenses/bsd-license.php\r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Base.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | #include <AutoGen.h>\r | |
18 | \r | |
19 | INCLUDE AsmMacroIoLib.inc\r | |
20 | \r | |
21 | IMPORT CEntryPoint\r | |
0787bc61 | 22 | IMPORT ArmReadMpidr\r |
695df8ba | 23 | IMPORT ArmPlatformStackSet\r |
24 | \r | |
cd872e40 | 25 | EXPORT _ModuleEntryPoint\r |
26 | \r | |
27 | PRESERVE8\r | |
28 | AREA PrePiCoreEntryPoint, CODE, READONLY\r | |
29 | \r | |
30 | StartupAddr DCD CEntryPoint\r | |
31 | \r | |
32 | _ModuleEntryPoint\r | |
0787bc61 | 33 | // Get ID of this CPU in Multicore system\r |
34 | bl ArmReadMpidr\r | |
35 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r | |
36 | and r5, r0, r1\r | |
cd872e40 | 37 | \r |
d269095b | 38 | _SetSVCMode\r |
99565b88 | 39 | // Enter SVC mode, Disable FIQ and IRQ\r |
2575b726 | 40 | mov r1, #0x13 :OR: 0x80 :OR: 0x40\r |
d269095b | 41 | msr CPSR_c, r1\r |
42 | \r | |
2dbcb8f0 | 43 | // Check if we can install the stack at the top of the System Memory or if we need\r |
d269095b | 44 | // to install the stacks at the bottom of the Firmware Device (case the FD is located\r |
45 | // at the top of the DRAM)\r | |
46 | _SetupStackPosition\r | |
cd872e40 | 47 | // Compute Top of System Memory\r |
48 | LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r | |
49 | LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r | |
2569b068 | 50 | sub r2, r2, #1\r |
cd872e40 | 51 | add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r |
cd872e40 | 52 | \r |
d269095b | 53 | // Calculate Top of the Firmware Device\r |
f92b93c9 | 54 | LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r |
55 | LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r | |
2569b068 | 56 | sub r3, r3, #1\r |
7defe7b3 | 57 | add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r |
d269095b | 58 | \r |
59 | // UEFI Memory Size (stacks are allocated in this region)\r | |
60 | LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r | |
61 | \r | |
62 | //\r | |
63 | // Reserve the memory for the UEFI region (contain stacks on its top)\r | |
64 | //\r | |
65 | \r | |
66 | // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r | |
2dbcb8f0 | 67 | subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r |
68 | bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r | |
69 | cmp r0, r4\r | |
d269095b | 70 | bge _SetupStack\r |
71 | \r | |
72 | // Case the top of stacks is the FdBaseAddress\r | |
73 | mov r1, r2\r | |
cd872e40 | 74 | \r |
75 | _SetupStack\r | |
2dbcb8f0 | 76 | // r1 contains the top of the stack (and the UEFI Memory)\r |
d269095b | 77 | \r |
2569b068 | 78 | // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r |
79 | // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r | |
80 | // top of the memory space)\r | |
81 | adds r6, r1, #1\r | |
82 | bcs _SetupOverflowStack\r | |
83 | \r | |
84 | _SetupAlignedStack\r | |
85 | mov r1, r6\r | |
86 | b _GetBaseUefiMemory\r | |
87 | \r | |
88 | _SetupOverflowStack\r | |
89 | // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r | |
90 | // aligned (4KB)\r | |
91 | LoadConstantToReg (EFI_PAGE_MASK, r6)\r | |
92 | and r6, r6, r1\r | |
93 | sub r1, r1, r6\r | |
94 | \r | |
95 | _GetBaseUefiMemory\r | |
d269095b | 96 | // Calculate the Base of the UEFI Memory\r |
2dbcb8f0 | 97 | sub r6, r1, r4\r |
cd872e40 | 98 | \r |
2dbcb8f0 | 99 | _GetStackBase\r |
100 | // Compute Base of Normal stacks for CPU Cores\r | |
101 | // Is it MpCore system\r | |
886f97c8 | 102 | bl ArmIsMpCore\r |
cd872e40 | 103 | cmp r0, #0\r |
2dbcb8f0 | 104 | // Case it is not an MP Core system. Just setup the primary core\r |
105 | beq _SetupUnicoreStack\r | |
106 | \r | |
107 | _GetStackBaseMpCore\r | |
1377db63 | 108 | // r1 = The top of the Mpcore Stacks\r |
2dbcb8f0 | 109 | // Stack for the primary core = PrimaryCoreStack\r |
110 | LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r | |
695df8ba | 111 | sub r8, r1, r2\r |
112 | \r | |
113 | // Stack for the secondary core = Number of Cores - 1\r | |
114 | LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r | |
115 | sub r0, r0, #1\r | |
116 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r | |
117 | mul r1, r1, r0\r | |
118 | sub r8, r8, r1\r | |
119 | \r | |
120 | // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r | |
121 | mov r0, r8\r | |
122 | mov r1, r6\r | |
123 | //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r | |
124 | LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r | |
2dbcb8f0 | 125 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r |
126 | mul r2, r2, r3\r | |
127 | sub r7, r7, r2\r | |
128 | \r | |
1377db63 | 129 | // The base of the secondary Stacks = Top of Primary stack\r |
130 | LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r | |
131 | add r1, r7, r2\r | |
132 | \r | |
82325f95 | 133 | // r7 = The base of the MpCore Stacks (primary stack + cluster_count * 4 * secondary stacks)\r |
1377db63 | 134 | // r1 = The base of the secondary Stacks = Top of the Primary stack\r |
2dbcb8f0 | 135 | \r |
136 | // Is it the Primary Core ?\r | |
137 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4)\r | |
99565b88 | 138 | cmp r5, r4\r |
2dbcb8f0 | 139 | beq _SetupPrimaryCoreStack\r |
140 | \r | |
141 | _SetupSecondaryCoreStack\r | |
1377db63 | 142 | // r1 = The base of the secondary Stacks\r |
2dbcb8f0 | 143 | \r |
144 | // Get the position of the cores (ClusterId * 4) + CoreId\r | |
a32dae48 | 145 | GetCorePositionFromMpId(r0, r5, r4)\r |
2dbcb8f0 | 146 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
147 | add r0, r0, #1\r | |
148 | // Get the offset for the Secondary Stack\r | |
149 | mul r0, r0, r3\r | |
1377db63 | 150 | add sp, r1, r0\r |
2dbcb8f0 | 151 | \r |
cd872e40 | 152 | bne _PrepareArguments\r |
153 | \r | |
2dbcb8f0 | 154 | _SetupPrimaryCoreStack\r |
1377db63 | 155 | // r1 = Top of the primary stack\r |
2dbcb8f0 | 156 | LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r |
1377db63 | 157 | b _PreparePrimaryStack\r |
158 | \r | |
159 | _SetupUnicoreStack\r | |
160 | // The top of the Unicore Stack is in r1\r | |
161 | LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r2)\r | |
162 | LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r3)\r | |
2dbcb8f0 | 163 | \r |
1377db63 | 164 | // Calculate the bottom of the primary stack (StackBase)\r |
165 | sub r7, r1, r3\r | |
166 | \r | |
167 | _PreparePrimaryStack\r | |
2dbcb8f0 | 168 | // The reserved space for global variable must be 8-bytes aligned for pushing\r |
169 | // 64-bit variable on the stack\r | |
170 | SetPrimaryStack (r1, r2, r3)\r | |
171 | \r | |
cd872e40 | 172 | _PrepareArguments\r |
c524ffbb | 173 | mov r0, r5\r |
174 | mov r1, r6\r | |
175 | mov r2, r7\r | |
176 | mov r3, sp\r | |
177 | \r | |
cd872e40 | 178 | // Move sec startup address into a data register\r |
179 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
c524ffbb | 180 | ldr r4, StartupAddr\r |
cd872e40 | 181 | \r |
d269095b | 182 | // Jump to PrePiCore C code\r |
0787bc61 | 183 | // r0 = MpId\r |
cd872e40 | 184 | // r1 = UefiMemoryBase\r |
c524ffbb | 185 | // r2 = StacksBase\r |
186 | // r3 = GlobalVariableBase\r | |
187 | blx r4\r | |
cd872e40 | 188 | \r |
2dbcb8f0 | 189 | _NeverReturn\r |
190 | b _NeverReturn\r | |
191 | \r | |
cd872e40 | 192 | END\r |