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cd872e40 | 1 | /** @file\r |
5a5440d0 PG |
2 | \r |
3 | Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r | |
4 | \r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
cd872e40 | 7 | **/\r |
8 | \r | |
9 | #include <PiPei.h>\r | |
10 | \r | |
492679a5 | 11 | #include <Library/CacheMaintenanceLib.h>\r |
cd872e40 | 12 | #include <Library/DebugAgentLib.h>\r |
13 | #include <Library/PrePiLib.h>\r | |
cd872e40 | 14 | #include <Library/PrintLib.h>\r |
37573927 | 15 | #include <Library/PrePiHobListPointerLib.h>\r |
cd872e40 | 16 | #include <Library/TimerLib.h>\r |
17 | #include <Library/PerformanceLib.h>\r | |
18 | \r | |
19 | #include <Ppi/GuidedSectionExtraction.h>\r | |
0dbbacdf | 20 | #include <Ppi/ArmMpCoreInfo.h>\r |
a63be426 | 21 | #include <Ppi/SecPerformance.h>\r |
cd872e40 | 22 | \r |
23 | #include "PrePi.h"\r | |
cd872e40 | 24 | \r |
40b0b23e | 25 | #define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) ||\\r |
d6607d8b | 26 | ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))\r |
8fc38a3f | 27 | \r |
40b0b23e MK |
28 | UINT64 mSystemMemoryEnd = FixedPcdGet64 (PcdSystemMemoryBase) +\r |
29 | FixedPcdGet64 (PcdSystemMemorySize) - 1;\r | |
4aae7419 | 30 | \r |
0dbbacdf | 31 | EFI_STATUS\r |
32 | GetPlatformPpi (\r | |
33 | IN EFI_GUID *PpiGuid,\r | |
34 | OUT VOID **Ppi\r | |
35 | )\r | |
36 | {\r | |
37 | UINTN PpiListSize;\r | |
38 | UINTN PpiListCount;\r | |
39 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
40 | UINTN Index;\r | |
41 | \r | |
42 | PpiListSize = 0;\r | |
43 | ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r | |
40b0b23e | 44 | PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);\r |
0dbbacdf | 45 | for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r |
46 | if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r | |
47 | *Ppi = PpiList->Ppi;\r | |
48 | return EFI_SUCCESS;\r | |
49 | }\r | |
50 | }\r | |
51 | \r | |
52 | return EFI_NOT_FOUND;\r | |
53 | }\r | |
54 | \r | |
cd872e40 | 55 | VOID\r |
56 | PrePiMain (\r | |
40b0b23e MK |
57 | IN UINTN UefiMemoryBase,\r |
58 | IN UINTN StacksBase,\r | |
59 | IN UINT64 StartTimeStamp\r | |
cd872e40 | 60 | )\r |
61 | {\r | |
40b0b23e MK |
62 | EFI_HOB_HANDOFF_INFO_TABLE *HobList;\r |
63 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
64 | UINTN ArmCoreCount;\r | |
65 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
66 | EFI_STATUS Status;\r | |
67 | CHAR8 Buffer[100];\r | |
68 | UINTN CharCount;\r | |
69 | UINTN StacksSize;\r | |
70 | FIRMWARE_SEC_PERFORMANCE Performance;\r | |
cd872e40 | 71 | \r |
8fc38a3f | 72 | // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)\r |
40b0b23e MK |
73 | ASSERT (\r |
74 | IS_XIP () ||\r | |
75 | ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&\r | |
76 | ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd))\r | |
77 | );\r | |
8fc38a3f | 78 | \r |
1bc83266 HL |
79 | // Initialize the architecture specific bits\r |
80 | ArchInitialize ();\r | |
cd872e40 | 81 | \r |
82 | // Initialize the Serial Port\r | |
83 | SerialPortInitialize ();\r | |
40b0b23e MK |
84 | CharCount = AsciiSPrint (\r |
85 | Buffer,\r | |
86 | sizeof (Buffer),\r | |
87 | "UEFI firmware (version %s built at %a on %a)\n\r",\r | |
88 | (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),\r | |
89 | __TIME__,\r | |
90 | __DATE__\r | |
91 | );\r | |
92 | SerialPortWrite ((UINT8 *)Buffer, CharCount);\r | |
cd872e40 | 93 | \r |
94 | // Initialize the Debug Agent for Source Level Debugging\r | |
95 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
96 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
3402aac7 | 97 | \r |
d269095b | 98 | // Declare the PI/UEFI memory region\r |
37573927 | 99 | HobList = HobConstructor (\r |
40b0b23e MK |
100 | (VOID *)UefiMemoryBase,\r |
101 | FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r | |
102 | (VOID *)UefiMemoryBase,\r | |
103 | (VOID *)StacksBase // The top of the UEFI Memory is reserved for the stacks\r | |
104 | );\r | |
37573927 | 105 | PrePeiSetHobList (HobList);\r |
cd872e40 | 106 | \r |
107 | // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r | |
108 | Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r | |
109 | ASSERT_EFI_ERROR (Status);\r | |
110 | \r | |
d269095b | 111 | // Create the Stacks HOB (reserve the memory for all stacks)\r |
99565b88 | 112 | if (ArmIsMpCore ()) {\r |
81514a8a OM |
113 | StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +\r |
114 | ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));\r | |
99565b88 | 115 | } else {\r |
116 | StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r | |
117 | }\r | |
40b0b23e | 118 | \r |
d269095b | 119 | BuildStackHob (StacksBase, StacksSize);\r |
cd872e40 | 120 | \r |
40b0b23e | 121 | // TODO: Call CpuPei as a library\r |
e0ec9a12 | 122 | BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));\r |
44788bae | 123 | \r |
0dbbacdf | 124 | if (ArmIsMpCore ()) {\r |
125 | // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r | |
40b0b23e | 126 | Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCoreInfoPpi);\r |
0dbbacdf | 127 | \r |
128 | // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r | |
129 | ASSERT_EFI_ERROR (Status);\r | |
130 | \r | |
131 | // Build the MP Core Info Table\r | |
132 | ArmCoreCount = 0;\r | |
40b0b23e MK |
133 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r |
134 | if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {\r | |
0dbbacdf | 135 | // Build MPCore Info HOB\r |
136 | BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r | |
137 | }\r | |
138 | }\r | |
139 | \r | |
a63be426 AF |
140 | // Store timer value logged at the beginning of firmware image execution\r |
141 | Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);\r | |
142 | \r | |
143 | // Build SEC Performance Data Hob\r | |
144 | BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));\r | |
145 | \r | |
cd872e40 | 146 | // Set the Boot Mode\r |
147 | SetBootMode (ArmPlatformGetBootMode ());\r | |
148 | \r | |
149 | // Initialize Platform HOBs (CpuHob and FvHob)\r | |
150 | Status = PlatformPeim ();\r | |
151 | ASSERT_EFI_ERROR (Status);\r | |
152 | \r | |
cd872e40 | 153 | // Now, the HOB List has been initialized, we can register performance information\r |
154 | PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r | |
155 | \r | |
156 | // SEC phase needs to run library constructors by hand.\r | |
6efd58aa | 157 | ProcessLibraryConstructorList ();\r |
cd872e40 | 158 | \r |
cd872e40 | 159 | // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r |
160 | Status = DecompressFirstFv ();\r | |
161 | ASSERT_EFI_ERROR (Status);\r | |
162 | \r | |
163 | // Load the DXE Core and transfer control to it\r | |
164 | Status = LoadDxeCoreFromFv (NULL, 0);\r | |
165 | ASSERT_EFI_ERROR (Status);\r | |
166 | }\r | |
167 | \r | |
168 | VOID\r | |
169 | CEntryPoint (\r | |
40b0b23e MK |
170 | IN UINTN MpId,\r |
171 | IN UINTN UefiMemoryBase,\r | |
172 | IN UINTN StacksBase\r | |
cd872e40 | 173 | )\r |
174 | {\r | |
40b0b23e | 175 | UINT64 StartTimeStamp;\r |
3402aac7 | 176 | \r |
f437141a | 177 | // Initialize the platform specific controllers\r |
178 | ArmPlatformInitialize (MpId);\r | |
179 | \r | |
bebda7ce | 180 | if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {\r |
cd872e40 | 181 | // Initialize the Timer Library to setup the Timer HW controller\r |
182 | TimerConstructor ();\r | |
183 | // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r | |
184 | StartTimeStamp = GetPerformanceCounter ();\r | |
2ee85366 | 185 | } else {\r |
186 | StartTimeStamp = 0;\r | |
cd872e40 | 187 | }\r |
188 | \r | |
6dafb303 OM |
189 | // Data Cache enabled on Primary core when MMU is enabled.\r |
190 | ArmDisableDataCache ();\r | |
d269095b | 191 | // Invalidate instruction cache\r |
192 | ArmInvalidateInstructionCache ();\r | |
6dafb303 | 193 | // Enable Instruction Caches on all cores.\r |
d269095b | 194 | ArmEnableInstructionCache ();\r |
cd872e40 | 195 | \r |
99565b88 | 196 | // Define the Global Variable region when we are not running in XIP\r |
40b0b23e | 197 | if (!IS_XIP ()) {\r |
bebda7ce | 198 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
40b0b23e | 199 | if (ArmIsMpCore ()) {\r |
b1d41be7 | 200 | // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r |
201 | ArmCallSEV ();\r | |
1aa9860e | 202 | }\r |
99565b88 | 203 | } else {\r |
16f3544d | 204 | // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r |
b1d41be7 | 205 | ArmCallWFE ();\r |
99565b88 | 206 | }\r |
207 | }\r | |
3402aac7 | 208 | \r |
d269095b | 209 | // If not primary Jump to Secondary Main\r |
bebda7ce | 210 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
40b0b23e MK |
211 | InvalidateDataCacheRange (\r |
212 | (VOID *)UefiMemoryBase,\r | |
213 | FixedPcdGet32 (PcdSystemMemoryUefiRegionSize)\r | |
214 | );\r | |
492679a5 | 215 | \r |
cd872e40 | 216 | // Goto primary Main.\r |
f2e17a07 | 217 | PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r |
cd872e40 | 218 | } else {\r |
0787bc61 | 219 | SecondaryMain (MpId);\r |
cd872e40 | 220 | }\r |
221 | \r | |
222 | // DXE Core should always load and never return\r | |
223 | ASSERT (FALSE);\r | |
224 | }\r |