ArmPlatformPkg/PrePi: replace set/way cache ops with by-VA ones

[mirror_edk2.git] / ArmPlatformPkg / PrePi / PrePi.c

/** @file\r
*\r
*  Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
*\r
*  SPDX-License-Identifier: BSD-2-Clause-Patent\r
*\r
**/\r
\r
#include <PiPei.h>\r
\r
#include <Library/CacheMaintenanceLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <Library/PrePiLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/PrePiHobListPointerLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/PerformanceLib.h>\r
\r
#include <Ppi/GuidedSectionExtraction.h>\r
#include <Ppi/ArmMpCoreInfo.h>\r
#include <Ppi/SecPerformance.h>\r
\r
#include "PrePi.h"\r
\r
#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \\r
                  ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= FixedPcdGet64 (PcdSystemMemoryBase)))\r
\r
UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +\r
                          FixedPcdGet64(PcdSystemMemorySize) - 1;\r
\r
EFI_STATUS\r
GetPlatformPpi (\r
  IN  EFI_GUID  *PpiGuid,\r
  OUT VOID      **Ppi\r
  )\r
{\r
  UINTN                   PpiListSize;\r
  UINTN                   PpiListCount;\r
  EFI_PEI_PPI_DESCRIPTOR  *PpiList;\r
  UINTN                   Index;\r
\r
  PpiListSize = 0;\r
  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
    if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r
      *Ppi = PpiList->Ppi;\r
      return EFI_SUCCESS;\r
    }\r
  }\r
\r
  return EFI_NOT_FOUND;\r
}\r
\r
VOID\r
PrePiMain (\r
  IN  UINTN                     UefiMemoryBase,\r
  IN  UINTN                     StacksBase,\r
  IN  UINT64                    StartTimeStamp\r
  )\r
{\r
  EFI_HOB_HANDOFF_INFO_TABLE*   HobList;\r
  ARM_MP_CORE_INFO_PPI*         ArmMpCoreInfoPpi;\r
  UINTN                         ArmCoreCount;\r
  ARM_CORE_INFO*                ArmCoreInfoTable;\r
  EFI_STATUS                    Status;\r
  CHAR8                         Buffer[100];\r
  UINTN                         CharCount;\r
  UINTN                         StacksSize;\r
  FIRMWARE_SEC_PERFORMANCE      Performance;\r
\r
  // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)\r
  ASSERT (IS_XIP() ||\r
          ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&\r
           ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));\r
\r
  // Initialize the architecture specific bits\r
  ArchInitialize ();\r
\r
  // Initialize the Serial Port\r
  SerialPortInitialize ();\r
  CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",\r
    (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
  SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
\r
  // Initialize the Debug Agent for Source Level Debugging\r
  InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
  SaveAndSetDebugTimerInterrupt (TRUE);\r
\r
  // Declare the PI/UEFI memory region\r
  HobList = HobConstructor (\r
    (VOID*)UefiMemoryBase,\r
    FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r
    (VOID*)UefiMemoryBase,\r
    (VOID*)StacksBase  // The top of the UEFI Memory is reserved for the stacks\r
    );\r
  PrePeiSetHobList (HobList);\r
\r
  // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r
  Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r
  ASSERT_EFI_ERROR (Status);\r
\r
  // Create the Stacks HOB (reserve the memory for all stacks)\r
  if (ArmIsMpCore ()) {\r
    StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +\r
                 ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));\r
  } else {\r
    StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r
  }\r
  BuildStackHob (StacksBase, StacksSize);\r
\r
  //TODO: Call CpuPei as a library\r
  BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));\r
\r
  if (ArmIsMpCore ()) {\r
    // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r
    Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
\r
    // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
    ASSERT_EFI_ERROR (Status);\r
\r
    // Build the MP Core Info Table\r
    ArmCoreCount = 0;\r
    Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
    if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {\r
      // Build MPCore Info HOB\r
      BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r
    }\r
  }\r
\r
  // Store timer value logged at the beginning of firmware image execution\r
  Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);\r
\r
  // Build SEC Performance Data Hob\r
  BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));\r
\r
  // Set the Boot Mode\r
  SetBootMode (ArmPlatformGetBootMode ());\r
\r
  // Initialize Platform HOBs (CpuHob and FvHob)\r
  Status = PlatformPeim ();\r
  ASSERT_EFI_ERROR (Status);\r
\r
  // Now, the HOB List has been initialized, we can register performance information\r
  PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r
\r
  // SEC phase needs to run library constructors by hand.\r
  ProcessLibraryConstructorList ();\r
\r
  // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
  Status = DecompressFirstFv ();\r
  ASSERT_EFI_ERROR (Status);\r
\r
  // Load the DXE Core and transfer control to it\r
  Status = LoadDxeCoreFromFv (NULL, 0);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
VOID\r
CEntryPoint (\r
  IN  UINTN                     MpId,\r
  IN  UINTN                     UefiMemoryBase,\r
  IN  UINTN                     StacksBase\r
  )\r
{\r
  UINT64   StartTimeStamp;\r
\r
  // Initialize the platform specific controllers\r
  ArmPlatformInitialize (MpId);\r
\r
  if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {\r
    // Initialize the Timer Library to setup the Timer HW controller\r
    TimerConstructor ();\r
    // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
    StartTimeStamp = GetPerformanceCounter ();\r
  } else {\r
    StartTimeStamp = 0;\r
  }\r
\r
  // Data Cache enabled on Primary core when MMU is enabled.\r
  ArmDisableDataCache ();\r
  // Invalidate instruction cache\r
  ArmInvalidateInstructionCache ();\r
  // Enable Instruction Caches on all cores.\r
  ArmEnableInstructionCache ();\r
\r
  // Define the Global Variable region when we are not running in XIP\r
  if (!IS_XIP()) {\r
    if (ArmPlatformIsPrimaryCore (MpId)) {\r
      if (ArmIsMpCore()) {\r
        // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r
        ArmCallSEV ();\r
      }\r
    } else {\r
      // Wait the Primary core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r
      ArmCallWFE ();\r
    }\r
  }\r
\r
  // If not primary Jump to Secondary Main\r
  if (ArmPlatformIsPrimaryCore (MpId)) {\r
\r
    InvalidateDataCacheRange ((VOID *)UefiMemoryBase,\r
                              FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r
\r
    // Goto primary Main.\r
    PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
  } else {\r
    SecondaryMain (MpId);\r
  }\r
\r
  // DXE Core should always load and never return\r
  ASSERT (FALSE);\r
}\r