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ArmPlatformPkg/PrePi: call all constructors by hand
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cd872e40 1/** @file\r
2*\r
a63be426 3* Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
cd872e40 4*\r
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12*\r
13**/\r
14\r
15#include <PiPei.h>\r
16\r
17#include <Library/DebugAgentLib.h>\r
18#include <Library/PrePiLib.h>\r
cd872e40 19#include <Library/PrintLib.h>\r
20#include <Library/PeCoffGetEntryPointLib.h>\r
37573927 21#include <Library/PrePiHobListPointerLib.h>\r
cd872e40 22#include <Library/TimerLib.h>\r
23#include <Library/PerformanceLib.h>\r
24\r
25#include <Ppi/GuidedSectionExtraction.h>\r
0dbbacdf 26#include <Ppi/ArmMpCoreInfo.h>\r
a63be426 27#include <Ppi/SecPerformance.h>\r
cd872e40 28#include <Guid/LzmaDecompress.h>\r
29\r
30#include "PrePi.h"\r
31#include "LzmaDecompress.h"\r
32\r
91673dfd
LD
33#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \\r
34 ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))\r
8fc38a3f 35\r
4aae7419
AB
36UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +\r
37 FixedPcdGet64(PcdSystemMemorySize) - 1;\r
38\r
0dbbacdf 39EFI_STATUS\r
40GetPlatformPpi (\r
41 IN EFI_GUID *PpiGuid,\r
42 OUT VOID **Ppi\r
43 )\r
44{\r
45 UINTN PpiListSize;\r
46 UINTN PpiListCount;\r
47 EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
48 UINTN Index;\r
49\r
50 PpiListSize = 0;\r
51 ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
52 PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
53 for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
54 if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r
55 *Ppi = PpiList->Ppi;\r
56 return EFI_SUCCESS;\r
57 }\r
58 }\r
59\r
60 return EFI_NOT_FOUND;\r
61}\r
62\r
cd872e40 63VOID\r
64PrePiMain (\r
65 IN UINTN UefiMemoryBase,\r
c524ffbb 66 IN UINTN StacksBase,\r
cd872e40 67 IN UINT64 StartTimeStamp\r
68 )\r
69{\r
37573927 70 EFI_HOB_HANDOFF_INFO_TABLE* HobList;\r
0dbbacdf 71 ARM_MP_CORE_INFO_PPI* ArmMpCoreInfoPpi;\r
72 UINTN ArmCoreCount;\r
73 ARM_CORE_INFO* ArmCoreInfoTable;\r
cd872e40 74 EFI_STATUS Status;\r
75 CHAR8 Buffer[100];\r
76 UINTN CharCount;\r
d269095b 77 UINTN StacksSize;\r
a63be426 78 FIRMWARE_SEC_PERFORMANCE Performance;\r
cd872e40 79\r
8fc38a3f 80 // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)\r
3402aac7 81 ASSERT (IS_XIP() ||\r
91673dfd
LD
82 ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&\r
83 ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));\r
8fc38a3f 84\r
1bc83266
HL
85 // Initialize the architecture specific bits\r
86 ArchInitialize ();\r
cd872e40 87\r
88 // Initialize the Serial Port\r
89 SerialPortInitialize ();\r
37363dff 90 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",\r
91 (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
cd872e40 92 SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
93\r
94 // Initialize the Debug Agent for Source Level Debugging\r
95 InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
96 SaveAndSetDebugTimerInterrupt (TRUE);\r
3402aac7 97\r
d269095b 98 // Declare the PI/UEFI memory region\r
37573927 99 HobList = HobConstructor (\r
cd872e40 100 (VOID*)UefiMemoryBase,\r
101 FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r
102 (VOID*)UefiMemoryBase,\r
d269095b 103 (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks\r
104 );\r
37573927 105 PrePeiSetHobList (HobList);\r
cd872e40 106\r
107 // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r
108 Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r
109 ASSERT_EFI_ERROR (Status);\r
110\r
d269095b 111 // Create the Stacks HOB (reserve the memory for all stacks)\r
99565b88 112 if (ArmIsMpCore ()) {\r
81514a8a
OM
113 StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +\r
114 ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));\r
99565b88 115 } else {\r
116 StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r
117 }\r
d269095b 118 BuildStackHob (StacksBase, StacksSize);\r
cd872e40 119\r
44788bae 120 //TODO: Call CpuPei as a library\r
121 BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
122\r
0dbbacdf 123 if (ArmIsMpCore ()) {\r
124 // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r
125 Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
126\r
127 // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
128 ASSERT_EFI_ERROR (Status);\r
129\r
130 // Build the MP Core Info Table\r
131 ArmCoreCount = 0;\r
132 Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
133 if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {\r
134 // Build MPCore Info HOB\r
135 BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r
136 }\r
137 }\r
138\r
a63be426
AF
139 // Store timer value logged at the beginning of firmware image execution\r
140 Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);\r
141\r
142 // Build SEC Performance Data Hob\r
143 BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));\r
144\r
cd872e40 145 // Set the Boot Mode\r
146 SetBootMode (ArmPlatformGetBootMode ());\r
147\r
148 // Initialize Platform HOBs (CpuHob and FvHob)\r
149 Status = PlatformPeim ();\r
150 ASSERT_EFI_ERROR (Status);\r
151\r
cd872e40 152 // Now, the HOB List has been initialized, we can register performance information\r
153 PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r
154\r
155 // SEC phase needs to run library constructors by hand.\r
6efd58aa 156 ProcessLibraryConstructorList ();\r
cd872e40 157\r
158 // Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
159 BuildPeCoffLoaderHob ();\r
160 BuildExtractSectionHob (\r
161 &gLzmaCustomDecompressGuid,\r
162 LzmaGuidedSectionGetInfo,\r
163 LzmaGuidedSectionExtraction\r
164 );\r
165\r
166 // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
167 Status = DecompressFirstFv ();\r
168 ASSERT_EFI_ERROR (Status);\r
169\r
170 // Load the DXE Core and transfer control to it\r
171 Status = LoadDxeCoreFromFv (NULL, 0);\r
172 ASSERT_EFI_ERROR (Status);\r
173}\r
174\r
175VOID\r
176CEntryPoint (\r
0787bc61 177 IN UINTN MpId,\r
c524ffbb 178 IN UINTN UefiMemoryBase,\r
f2e17a07 179 IN UINTN StacksBase\r
cd872e40 180 )\r
181{\r
182 UINT64 StartTimeStamp;\r
3402aac7 183\r
f437141a 184 // Initialize the platform specific controllers\r
185 ArmPlatformInitialize (MpId);\r
186\r
bebda7ce 187 if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {\r
cd872e40 188 // Initialize the Timer Library to setup the Timer HW controller\r
189 TimerConstructor ();\r
190 // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
191 StartTimeStamp = GetPerformanceCounter ();\r
2ee85366 192 } else {\r
193 StartTimeStamp = 0;\r
cd872e40 194 }\r
195\r
6dafb303
OM
196 // Data Cache enabled on Primary core when MMU is enabled.\r
197 ArmDisableDataCache ();\r
198 // Invalidate Data cache\r
199 ArmInvalidateDataCache ();\r
d269095b 200 // Invalidate instruction cache\r
201 ArmInvalidateInstructionCache ();\r
6dafb303 202 // Enable Instruction Caches on all cores.\r
d269095b 203 ArmEnableInstructionCache ();\r
cd872e40 204\r
99565b88 205 // Define the Global Variable region when we are not running in XIP\r
206 if (!IS_XIP()) {\r
bebda7ce 207 if (ArmPlatformIsPrimaryCore (MpId)) {\r
1aa9860e 208 if (ArmIsMpCore()) {\r
b1d41be7 209 // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r
210 ArmCallSEV ();\r
1aa9860e 211 }\r
99565b88 212 } else {\r
b1d41be7 213 // Wait the Primay core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r
214 ArmCallWFE ();\r
99565b88 215 }\r
216 }\r
3402aac7 217\r
d269095b 218 // If not primary Jump to Secondary Main\r
bebda7ce 219 if (ArmPlatformIsPrimaryCore (MpId)) {\r
cd872e40 220 // Goto primary Main.\r
f2e17a07 221 PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
cd872e40 222 } else {\r
0787bc61 223 SecondaryMain (MpId);\r
cd872e40 224 }\r
225\r
226 // DXE Core should always load and never return\r
227 ASSERT (FALSE);\r
228}\r
229\r