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cd872e40 1/** @file\r
2*\r
a63be426 3* Copyright (c) 2011-2017, ARM Limited. All rights reserved.\r
cd872e40 4*\r
5* This program and the accompanying materials\r
6* are licensed and made available under the terms and conditions of the BSD License\r
7* which accompanies this distribution. The full text of the license may be found at\r
8* http://opensource.org/licenses/bsd-license.php\r
9*\r
10* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12*\r
13**/\r
14\r
15#include <PiPei.h>\r
16\r
17#include <Library/DebugAgentLib.h>\r
18#include <Library/PrePiLib.h>\r
cd872e40 19#include <Library/PrintLib.h>\r
20#include <Library/PeCoffGetEntryPointLib.h>\r
37573927 21#include <Library/PrePiHobListPointerLib.h>\r
cd872e40 22#include <Library/TimerLib.h>\r
23#include <Library/PerformanceLib.h>\r
24\r
25#include <Ppi/GuidedSectionExtraction.h>\r
0dbbacdf 26#include <Ppi/ArmMpCoreInfo.h>\r
a63be426 27#include <Ppi/SecPerformance.h>\r
cd872e40 28#include <Guid/LzmaDecompress.h>\r
29\r
30#include "PrePi.h"\r
31#include "LzmaDecompress.h"\r
32\r
91673dfd
LD
33#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMemoryEnd) || \\r
34 ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))\r
8fc38a3f 35\r
4aae7419
AB
36UINT64 mSystemMemoryEnd = FixedPcdGet64(PcdSystemMemoryBase) +\r
37 FixedPcdGet64(PcdSystemMemorySize) - 1;\r
38\r
cd872e40 39EFI_STATUS\r
40EFIAPI\r
41ExtractGuidedSectionLibConstructor (\r
42 VOID\r
43 );\r
44\r
45EFI_STATUS\r
46EFIAPI\r
47LzmaDecompressLibConstructor (\r
48 VOID\r
49 );\r
50\r
0dbbacdf 51EFI_STATUS\r
52GetPlatformPpi (\r
53 IN EFI_GUID *PpiGuid,\r
54 OUT VOID **Ppi\r
55 )\r
56{\r
57 UINTN PpiListSize;\r
58 UINTN PpiListCount;\r
59 EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
60 UINTN Index;\r
61\r
62 PpiListSize = 0;\r
63 ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
64 PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
65 for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
66 if (CompareGuid (PpiList->Guid, PpiGuid) == TRUE) {\r
67 *Ppi = PpiList->Ppi;\r
68 return EFI_SUCCESS;\r
69 }\r
70 }\r
71\r
72 return EFI_NOT_FOUND;\r
73}\r
74\r
cd872e40 75VOID\r
76PrePiMain (\r
77 IN UINTN UefiMemoryBase,\r
c524ffbb 78 IN UINTN StacksBase,\r
cd872e40 79 IN UINT64 StartTimeStamp\r
80 )\r
81{\r
37573927 82 EFI_HOB_HANDOFF_INFO_TABLE* HobList;\r
0dbbacdf 83 ARM_MP_CORE_INFO_PPI* ArmMpCoreInfoPpi;\r
84 UINTN ArmCoreCount;\r
85 ARM_CORE_INFO* ArmCoreInfoTable;\r
cd872e40 86 EFI_STATUS Status;\r
87 CHAR8 Buffer[100];\r
88 UINTN CharCount;\r
d269095b 89 UINTN StacksSize;\r
a63be426 90 FIRMWARE_SEC_PERFORMANCE Performance;\r
cd872e40 91\r
8fc38a3f 92 // If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)\r
3402aac7 93 ASSERT (IS_XIP() ||\r
91673dfd
LD
94 ((FixedPcdGet64 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&\r
95 ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT64)mSystemMemoryEnd)));\r
8fc38a3f 96\r
1bc83266
HL
97 // Initialize the architecture specific bits\r
98 ArchInitialize ();\r
cd872e40 99\r
100 // Initialize the Serial Port\r
101 SerialPortInitialize ();\r
37363dff 102 CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"UEFI firmware (version %s built at %a on %a)\n\r",\r
103 (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
cd872e40 104 SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
105\r
106 // Initialize the Debug Agent for Source Level Debugging\r
107 InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r
108 SaveAndSetDebugTimerInterrupt (TRUE);\r
3402aac7 109\r
d269095b 110 // Declare the PI/UEFI memory region\r
37573927 111 HobList = HobConstructor (\r
cd872e40 112 (VOID*)UefiMemoryBase,\r
113 FixedPcdGet32 (PcdSystemMemoryUefiRegionSize),\r
114 (VOID*)UefiMemoryBase,\r
d269095b 115 (VOID*)StacksBase // The top of the UEFI Memory is reserved for the stacks\r
116 );\r
37573927 117 PrePeiSetHobList (HobList);\r
cd872e40 118\r
119 // Initialize MMU and Memory HOBs (Resource Descriptor HOBs)\r
120 Status = MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryUefiRegionSize));\r
121 ASSERT_EFI_ERROR (Status);\r
122\r
d269095b 123 // Create the Stacks HOB (reserve the memory for all stacks)\r
99565b88 124 if (ArmIsMpCore ()) {\r
81514a8a
OM
125 StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize) +\r
126 ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (PcdCPUCoreSecondaryStackSize));\r
99565b88 127 } else {\r
128 StacksSize = PcdGet32 (PcdCPUCorePrimaryStackSize);\r
129 }\r
d269095b 130 BuildStackHob (StacksBase, StacksSize);\r
cd872e40 131\r
44788bae 132 //TODO: Call CpuPei as a library\r
133 BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
134\r
0dbbacdf 135 if (ArmIsMpCore ()) {\r
136 // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r
137 Status = GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID**)&ArmMpCoreInfoPpi);\r
138\r
139 // On MP Core Platform we must implement the ARM MP Core Info PPI (gArmMpCoreInfoPpiGuid)\r
140 ASSERT_EFI_ERROR (Status);\r
141\r
142 // Build the MP Core Info Table\r
143 ArmCoreCount = 0;\r
144 Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
145 if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {\r
146 // Build MPCore Info HOB\r
147 BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r
148 }\r
149 }\r
150\r
a63be426
AF
151 // Store timer value logged at the beginning of firmware image execution\r
152 Performance.ResetEnd = GetTimeInNanoSecond (StartTimeStamp);\r
153\r
154 // Build SEC Performance Data Hob\r
155 BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (Performance));\r
156\r
cd872e40 157 // Set the Boot Mode\r
158 SetBootMode (ArmPlatformGetBootMode ());\r
159\r
160 // Initialize Platform HOBs (CpuHob and FvHob)\r
161 Status = PlatformPeim ();\r
162 ASSERT_EFI_ERROR (Status);\r
163\r
cd872e40 164 // Now, the HOB List has been initialized, we can register performance information\r
165 PERF_START (NULL, "PEI", NULL, StartTimeStamp);\r
166\r
167 // SEC phase needs to run library constructors by hand.\r
168 ExtractGuidedSectionLibConstructor ();\r
169 LzmaDecompressLibConstructor ();\r
170\r
171 // Build HOBs to pass up our version of stuff the DXE Core needs to save space\r
172 BuildPeCoffLoaderHob ();\r
173 BuildExtractSectionHob (\r
174 &gLzmaCustomDecompressGuid,\r
175 LzmaGuidedSectionGetInfo,\r
176 LzmaGuidedSectionExtraction\r
177 );\r
178\r
179 // Assume the FV that contains the SEC (our code) also contains a compressed FV.\r
180 Status = DecompressFirstFv ();\r
181 ASSERT_EFI_ERROR (Status);\r
182\r
183 // Load the DXE Core and transfer control to it\r
184 Status = LoadDxeCoreFromFv (NULL, 0);\r
185 ASSERT_EFI_ERROR (Status);\r
186}\r
187\r
188VOID\r
189CEntryPoint (\r
0787bc61 190 IN UINTN MpId,\r
c524ffbb 191 IN UINTN UefiMemoryBase,\r
f2e17a07 192 IN UINTN StacksBase\r
cd872e40 193 )\r
194{\r
195 UINT64 StartTimeStamp;\r
3402aac7 196\r
f437141a 197 // Initialize the platform specific controllers\r
198 ArmPlatformInitialize (MpId);\r
199\r
bebda7ce 200 if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled ()) {\r
cd872e40 201 // Initialize the Timer Library to setup the Timer HW controller\r
202 TimerConstructor ();\r
203 // We cannot call yet the PerformanceLib because the HOB List has not been initialized\r
204 StartTimeStamp = GetPerformanceCounter ();\r
2ee85366 205 } else {\r
206 StartTimeStamp = 0;\r
cd872e40 207 }\r
208\r
6dafb303
OM
209 // Data Cache enabled on Primary core when MMU is enabled.\r
210 ArmDisableDataCache ();\r
211 // Invalidate Data cache\r
212 ArmInvalidateDataCache ();\r
d269095b 213 // Invalidate instruction cache\r
214 ArmInvalidateInstructionCache ();\r
6dafb303 215 // Enable Instruction Caches on all cores.\r
d269095b 216 ArmEnableInstructionCache ();\r
cd872e40 217\r
99565b88 218 // Define the Global Variable region when we are not running in XIP\r
219 if (!IS_XIP()) {\r
bebda7ce 220 if (ArmPlatformIsPrimaryCore (MpId)) {\r
1aa9860e 221 if (ArmIsMpCore()) {\r
b1d41be7 222 // Signal the Global Variable Region is defined (event: ARM_CPU_EVENT_DEFAULT)\r
223 ArmCallSEV ();\r
1aa9860e 224 }\r
99565b88 225 } else {\r
b1d41be7 226 // Wait the Primay core has defined the address of the Global Variable region (event: ARM_CPU_EVENT_DEFAULT)\r
227 ArmCallWFE ();\r
99565b88 228 }\r
229 }\r
3402aac7 230\r
d269095b 231 // If not primary Jump to Secondary Main\r
bebda7ce 232 if (ArmPlatformIsPrimaryCore (MpId)) {\r
cd872e40 233 // Goto primary Main.\r
f2e17a07 234 PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp);\r
cd872e40 235 } else {\r
0787bc61 236 SecondaryMain (MpId);\r
cd872e40 237 }\r
238\r
239 // DXE Core should always load and never return\r
240 ASSERT (FALSE);\r
241}\r
242\r