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1bc83266 1#========================================================================================\r
73ca5009 2# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
1bc83266
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3#\r
4# This program and the accompanying materials\r
5# are licensed and made available under the terms and conditions of the BSD License\r
6# which accompanies this distribution. The full text of the license may be found at\r
7# http:#opensource.org/licenses/bsd-license.php\r
8#\r
9# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11#\r
12#=======================================================================================\r
13\r
14#include <AsmMacroIoLibV8.h>\r
15#include <Chipset/AArch64.h>\r
16\r
17#start of the code section\r
18.text\r
19.align 3\r
20\r
919a3a02
BJ
21GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)\r
22GCC_ASM_EXPORT(enter_monitor_mode)\r
23GCC_ASM_EXPORT(return_from_exception)\r
24GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
25GCC_ASM_EXPORT(set_non_secure_mode)\r
1bc83266 26\r
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27// Switch from EL3 to NS-EL1\r
28ASM_PFX(SwitchToNSExceptionLevel1):\r
29 // Now setup our EL1. Controlled by EL2 config on Model\r
30 mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
31 orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
32\r
33 // Send all interrupts to their respective Exception levels for EL2\r
73ca5009 34 and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort\r
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35 msr hcr_el2, x0 // Write back our settings\r
36\r
37 msr cptr_el2, xzr // Disable copro traps to EL2\r
38\r
39 msr sctlr_el2, xzr\r
40\r
41 // Enable architected timer access\r
42 mrs x0, cnthctl_el2\r
43 orr x0, x0, #3 // Enable EL1 access to timers\r
44 msr cnthctl_el2, x0\r
45\r
46 mrs x0, cntkctl_el1\r
47 orr x0, x0, #3 // EL0 access to counters\r
48 msr cntkctl_el1, x0\r
49\r
50 // Set ID regs\r
51 mrs x0, midr_el1\r
52 mrs x1, mpidr_el1\r
53 msr vpidr_el2, x0\r
54 msr vmpidr_el2, x1\r
55\r
56 ret\r
57\r
58\r
59// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7\r
60// we don't need a mode switch, just setup the Arguments and jump.\r
61// x0: Monitor World EntryPoint\r
62// x1: MpId\r
63// x2: SecBootMode\r
64// x3: Secure Monitor mode stack\r
65ASM_PFX(enter_monitor_mode):\r
66 mov x4, x0 // Swap EntryPoint and MpId registers\r
67 mov x0, x1\r
68 mov x1, x2\r
69 mov x2, x3\r
70 br x4\r
71\r
72// Put the address in correct ELR_ELx and do a eret.\r
73// We may need to do some config before we change to another Mode.\r
74ASM_PFX(return_from_exception):\r
75 msr elr_el3, x0\r
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76 eret\r
77\r
78// For AArch64 we need to construct the spsr we want from individual bits and pieces.\r
79ASM_PFX(copy_cpsr_into_spsr):\r
80 mrs x0, CurrentEl // Get the current exception level we are running at.\r
81 mrs x1, SPSel // Which Stack are we using\r
82 orr x0, x0, x1\r
83 mrs x1, daif // Which interrupts are enabled\r
84 orr x0, x0, x1\r
85 msr spsr_el3, x0 // Write to spsr\r
86 ret\r
87\r
88// Get this from platform file.\r
89ASM_PFX(set_non_secure_mode):\r
90 msr spsr_el3, x0\r
91 ret\r
92\r
1bc83266 93ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r