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ARM Packages: use GCC_ASM_EXPORT to export functions
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1#========================================================================================\r
2# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
3#\r
4# This program and the accompanying materials\r
5# are licensed and made available under the terms and conditions of the BSD License\r
6# which accompanies this distribution. The full text of the license may be found at\r
7# http:#opensource.org/licenses/bsd-license.php\r
8#\r
9# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11#\r
12#=======================================================================================\r
13\r
14#include <AsmMacroIoLibV8.h>\r
15#include <Chipset/AArch64.h>\r
16\r
17#start of the code section\r
18.text\r
19.align 3\r
20\r
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21GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)\r
22GCC_ASM_EXPORT(enter_monitor_mode)\r
23GCC_ASM_EXPORT(return_from_exception)\r
24GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
25GCC_ASM_EXPORT(set_non_secure_mode)\r
1bc83266 26\r
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27// Switch from EL3 to NS-EL1\r
28ASM_PFX(SwitchToNSExceptionLevel1):\r
29 // Now setup our EL1. Controlled by EL2 config on Model\r
30 mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
31 orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
32\r
33 // Send all interrupts to their respective Exception levels for EL2\r
34 bic x0, x0, #(1 << 3) // Disable virtual FIQ\r
35 bic x0, x0, #(1 << 4) // Disable virtual IRQ\r
36 bic x0, x0, #(1 << 5) // Disable virtual SError and Abort\r
37 msr hcr_el2, x0 // Write back our settings\r
38\r
39 msr cptr_el2, xzr // Disable copro traps to EL2\r
40\r
41 msr sctlr_el2, xzr\r
42\r
43 // Enable architected timer access\r
44 mrs x0, cnthctl_el2\r
45 orr x0, x0, #3 // Enable EL1 access to timers\r
46 msr cnthctl_el2, x0\r
47\r
48 mrs x0, cntkctl_el1\r
49 orr x0, x0, #3 // EL0 access to counters\r
50 msr cntkctl_el1, x0\r
51\r
52 // Set ID regs\r
53 mrs x0, midr_el1\r
54 mrs x1, mpidr_el1\r
55 msr vpidr_el2, x0\r
56 msr vmpidr_el2, x1\r
57\r
58 ret\r
59\r
60\r
61// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7\r
62// we don't need a mode switch, just setup the Arguments and jump.\r
63// x0: Monitor World EntryPoint\r
64// x1: MpId\r
65// x2: SecBootMode\r
66// x3: Secure Monitor mode stack\r
67ASM_PFX(enter_monitor_mode):\r
68 mov x4, x0 // Swap EntryPoint and MpId registers\r
69 mov x0, x1\r
70 mov x1, x2\r
71 mov x2, x3\r
72 br x4\r
73\r
74// Put the address in correct ELR_ELx and do a eret.\r
75// We may need to do some config before we change to another Mode.\r
76ASM_PFX(return_from_exception):\r
77 msr elr_el3, x0\r
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78 eret\r
79\r
80// For AArch64 we need to construct the spsr we want from individual bits and pieces.\r
81ASM_PFX(copy_cpsr_into_spsr):\r
82 mrs x0, CurrentEl // Get the current exception level we are running at.\r
83 mrs x1, SPSel // Which Stack are we using\r
84 orr x0, x0, x1\r
85 mrs x1, daif // Which interrupts are enabled\r
86 orr x0, x0, x1\r
87 msr spsr_el3, x0 // Write to spsr\r
88 ret\r
89\r
90// Get this from platform file.\r
91ASM_PFX(set_non_secure_mode):\r
92 msr spsr_el3, x0\r
93 ret\r
94\r
1bc83266 95ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r