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90d6a1bb | 1 | //\r |
1377db63 | 2 | // Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r |
90d6a1bb | 3 | // \r |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AutoGen.h>\r | |
15 | #include <AsmMacroIoLib.h>\r | |
16 | #include "SecInternal.h"\r | |
17 | \r | |
18 | INCLUDE AsmMacroIoLib.inc\r | |
19 | \r | |
20 | IMPORT CEntryPoint\r | |
21 | IMPORT ArmPlatformSecBootAction\r | |
e314d564 | 22 | IMPORT ArmPlatformSecBootMemoryInit\r |
90d6a1bb | 23 | IMPORT ArmDisableInterrupts\r |
24 | IMPORT ArmDisableCachesAndMmu\r | |
25 | IMPORT ArmWriteVBar\r | |
26 | IMPORT ArmReadMpidr\r | |
b1d41be7 | 27 | IMPORT ArmCallWFE\r |
90d6a1bb | 28 | IMPORT SecVectorTable\r |
90d6a1bb | 29 | EXPORT _ModuleEntryPoint\r |
30 | \r | |
31 | PRESERVE8\r | |
32 | AREA SecEntryPoint, CODE, READONLY\r | |
33 | \r | |
34 | StartupAddr DCD CEntryPoint\r | |
35 | \r | |
a75568e9 | 36 | _ModuleEntryPoint FUNCTION\r |
90d6a1bb | 37 | // First ensure all interrupts are disabled\r |
38 | blx ArmDisableInterrupts\r | |
39 | \r | |
40 | // Ensure that the MMU and caches are off\r | |
41 | blx ArmDisableCachesAndMmu\r | |
42 | \r | |
a75568e9 | 43 | // By default, we are doing a cold boot\r |
44 | mov r10, #ARM_SEC_COLD_BOOT\r | |
45 | \r | |
90d6a1bb | 46 | // Jump to Platform Specific Boot Action function\r |
47 | blx ArmPlatformSecBootAction\r | |
48 | \r | |
49 | // Set VBAR to the start of the exception vectors in Secure Mode\r | |
50 | ldr r0, =SecVectorTable\r | |
51 | blx ArmWriteVBar\r | |
52 | \r | |
53 | _IdentifyCpu \r | |
54 | // Identify CPU ID\r | |
55 | bl ArmReadMpidr\r | |
56 | // Get ID of this CPU in Multicore system\r | |
57 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r | |
58 | and r5, r0, r1\r | |
59 | \r | |
60 | // Is it the Primary Core ?\r | |
1377db63 | 61 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r3)\r |
62 | cmp r5, r3\r | |
90d6a1bb | 63 | // Only the primary core initialize the memory (SMC)\r |
64 | beq _InitMem\r | |
65 | \r | |
66 | _WaitInitMem\r | |
a75568e9 | 67 | // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r |
68 | // Otherwise we have to wait the Primary Core to finish the initialization\r | |
69 | cmp r10, #ARM_SEC_COLD_BOOT\r | |
70 | bne _SetupSecondaryCoreStack\r | |
71 | \r | |
b1d41be7 | 72 | // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r |
73 | bl ArmCallWFE\r | |
90d6a1bb | 74 | // Now the Init Mem is initialized, we setup the secondary core stacks\r |
75 | b _SetupSecondaryCoreStack\r | |
76 | \r | |
77 | _InitMem\r | |
8cfd2e24 | 78 | // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r |
79 | cmp r10, #ARM_SEC_COLD_BOOT\r | |
80 | bne _SetupPrimaryCoreStack\r | |
81 | \r | |
90d6a1bb | 82 | // Initialize Init Boot Memory\r |
e314d564 | 83 | bl ArmPlatformSecBootMemoryInit\r |
90d6a1bb | 84 | \r |
85 | // Only Primary CPU could run this line (the secondary cores have jumped from _IdentifyCpu to _SetupStack)\r | |
86 | LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r5)\r | |
87 | \r | |
88 | _SetupPrimaryCoreStack\r | |
1377db63 | 89 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
90 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
91 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
92 | add r1, r1, r2\r | |
93 | \r | |
94 | LoadConstantToReg (FixedPcdGet32(PcdSecGlobalVariableSize), r2)\r | |
90d6a1bb | 95 | \r |
96 | // The reserved space for global variable must be 8-bytes aligned for pushing\r | |
97 | // 64-bit variable on the stack\r | |
1377db63 | 98 | SetPrimaryStack (r1, r2, r3)\r |
99 | b _PrepareArguments\r | |
90d6a1bb | 100 | \r |
101 | _SetupSecondaryCoreStack\r | |
1377db63 | 102 | // Get the top of the primary stacks (and the base of the secondary stacks)\r |
103 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r | |
104 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r | |
105 | add r1, r1, r2\r | |
106 | \r | |
90d6a1bb | 107 | // Get the Core Position (ClusterId * 4) + CoreId\r |
a32dae48 | 108 | GetCorePositionFromMpId(r0, r5, r2)\r |
90d6a1bb | 109 | // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r |
110 | add r0, r0, #1\r | |
111 | \r | |
90d6a1bb | 112 | // StackOffset = CorePos * StackSize\r |
1377db63 | 113 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r |
90d6a1bb | 114 | mul r0, r0, r2\r |
115 | // SP = StackBase + StackOffset\r | |
116 | add sp, r1, r0\r | |
117 | \r | |
90d6a1bb | 118 | _PrepareArguments\r |
119 | // Move sec startup address into a data register\r | |
120 | // Ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
121 | ldr r3, StartupAddr\r | |
122 | \r | |
123 | // Jump to SEC C code\r | |
124 | // r0 = mp_id\r | |
a75568e9 | 125 | // r1 = Boot Mode\r |
90d6a1bb | 126 | mov r0, r5\r |
a75568e9 | 127 | mov r1, r10\r |
90d6a1bb | 128 | blx r3\r |
a75568e9 | 129 | ENDFUNC\r |
90d6a1bb | 130 | \r |
131 | _NeverReturn\r | |
132 | b _NeverReturn\r | |
133 | END\r |