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a36d531f MC |
1 | #\r |
2 | # Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r | |
dfc28388 | 3 | # Copyright (c) 2016, Linaro Limited. All rights reserved.\r |
a36d531f MC |
4 | #\r |
5 | # This program and the accompanying materials\r | |
6 | # are licensed and made available under the terms and conditions of the BSD License\r | |
7 | # which accompanies this distribution. The full text of the license may be found at\r | |
8 | # http://opensource.org/licenses/bsd-license.php\r | |
9 | #\r | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | #\r | |
13 | #\r | |
14 | \r | |
15 | #include <AsmMacroIoLibV8.h>\r | |
a36d531f | 16 | #include <Library/ArmLib.h>\r |
a36d531f | 17 | \r |
dfc28388 | 18 | ASM_FUNC(ArmPlatformPeiBootAction)\r |
a36d531f MC |
19 | ret\r |
20 | \r | |
21 | //UINTN\r | |
22 | //ArmPlatformGetPrimaryCoreMpId (\r | |
23 | // VOID\r | |
24 | // );\r | |
dfc28388 AB |
25 | ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)\r |
26 | MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))\r | |
a36d531f MC |
27 | ret\r |
28 | \r | |
29 | //UINTN\r | |
30 | //ArmPlatformIsPrimaryCore (\r | |
31 | // IN UINTN MpId\r | |
32 | // );\r | |
dfc28388 | 33 | ASM_FUNC(ArmPlatformIsPrimaryCore)\r |
a36d531f MC |
34 | mov x0, #1\r |
35 | ret\r | |
36 | \r | |
37 | //UINTN\r | |
38 | //ArmPlatformGetCorePosition (\r | |
39 | // IN UINTN MpId\r | |
40 | // );\r | |
41 | // With this function: CorePos = (ClusterId * 4) + CoreId\r | |
dfc28388 | 42 | ASM_FUNC(ArmPlatformGetCorePosition)\r |
a36d531f MC |
43 | and x1, x0, #ARM_CORE_MASK\r |
44 | and x0, x0, #ARM_CLUSTER_MASK\r | |
45 | add x0, x1, x0, LSR #6\r | |
46 | ret\r | |
47 | \r | |
48 | //EFI_PHYSICAL_ADDRESS\r | |
49 | //GetPhysAddrTop (\r | |
50 | // VOID\r | |
51 | // );\r | |
dfc28388 | 52 | ASM_FUNC(ArmGetPhysAddrTop)\r |
a36d531f MC |
53 | mrs x0, id_aa64mmfr0_el1\r |
54 | adr x1, .LPARanges\r | |
55 | and x0, x0, #7\r | |
56 | ldrb w1, [x1, x0]\r | |
57 | mov x0, #1\r | |
58 | lsl x0, x0, x1\r | |
59 | ret\r | |
60 | \r | |
61 | //\r | |
62 | // Bits 0..2 of the AA64MFR0_EL1 system register encode the size of the\r | |
63 | // physical address space support on this CPU:\r | |
64 | // 0 == 32 bits, 1 == 36 bits, etc etc\r | |
65 | // 6 and 7 are reserved\r | |
66 | //\r | |
67 | .LPARanges:\r | |
68 | .byte 32, 36, 40, 42, 44, 48, -1, -1\r | |
69 | \r | |
70 | ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r |