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ad3359eb LE |
1 | /** @file\r |
2 | Functions in this library instance make use of MMIO functions in IoLib to\r | |
3 | access memory mapped PCI configuration space.\r | |
4 | \r | |
5 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r | |
6 | Library.\r | |
7 | \r | |
8 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r | |
9 | This program and the accompanying materials\r | |
10 | are licensed and made available under the terms and conditions of the BSD License\r | |
11 | which accompanies this distribution. The full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php.\r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | \r | |
20 | #include <Base.h>\r | |
21 | \r | |
22 | #include <Library/BaseLib.h>\r | |
23 | #include <Library/PciExpressLib.h>\r | |
24 | #include <Library/IoLib.h>\r | |
25 | #include <Library/DebugLib.h>\r | |
26 | #include <Library/PcdLib.h>\r | |
27 | \r | |
28 | \r | |
29 | /**\r | |
30 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
31 | only in the low 28 bits.\r | |
32 | \r | |
33 | @param A The address to validate.\r | |
34 | \r | |
35 | **/\r | |
36 | #define ASSERT_INVALID_PCI_ADDRESS(A) \\r | |
37 | ASSERT (((A) & ~0xfffffff) == 0)\r | |
38 | \r | |
39 | /**\r | |
d1c561f9 | 40 | Registers a PCI device so PCI configuration registers may be accessed after\r |
ad3359eb | 41 | SetVirtualAddressMap().\r |
d1c561f9 OM |
42 | \r |
43 | Registers the PCI device specified by Address so all the PCI configuration\r | |
44 | registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r | |
ad3359eb | 45 | is called.\r |
d1c561f9 | 46 | \r |
ad3359eb LE |
47 | If Address > 0x0FFFFFFF, then ASSERT().\r |
48 | \r | |
49 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
50 | Register.\r | |
d1c561f9 | 51 | \r |
ad3359eb | 52 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
d1c561f9 | 53 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
ad3359eb LE |
54 | after ExitBootServices().\r |
55 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
56 | at runtime could not be mapped.\r | |
57 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
58 | complete the registration.\r | |
59 | \r | |
60 | **/\r | |
61 | RETURN_STATUS\r | |
62 | EFIAPI\r | |
63 | PciExpressRegisterForRuntimeAccess (\r | |
64 | IN UINTN Address\r | |
65 | )\r | |
66 | {\r | |
67 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
68 | return RETURN_UNSUPPORTED;\r | |
69 | }\r | |
70 | \r | |
71 | STATIC UINT64 mPciExpressBaseAddress;\r | |
72 | \r | |
73 | RETURN_STATUS\r | |
74 | EFIAPI\r | |
75 | PciExpressLibInitialize (\r | |
76 | VOID\r | |
77 | )\r | |
78 | {\r | |
79 | mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);\r | |
80 | return RETURN_SUCCESS;\r | |
81 | }\r | |
82 | \r | |
83 | \r | |
84 | /**\r | |
85 | Gets the base address of PCI Express.\r | |
d1c561f9 | 86 | \r |
ad3359eb LE |
87 | @return The base address of PCI Express.\r |
88 | \r | |
89 | **/\r | |
90 | VOID*\r | |
91 | GetPciExpressBaseAddress (\r | |
92 | VOID\r | |
93 | )\r | |
94 | {\r | |
95 | return (VOID*)(UINTN) mPciExpressBaseAddress;\r | |
96 | }\r | |
97 | \r | |
98 | /**\r | |
99 | Reads an 8-bit PCI configuration register.\r | |
100 | \r | |
101 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
102 | This function must guarantee that all PCI read and write operations are\r | |
103 | serialized.\r | |
104 | \r | |
105 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
106 | \r | |
107 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
108 | Register.\r | |
109 | \r | |
110 | @return The read value from the PCI configuration register.\r | |
111 | \r | |
112 | **/\r | |
113 | UINT8\r | |
114 | EFIAPI\r | |
115 | PciExpressRead8 (\r | |
116 | IN UINTN Address\r | |
117 | )\r | |
118 | {\r | |
119 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
120 | return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
121 | }\r | |
122 | \r | |
123 | /**\r | |
124 | Writes an 8-bit PCI configuration register.\r | |
125 | \r | |
126 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
127 | value specified by Value. Value is returned. This function must guarantee\r | |
128 | that all PCI read and write operations are serialized.\r | |
129 | \r | |
130 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
131 | \r | |
132 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
133 | Register.\r | |
134 | @param Value The value to write.\r | |
135 | \r | |
136 | @return The value written to the PCI configuration register.\r | |
137 | \r | |
138 | **/\r | |
139 | UINT8\r | |
140 | EFIAPI\r | |
141 | PciExpressWrite8 (\r | |
142 | IN UINTN Address,\r | |
143 | IN UINT8 Value\r | |
144 | )\r | |
145 | {\r | |
146 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
147 | return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
148 | }\r | |
149 | \r | |
150 | /**\r | |
151 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
152 | an 8-bit value.\r | |
153 | \r | |
154 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
155 | bitwise OR between the read result and the value specified by\r | |
156 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
157 | specified by Address. The value written to the PCI configuration register is\r | |
158 | returned. This function must guarantee that all PCI read and write operations\r | |
159 | are serialized.\r | |
160 | \r | |
161 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
162 | \r | |
163 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
164 | Register.\r | |
165 | @param OrData The value to OR with the PCI configuration register.\r | |
166 | \r | |
167 | @return The value written back to the PCI configuration register.\r | |
168 | \r | |
169 | **/\r | |
170 | UINT8\r | |
171 | EFIAPI\r | |
172 | PciExpressOr8 (\r | |
173 | IN UINTN Address,\r | |
174 | IN UINT8 OrData\r | |
175 | )\r | |
176 | {\r | |
177 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
178 | return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
179 | }\r | |
180 | \r | |
181 | /**\r | |
182 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
183 | value.\r | |
184 | \r | |
185 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
186 | bitwise AND between the read result and the value specified by AndData, and\r | |
187 | writes the result to the 8-bit PCI configuration register specified by\r | |
188 | Address. The value written to the PCI configuration register is returned.\r | |
189 | This function must guarantee that all PCI read and write operations are\r | |
190 | serialized.\r | |
191 | \r | |
192 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
193 | \r | |
194 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
195 | Register.\r | |
196 | @param AndData The value to AND with the PCI configuration register.\r | |
197 | \r | |
198 | @return The value written back to the PCI configuration register.\r | |
199 | \r | |
200 | **/\r | |
201 | UINT8\r | |
202 | EFIAPI\r | |
203 | PciExpressAnd8 (\r | |
204 | IN UINTN Address,\r | |
205 | IN UINT8 AndData\r | |
206 | )\r | |
207 | {\r | |
208 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
209 | return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
210 | }\r | |
211 | \r | |
212 | /**\r | |
213 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
214 | value, followed a bitwise OR with another 8-bit value.\r | |
215 | \r | |
216 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
217 | bitwise AND between the read result and the value specified by AndData,\r | |
218 | performs a bitwise OR between the result of the AND operation and\r | |
219 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
220 | configuration register specified by Address. The value written to the PCI\r | |
221 | configuration register is returned. This function must guarantee that all PCI\r | |
222 | read and write operations are serialized.\r | |
223 | \r | |
224 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
225 | \r | |
226 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
227 | Register.\r | |
228 | @param AndData The value to AND with the PCI configuration register.\r | |
229 | @param OrData The value to OR with the result of the AND operation.\r | |
230 | \r | |
231 | @return The value written back to the PCI configuration register.\r | |
232 | \r | |
233 | **/\r | |
234 | UINT8\r | |
235 | EFIAPI\r | |
236 | PciExpressAndThenOr8 (\r | |
237 | IN UINTN Address,\r | |
238 | IN UINT8 AndData,\r | |
239 | IN UINT8 OrData\r | |
240 | )\r | |
241 | {\r | |
242 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
243 | return MmioAndThenOr8 (\r | |
244 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
245 | AndData,\r | |
246 | OrData\r | |
247 | );\r | |
248 | }\r | |
249 | \r | |
250 | /**\r | |
251 | Reads a bit field of a PCI configuration register.\r | |
252 | \r | |
253 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
254 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
255 | returned.\r | |
256 | \r | |
257 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
258 | If StartBit is greater than 7, then ASSERT().\r | |
259 | If EndBit is greater than 7, then ASSERT().\r | |
260 | If EndBit is less than StartBit, then ASSERT().\r | |
261 | \r | |
262 | @param Address The PCI configuration register to read.\r | |
263 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
264 | Range 0..7.\r | |
265 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
266 | Range 0..7.\r | |
267 | \r | |
268 | @return The value of the bit field read from the PCI configuration register.\r | |
269 | \r | |
270 | **/\r | |
271 | UINT8\r | |
272 | EFIAPI\r | |
273 | PciExpressBitFieldRead8 (\r | |
274 | IN UINTN Address,\r | |
275 | IN UINTN StartBit,\r | |
276 | IN UINTN EndBit\r | |
277 | )\r | |
278 | {\r | |
279 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
280 | return MmioBitFieldRead8 (\r | |
281 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
282 | StartBit,\r | |
283 | EndBit\r | |
284 | );\r | |
285 | }\r | |
286 | \r | |
287 | /**\r | |
288 | Writes a bit field to a PCI configuration register.\r | |
289 | \r | |
290 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
291 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
292 | destination PCI configuration register are preserved. The new value of the\r | |
293 | 8-bit register is returned.\r | |
294 | \r | |
295 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
296 | If StartBit is greater than 7, then ASSERT().\r | |
297 | If EndBit is greater than 7, then ASSERT().\r | |
298 | If EndBit is less than StartBit, then ASSERT().\r | |
299 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
300 | \r | |
301 | @param Address The PCI configuration register to write.\r | |
302 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
303 | Range 0..7.\r | |
304 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
305 | Range 0..7.\r | |
306 | @param Value The new value of the bit field.\r | |
307 | \r | |
308 | @return The value written back to the PCI configuration register.\r | |
309 | \r | |
310 | **/\r | |
311 | UINT8\r | |
312 | EFIAPI\r | |
313 | PciExpressBitFieldWrite8 (\r | |
314 | IN UINTN Address,\r | |
315 | IN UINTN StartBit,\r | |
316 | IN UINTN EndBit,\r | |
317 | IN UINT8 Value\r | |
318 | )\r | |
319 | {\r | |
320 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
321 | return MmioBitFieldWrite8 (\r | |
322 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
323 | StartBit,\r | |
324 | EndBit,\r | |
325 | Value\r | |
326 | );\r | |
327 | }\r | |
328 | \r | |
329 | /**\r | |
330 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
331 | writes the result back to the bit field in the 8-bit port.\r | |
332 | \r | |
333 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
334 | bitwise OR between the read result and the value specified by\r | |
335 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
336 | specified by Address. The value written to the PCI configuration register is\r | |
337 | returned. This function must guarantee that all PCI read and write operations\r | |
338 | are serialized. Extra left bits in OrData are stripped.\r | |
339 | \r | |
340 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
341 | If StartBit is greater than 7, then ASSERT().\r | |
342 | If EndBit is greater than 7, then ASSERT().\r | |
343 | If EndBit is less than StartBit, then ASSERT().\r | |
344 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
345 | \r | |
346 | @param Address The PCI configuration register to write.\r | |
347 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
348 | Range 0..7.\r | |
349 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
350 | Range 0..7.\r | |
351 | @param OrData The value to OR with the PCI configuration register.\r | |
352 | \r | |
353 | @return The value written back to the PCI configuration register.\r | |
354 | \r | |
355 | **/\r | |
356 | UINT8\r | |
357 | EFIAPI\r | |
358 | PciExpressBitFieldOr8 (\r | |
359 | IN UINTN Address,\r | |
360 | IN UINTN StartBit,\r | |
361 | IN UINTN EndBit,\r | |
362 | IN UINT8 OrData\r | |
363 | )\r | |
364 | {\r | |
365 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
366 | return MmioBitFieldOr8 (\r | |
367 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
368 | StartBit,\r | |
369 | EndBit,\r | |
370 | OrData\r | |
371 | );\r | |
372 | }\r | |
373 | \r | |
374 | /**\r | |
375 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
376 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
377 | \r | |
378 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
379 | bitwise AND between the read result and the value specified by AndData, and\r | |
380 | writes the result to the 8-bit PCI configuration register specified by\r | |
381 | Address. The value written to the PCI configuration register is returned.\r | |
382 | This function must guarantee that all PCI read and write operations are\r | |
383 | serialized. Extra left bits in AndData are stripped.\r | |
384 | \r | |
385 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
386 | If StartBit is greater than 7, then ASSERT().\r | |
387 | If EndBit is greater than 7, then ASSERT().\r | |
388 | If EndBit is less than StartBit, then ASSERT().\r | |
389 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
390 | \r | |
391 | @param Address The PCI configuration register to write.\r | |
392 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
393 | Range 0..7.\r | |
394 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
395 | Range 0..7.\r | |
396 | @param AndData The value to AND with the PCI configuration register.\r | |
397 | \r | |
398 | @return The value written back to the PCI configuration register.\r | |
399 | \r | |
400 | **/\r | |
401 | UINT8\r | |
402 | EFIAPI\r | |
403 | PciExpressBitFieldAnd8 (\r | |
404 | IN UINTN Address,\r | |
405 | IN UINTN StartBit,\r | |
406 | IN UINTN EndBit,\r | |
407 | IN UINT8 AndData\r | |
408 | )\r | |
409 | {\r | |
410 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
411 | return MmioBitFieldAnd8 (\r | |
412 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
413 | StartBit,\r | |
414 | EndBit,\r | |
415 | AndData\r | |
416 | );\r | |
417 | }\r | |
418 | \r | |
419 | /**\r | |
420 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
421 | bitwise OR, and writes the result back to the bit field in the\r | |
422 | 8-bit port.\r | |
423 | \r | |
424 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
425 | bitwise AND followed by a bitwise OR between the read result and\r | |
426 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
427 | configuration register specified by Address. The value written to the PCI\r | |
428 | configuration register is returned. This function must guarantee that all PCI\r | |
429 | read and write operations are serialized. Extra left bits in both AndData and\r | |
430 | OrData are stripped.\r | |
431 | \r | |
432 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
433 | If StartBit is greater than 7, then ASSERT().\r | |
434 | If EndBit is greater than 7, then ASSERT().\r | |
435 | If EndBit is less than StartBit, then ASSERT().\r | |
436 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
437 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
438 | \r | |
439 | @param Address The PCI configuration register to write.\r | |
440 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
441 | Range 0..7.\r | |
442 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
443 | Range 0..7.\r | |
444 | @param AndData The value to AND with the PCI configuration register.\r | |
445 | @param OrData The value to OR with the result of the AND operation.\r | |
446 | \r | |
447 | @return The value written back to the PCI configuration register.\r | |
448 | \r | |
449 | **/\r | |
450 | UINT8\r | |
451 | EFIAPI\r | |
452 | PciExpressBitFieldAndThenOr8 (\r | |
453 | IN UINTN Address,\r | |
454 | IN UINTN StartBit,\r | |
455 | IN UINTN EndBit,\r | |
456 | IN UINT8 AndData,\r | |
457 | IN UINT8 OrData\r | |
458 | )\r | |
459 | {\r | |
460 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
461 | return MmioBitFieldAndThenOr8 (\r | |
462 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
463 | StartBit,\r | |
464 | EndBit,\r | |
465 | AndData,\r | |
466 | OrData\r | |
467 | );\r | |
468 | }\r | |
469 | \r | |
470 | /**\r | |
471 | Reads a 16-bit PCI configuration register.\r | |
472 | \r | |
473 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
474 | This function must guarantee that all PCI read and write operations are\r | |
475 | serialized.\r | |
476 | \r | |
477 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
478 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
479 | \r | |
480 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
481 | Register.\r | |
482 | \r | |
483 | @return The read value from the PCI configuration register.\r | |
484 | \r | |
485 | **/\r | |
486 | UINT16\r | |
487 | EFIAPI\r | |
488 | PciExpressRead16 (\r | |
489 | IN UINTN Address\r | |
490 | )\r | |
491 | {\r | |
492 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
493 | return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
494 | }\r | |
495 | \r | |
496 | /**\r | |
497 | Writes a 16-bit PCI configuration register.\r | |
498 | \r | |
499 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
500 | value specified by Value. Value is returned. This function must guarantee\r | |
501 | that all PCI read and write operations are serialized.\r | |
502 | \r | |
503 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
504 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
505 | \r | |
506 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
507 | Register.\r | |
508 | @param Value The value to write.\r | |
509 | \r | |
510 | @return The value written to the PCI configuration register.\r | |
511 | \r | |
512 | **/\r | |
513 | UINT16\r | |
514 | EFIAPI\r | |
515 | PciExpressWrite16 (\r | |
516 | IN UINTN Address,\r | |
517 | IN UINT16 Value\r | |
518 | )\r | |
519 | {\r | |
520 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
521 | return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
522 | }\r | |
523 | \r | |
524 | /**\r | |
525 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
526 | a 16-bit value.\r | |
527 | \r | |
528 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
529 | bitwise OR between the read result and the value specified by\r | |
530 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
531 | specified by Address. The value written to the PCI configuration register is\r | |
532 | returned. This function must guarantee that all PCI read and write operations\r | |
533 | are serialized.\r | |
534 | \r | |
535 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
536 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
537 | \r | |
538 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
539 | Register.\r | |
540 | @param OrData The value to OR with the PCI configuration register.\r | |
541 | \r | |
542 | @return The value written back to the PCI configuration register.\r | |
543 | \r | |
544 | **/\r | |
545 | UINT16\r | |
546 | EFIAPI\r | |
547 | PciExpressOr16 (\r | |
548 | IN UINTN Address,\r | |
549 | IN UINT16 OrData\r | |
550 | )\r | |
551 | {\r | |
552 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
553 | return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
554 | }\r | |
555 | \r | |
556 | /**\r | |
557 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
558 | value.\r | |
559 | \r | |
560 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
561 | bitwise AND between the read result and the value specified by AndData, and\r | |
562 | writes the result to the 16-bit PCI configuration register specified by\r | |
563 | Address. The value written to the PCI configuration register is returned.\r | |
564 | This function must guarantee that all PCI read and write operations are\r | |
565 | serialized.\r | |
566 | \r | |
567 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
568 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
569 | \r | |
570 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
571 | Register.\r | |
572 | @param AndData The value to AND with the PCI configuration register.\r | |
573 | \r | |
574 | @return The value written back to the PCI configuration register.\r | |
575 | \r | |
576 | **/\r | |
577 | UINT16\r | |
578 | EFIAPI\r | |
579 | PciExpressAnd16 (\r | |
580 | IN UINTN Address,\r | |
581 | IN UINT16 AndData\r | |
582 | )\r | |
583 | {\r | |
584 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
585 | return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
586 | }\r | |
587 | \r | |
588 | /**\r | |
589 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
590 | value, followed a bitwise OR with another 16-bit value.\r | |
591 | \r | |
592 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
593 | bitwise AND between the read result and the value specified by AndData,\r | |
594 | performs a bitwise OR between the result of the AND operation and\r | |
595 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
596 | configuration register specified by Address. The value written to the PCI\r | |
597 | configuration register is returned. This function must guarantee that all PCI\r | |
598 | read and write operations are serialized.\r | |
599 | \r | |
600 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
601 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
602 | \r | |
603 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
604 | Register.\r | |
605 | @param AndData The value to AND with the PCI configuration register.\r | |
606 | @param OrData The value to OR with the result of the AND operation.\r | |
607 | \r | |
608 | @return The value written back to the PCI configuration register.\r | |
609 | \r | |
610 | **/\r | |
611 | UINT16\r | |
612 | EFIAPI\r | |
613 | PciExpressAndThenOr16 (\r | |
614 | IN UINTN Address,\r | |
615 | IN UINT16 AndData,\r | |
616 | IN UINT16 OrData\r | |
617 | )\r | |
618 | {\r | |
619 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
620 | return MmioAndThenOr16 (\r | |
621 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
622 | AndData,\r | |
623 | OrData\r | |
624 | );\r | |
625 | }\r | |
626 | \r | |
627 | /**\r | |
628 | Reads a bit field of a PCI configuration register.\r | |
629 | \r | |
630 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
631 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
632 | returned.\r | |
633 | \r | |
634 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
635 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
636 | If StartBit is greater than 15, then ASSERT().\r | |
637 | If EndBit is greater than 15, then ASSERT().\r | |
638 | If EndBit is less than StartBit, then ASSERT().\r | |
639 | \r | |
640 | @param Address The PCI configuration register to read.\r | |
641 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
642 | Range 0..15.\r | |
643 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
644 | Range 0..15.\r | |
645 | \r | |
646 | @return The value of the bit field read from the PCI configuration register.\r | |
647 | \r | |
648 | **/\r | |
649 | UINT16\r | |
650 | EFIAPI\r | |
651 | PciExpressBitFieldRead16 (\r | |
652 | IN UINTN Address,\r | |
653 | IN UINTN StartBit,\r | |
654 | IN UINTN EndBit\r | |
655 | )\r | |
656 | {\r | |
657 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
658 | return MmioBitFieldRead16 (\r | |
659 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
660 | StartBit,\r | |
661 | EndBit\r | |
662 | );\r | |
663 | }\r | |
664 | \r | |
665 | /**\r | |
666 | Writes a bit field to a PCI configuration register.\r | |
667 | \r | |
668 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
669 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
670 | destination PCI configuration register are preserved. The new value of the\r | |
671 | 16-bit register is returned.\r | |
672 | \r | |
673 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
674 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
675 | If StartBit is greater than 15, then ASSERT().\r | |
676 | If EndBit is greater than 15, then ASSERT().\r | |
677 | If EndBit is less than StartBit, then ASSERT().\r | |
678 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
679 | \r | |
680 | @param Address The PCI configuration register to write.\r | |
681 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
682 | Range 0..15.\r | |
683 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
684 | Range 0..15.\r | |
685 | @param Value The new value of the bit field.\r | |
686 | \r | |
687 | @return The value written back to the PCI configuration register.\r | |
688 | \r | |
689 | **/\r | |
690 | UINT16\r | |
691 | EFIAPI\r | |
692 | PciExpressBitFieldWrite16 (\r | |
693 | IN UINTN Address,\r | |
694 | IN UINTN StartBit,\r | |
695 | IN UINTN EndBit,\r | |
696 | IN UINT16 Value\r | |
697 | )\r | |
698 | {\r | |
699 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
700 | return MmioBitFieldWrite16 (\r | |
701 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
702 | StartBit,\r | |
703 | EndBit,\r | |
704 | Value\r | |
705 | );\r | |
706 | }\r | |
707 | \r | |
708 | /**\r | |
709 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
710 | writes the result back to the bit field in the 16-bit port.\r | |
711 | \r | |
712 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
713 | bitwise OR between the read result and the value specified by\r | |
714 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
715 | specified by Address. The value written to the PCI configuration register is\r | |
716 | returned. This function must guarantee that all PCI read and write operations\r | |
717 | are serialized. Extra left bits in OrData are stripped.\r | |
718 | \r | |
719 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
720 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
721 | If StartBit is greater than 15, then ASSERT().\r | |
722 | If EndBit is greater than 15, then ASSERT().\r | |
723 | If EndBit is less than StartBit, then ASSERT().\r | |
724 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
725 | \r | |
726 | @param Address The PCI configuration register to write.\r | |
727 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
728 | Range 0..15.\r | |
729 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
730 | Range 0..15.\r | |
731 | @param OrData The value to OR with the PCI configuration register.\r | |
732 | \r | |
733 | @return The value written back to the PCI configuration register.\r | |
734 | \r | |
735 | **/\r | |
736 | UINT16\r | |
737 | EFIAPI\r | |
738 | PciExpressBitFieldOr16 (\r | |
739 | IN UINTN Address,\r | |
740 | IN UINTN StartBit,\r | |
741 | IN UINTN EndBit,\r | |
742 | IN UINT16 OrData\r | |
743 | )\r | |
744 | {\r | |
745 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
746 | return MmioBitFieldOr16 (\r | |
747 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
748 | StartBit,\r | |
749 | EndBit,\r | |
750 | OrData\r | |
751 | );\r | |
752 | }\r | |
753 | \r | |
754 | /**\r | |
755 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
756 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
757 | \r | |
758 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
759 | bitwise AND between the read result and the value specified by AndData, and\r | |
760 | writes the result to the 16-bit PCI configuration register specified by\r | |
761 | Address. The value written to the PCI configuration register is returned.\r | |
762 | This function must guarantee that all PCI read and write operations are\r | |
763 | serialized. Extra left bits in AndData are stripped.\r | |
764 | \r | |
765 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
766 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
767 | If StartBit is greater than 15, then ASSERT().\r | |
768 | If EndBit is greater than 15, then ASSERT().\r | |
769 | If EndBit is less than StartBit, then ASSERT().\r | |
770 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
771 | \r | |
772 | @param Address The PCI configuration register to write.\r | |
773 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
774 | Range 0..15.\r | |
775 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
776 | Range 0..15.\r | |
777 | @param AndData The value to AND with the PCI configuration register.\r | |
778 | \r | |
779 | @return The value written back to the PCI configuration register.\r | |
780 | \r | |
781 | **/\r | |
782 | UINT16\r | |
783 | EFIAPI\r | |
784 | PciExpressBitFieldAnd16 (\r | |
785 | IN UINTN Address,\r | |
786 | IN UINTN StartBit,\r | |
787 | IN UINTN EndBit,\r | |
788 | IN UINT16 AndData\r | |
789 | )\r | |
790 | {\r | |
791 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
792 | return MmioBitFieldAnd16 (\r | |
793 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
794 | StartBit,\r | |
795 | EndBit,\r | |
796 | AndData\r | |
797 | );\r | |
798 | }\r | |
799 | \r | |
800 | /**\r | |
801 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
802 | bitwise OR, and writes the result back to the bit field in the\r | |
803 | 16-bit port.\r | |
804 | \r | |
805 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
806 | bitwise AND followed by a bitwise OR between the read result and\r | |
807 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
808 | configuration register specified by Address. The value written to the PCI\r | |
809 | configuration register is returned. This function must guarantee that all PCI\r | |
810 | read and write operations are serialized. Extra left bits in both AndData and\r | |
811 | OrData are stripped.\r | |
812 | \r | |
813 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
814 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
815 | If StartBit is greater than 15, then ASSERT().\r | |
816 | If EndBit is greater than 15, then ASSERT().\r | |
817 | If EndBit is less than StartBit, then ASSERT().\r | |
818 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
819 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
820 | \r | |
821 | @param Address The PCI configuration register to write.\r | |
822 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
823 | Range 0..15.\r | |
824 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
825 | Range 0..15.\r | |
826 | @param AndData The value to AND with the PCI configuration register.\r | |
827 | @param OrData The value to OR with the result of the AND operation.\r | |
828 | \r | |
829 | @return The value written back to the PCI configuration register.\r | |
830 | \r | |
831 | **/\r | |
832 | UINT16\r | |
833 | EFIAPI\r | |
834 | PciExpressBitFieldAndThenOr16 (\r | |
835 | IN UINTN Address,\r | |
836 | IN UINTN StartBit,\r | |
837 | IN UINTN EndBit,\r | |
838 | IN UINT16 AndData,\r | |
839 | IN UINT16 OrData\r | |
840 | )\r | |
841 | {\r | |
842 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
843 | return MmioBitFieldAndThenOr16 (\r | |
844 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
845 | StartBit,\r | |
846 | EndBit,\r | |
847 | AndData,\r | |
848 | OrData\r | |
849 | );\r | |
850 | }\r | |
851 | \r | |
852 | /**\r | |
853 | Reads a 32-bit PCI configuration register.\r | |
854 | \r | |
855 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
856 | This function must guarantee that all PCI read and write operations are\r | |
857 | serialized.\r | |
858 | \r | |
859 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
860 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
861 | \r | |
862 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
863 | Register.\r | |
864 | \r | |
865 | @return The read value from the PCI configuration register.\r | |
866 | \r | |
867 | **/\r | |
868 | UINT32\r | |
869 | EFIAPI\r | |
870 | PciExpressRead32 (\r | |
871 | IN UINTN Address\r | |
872 | )\r | |
873 | {\r | |
874 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
875 | return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
876 | }\r | |
877 | \r | |
878 | /**\r | |
879 | Writes a 32-bit PCI configuration register.\r | |
880 | \r | |
881 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
882 | value specified by Value. Value is returned. This function must guarantee\r | |
883 | that all PCI read and write operations are serialized.\r | |
884 | \r | |
885 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
886 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
887 | \r | |
888 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
889 | Register.\r | |
890 | @param Value The value to write.\r | |
891 | \r | |
892 | @return The value written to the PCI configuration register.\r | |
893 | \r | |
894 | **/\r | |
895 | UINT32\r | |
896 | EFIAPI\r | |
897 | PciExpressWrite32 (\r | |
898 | IN UINTN Address,\r | |
899 | IN UINT32 Value\r | |
900 | )\r | |
901 | {\r | |
902 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
903 | return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
904 | }\r | |
905 | \r | |
906 | /**\r | |
907 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
908 | a 32-bit value.\r | |
909 | \r | |
910 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
911 | bitwise OR between the read result and the value specified by\r | |
912 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
913 | specified by Address. The value written to the PCI configuration register is\r | |
914 | returned. This function must guarantee that all PCI read and write operations\r | |
915 | are serialized.\r | |
916 | \r | |
917 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
918 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
919 | \r | |
920 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
921 | Register.\r | |
922 | @param OrData The value to OR with the PCI configuration register.\r | |
923 | \r | |
924 | @return The value written back to the PCI configuration register.\r | |
925 | \r | |
926 | **/\r | |
927 | UINT32\r | |
928 | EFIAPI\r | |
929 | PciExpressOr32 (\r | |
930 | IN UINTN Address,\r | |
931 | IN UINT32 OrData\r | |
932 | )\r | |
933 | {\r | |
934 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
935 | return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
936 | }\r | |
937 | \r | |
938 | /**\r | |
939 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
940 | value.\r | |
941 | \r | |
942 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
943 | bitwise AND between the read result and the value specified by AndData, and\r | |
944 | writes the result to the 32-bit PCI configuration register specified by\r | |
945 | Address. The value written to the PCI configuration register is returned.\r | |
946 | This function must guarantee that all PCI read and write operations are\r | |
947 | serialized.\r | |
948 | \r | |
949 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
950 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
951 | \r | |
952 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
953 | Register.\r | |
954 | @param AndData The value to AND with the PCI configuration register.\r | |
955 | \r | |
956 | @return The value written back to the PCI configuration register.\r | |
957 | \r | |
958 | **/\r | |
959 | UINT32\r | |
960 | EFIAPI\r | |
961 | PciExpressAnd32 (\r | |
962 | IN UINTN Address,\r | |
963 | IN UINT32 AndData\r | |
964 | )\r | |
965 | {\r | |
966 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
967 | return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
968 | }\r | |
969 | \r | |
970 | /**\r | |
971 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
972 | value, followed a bitwise OR with another 32-bit value.\r | |
973 | \r | |
974 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
975 | bitwise AND between the read result and the value specified by AndData,\r | |
976 | performs a bitwise OR between the result of the AND operation and\r | |
977 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
978 | configuration register specified by Address. The value written to the PCI\r | |
979 | configuration register is returned. This function must guarantee that all PCI\r | |
980 | read and write operations are serialized.\r | |
981 | \r | |
982 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
983 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
984 | \r | |
985 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
986 | Register.\r | |
987 | @param AndData The value to AND with the PCI configuration register.\r | |
988 | @param OrData The value to OR with the result of the AND operation.\r | |
989 | \r | |
990 | @return The value written back to the PCI configuration register.\r | |
991 | \r | |
992 | **/\r | |
993 | UINT32\r | |
994 | EFIAPI\r | |
995 | PciExpressAndThenOr32 (\r | |
996 | IN UINTN Address,\r | |
997 | IN UINT32 AndData,\r | |
998 | IN UINT32 OrData\r | |
999 | )\r | |
1000 | {\r | |
1001 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1002 | return MmioAndThenOr32 (\r | |
1003 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1004 | AndData,\r | |
1005 | OrData\r | |
1006 | );\r | |
1007 | }\r | |
1008 | \r | |
1009 | /**\r | |
1010 | Reads a bit field of a PCI configuration register.\r | |
1011 | \r | |
1012 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1013 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1014 | returned.\r | |
1015 | \r | |
1016 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1017 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1018 | If StartBit is greater than 31, then ASSERT().\r | |
1019 | If EndBit is greater than 31, then ASSERT().\r | |
1020 | If EndBit is less than StartBit, then ASSERT().\r | |
1021 | \r | |
1022 | @param Address The PCI configuration register to read.\r | |
1023 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1024 | Range 0..31.\r | |
1025 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1026 | Range 0..31.\r | |
1027 | \r | |
1028 | @return The value of the bit field read from the PCI configuration register.\r | |
1029 | \r | |
1030 | **/\r | |
1031 | UINT32\r | |
1032 | EFIAPI\r | |
1033 | PciExpressBitFieldRead32 (\r | |
1034 | IN UINTN Address,\r | |
1035 | IN UINTN StartBit,\r | |
1036 | IN UINTN EndBit\r | |
1037 | )\r | |
1038 | {\r | |
1039 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1040 | return MmioBitFieldRead32 (\r | |
1041 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1042 | StartBit,\r | |
1043 | EndBit\r | |
1044 | );\r | |
1045 | }\r | |
1046 | \r | |
1047 | /**\r | |
1048 | Writes a bit field to a PCI configuration register.\r | |
1049 | \r | |
1050 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1051 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1052 | destination PCI configuration register are preserved. The new value of the\r | |
1053 | 32-bit register is returned.\r | |
1054 | \r | |
1055 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1056 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1057 | If StartBit is greater than 31, then ASSERT().\r | |
1058 | If EndBit is greater than 31, then ASSERT().\r | |
1059 | If EndBit is less than StartBit, then ASSERT().\r | |
1060 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1061 | \r | |
1062 | @param Address The PCI configuration register to write.\r | |
1063 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1064 | Range 0..31.\r | |
1065 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1066 | Range 0..31.\r | |
1067 | @param Value The new value of the bit field.\r | |
1068 | \r | |
1069 | @return The value written back to the PCI configuration register.\r | |
1070 | \r | |
1071 | **/\r | |
1072 | UINT32\r | |
1073 | EFIAPI\r | |
1074 | PciExpressBitFieldWrite32 (\r | |
1075 | IN UINTN Address,\r | |
1076 | IN UINTN StartBit,\r | |
1077 | IN UINTN EndBit,\r | |
1078 | IN UINT32 Value\r | |
1079 | )\r | |
1080 | {\r | |
1081 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1082 | return MmioBitFieldWrite32 (\r | |
1083 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1084 | StartBit,\r | |
1085 | EndBit,\r | |
1086 | Value\r | |
1087 | );\r | |
1088 | }\r | |
1089 | \r | |
1090 | /**\r | |
1091 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1092 | writes the result back to the bit field in the 32-bit port.\r | |
1093 | \r | |
1094 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1095 | bitwise OR between the read result and the value specified by\r | |
1096 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1097 | specified by Address. The value written to the PCI configuration register is\r | |
1098 | returned. This function must guarantee that all PCI read and write operations\r | |
1099 | are serialized. Extra left bits in OrData are stripped.\r | |
1100 | \r | |
1101 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1102 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1103 | If StartBit is greater than 31, then ASSERT().\r | |
1104 | If EndBit is greater than 31, then ASSERT().\r | |
1105 | If EndBit is less than StartBit, then ASSERT().\r | |
1106 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1107 | \r | |
1108 | @param Address The PCI configuration register to write.\r | |
1109 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1110 | Range 0..31.\r | |
1111 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1112 | Range 0..31.\r | |
1113 | @param OrData The value to OR with the PCI configuration register.\r | |
1114 | \r | |
1115 | @return The value written back to the PCI configuration register.\r | |
1116 | \r | |
1117 | **/\r | |
1118 | UINT32\r | |
1119 | EFIAPI\r | |
1120 | PciExpressBitFieldOr32 (\r | |
1121 | IN UINTN Address,\r | |
1122 | IN UINTN StartBit,\r | |
1123 | IN UINTN EndBit,\r | |
1124 | IN UINT32 OrData\r | |
1125 | )\r | |
1126 | {\r | |
1127 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1128 | return MmioBitFieldOr32 (\r | |
1129 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1130 | StartBit,\r | |
1131 | EndBit,\r | |
1132 | OrData\r | |
1133 | );\r | |
1134 | }\r | |
1135 | \r | |
1136 | /**\r | |
1137 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1138 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1139 | \r | |
1140 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1141 | bitwise AND between the read result and the value specified by AndData, and\r | |
1142 | writes the result to the 32-bit PCI configuration register specified by\r | |
1143 | Address. The value written to the PCI configuration register is returned.\r | |
1144 | This function must guarantee that all PCI read and write operations are\r | |
1145 | serialized. Extra left bits in AndData are stripped.\r | |
1146 | \r | |
1147 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1148 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1149 | If StartBit is greater than 31, then ASSERT().\r | |
1150 | If EndBit is greater than 31, then ASSERT().\r | |
1151 | If EndBit is less than StartBit, then ASSERT().\r | |
1152 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1153 | \r | |
1154 | @param Address The PCI configuration register to write.\r | |
1155 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1156 | Range 0..31.\r | |
1157 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1158 | Range 0..31.\r | |
1159 | @param AndData The value to AND with the PCI configuration register.\r | |
1160 | \r | |
1161 | @return The value written back to the PCI configuration register.\r | |
1162 | \r | |
1163 | **/\r | |
1164 | UINT32\r | |
1165 | EFIAPI\r | |
1166 | PciExpressBitFieldAnd32 (\r | |
1167 | IN UINTN Address,\r | |
1168 | IN UINTN StartBit,\r | |
1169 | IN UINTN EndBit,\r | |
1170 | IN UINT32 AndData\r | |
1171 | )\r | |
1172 | {\r | |
1173 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1174 | return MmioBitFieldAnd32 (\r | |
1175 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1176 | StartBit,\r | |
1177 | EndBit,\r | |
1178 | AndData\r | |
1179 | );\r | |
1180 | }\r | |
1181 | \r | |
1182 | /**\r | |
1183 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1184 | bitwise OR, and writes the result back to the bit field in the\r | |
1185 | 32-bit port.\r | |
1186 | \r | |
1187 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1188 | bitwise AND followed by a bitwise OR between the read result and\r | |
1189 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1190 | configuration register specified by Address. The value written to the PCI\r | |
1191 | configuration register is returned. This function must guarantee that all PCI\r | |
1192 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1193 | OrData are stripped.\r | |
1194 | \r | |
1195 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1196 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1197 | If StartBit is greater than 31, then ASSERT().\r | |
1198 | If EndBit is greater than 31, then ASSERT().\r | |
1199 | If EndBit is less than StartBit, then ASSERT().\r | |
1200 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1201 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1202 | \r | |
1203 | @param Address The PCI configuration register to write.\r | |
1204 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1205 | Range 0..31.\r | |
1206 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1207 | Range 0..31.\r | |
1208 | @param AndData The value to AND with the PCI configuration register.\r | |
1209 | @param OrData The value to OR with the result of the AND operation.\r | |
1210 | \r | |
1211 | @return The value written back to the PCI configuration register.\r | |
1212 | \r | |
1213 | **/\r | |
1214 | UINT32\r | |
1215 | EFIAPI\r | |
1216 | PciExpressBitFieldAndThenOr32 (\r | |
1217 | IN UINTN Address,\r | |
1218 | IN UINTN StartBit,\r | |
1219 | IN UINTN EndBit,\r | |
1220 | IN UINT32 AndData,\r | |
1221 | IN UINT32 OrData\r | |
1222 | )\r | |
1223 | {\r | |
1224 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1225 | return MmioBitFieldAndThenOr32 (\r | |
1226 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1227 | StartBit,\r | |
1228 | EndBit,\r | |
1229 | AndData,\r | |
1230 | OrData\r | |
1231 | );\r | |
1232 | }\r | |
1233 | \r | |
1234 | /**\r | |
1235 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1236 | \r | |
1237 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1238 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1239 | configuration registers from a single PCI function to be read. Size is\r | |
1240 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1241 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1242 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1243 | end of the range.\r | |
1244 | \r | |
1245 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1246 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1247 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1248 | \r | |
1249 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
1250 | Function and Register.\r | |
1251 | @param Size The size in bytes of the transfer.\r | |
1252 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1253 | \r | |
1254 | @return Size read data from StartAddress.\r | |
1255 | \r | |
1256 | **/\r | |
1257 | UINTN\r | |
1258 | EFIAPI\r | |
1259 | PciExpressReadBuffer (\r | |
1260 | IN UINTN StartAddress,\r | |
1261 | IN UINTN Size,\r | |
1262 | OUT VOID *Buffer\r | |
1263 | )\r | |
1264 | {\r | |
1265 | UINTN ReturnValue;\r | |
1266 | \r | |
1267 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1268 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1269 | \r | |
1270 | if (Size == 0) {\r | |
1271 | return Size;\r | |
1272 | }\r | |
1273 | \r | |
1274 | ASSERT (Buffer != NULL);\r | |
1275 | \r | |
1276 | //\r | |
1277 | // Save Size for return\r | |
1278 | //\r | |
1279 | ReturnValue = Size;\r | |
1280 | \r | |
1281 | if ((StartAddress & 1) != 0) {\r | |
1282 | //\r | |
1283 | // Read a byte if StartAddress is byte aligned\r | |
1284 | //\r | |
1285 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1286 | StartAddress += sizeof (UINT8);\r | |
1287 | Size -= sizeof (UINT8);\r | |
1288 | Buffer = (UINT8*)Buffer + 1;\r | |
1289 | }\r | |
1290 | \r | |
1291 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1292 | //\r | |
1293 | // Read a word if StartAddress is word aligned\r | |
1294 | //\r | |
1295 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r | |
1296 | \r | |
1297 | StartAddress += sizeof (UINT16);\r | |
1298 | Size -= sizeof (UINT16);\r | |
1299 | Buffer = (UINT16*)Buffer + 1;\r | |
1300 | }\r | |
1301 | \r | |
1302 | while (Size >= sizeof (UINT32)) {\r | |
1303 | //\r | |
1304 | // Read as many double words as possible\r | |
1305 | //\r | |
1306 | WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r | |
1307 | \r | |
1308 | StartAddress += sizeof (UINT32);\r | |
1309 | Size -= sizeof (UINT32);\r | |
1310 | Buffer = (UINT32*)Buffer + 1;\r | |
1311 | }\r | |
1312 | \r | |
1313 | if (Size >= sizeof (UINT16)) {\r | |
1314 | //\r | |
1315 | // Read the last remaining word if exist\r | |
1316 | //\r | |
1317 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r | |
1318 | StartAddress += sizeof (UINT16);\r | |
1319 | Size -= sizeof (UINT16);\r | |
1320 | Buffer = (UINT16*)Buffer + 1;\r | |
1321 | }\r | |
1322 | \r | |
1323 | if (Size >= sizeof (UINT8)) {\r | |
1324 | //\r | |
1325 | // Read the last remaining byte if exist\r | |
1326 | //\r | |
1327 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1328 | }\r | |
1329 | \r | |
1330 | return ReturnValue;\r | |
1331 | }\r | |
1332 | \r | |
1333 | /**\r | |
1334 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1335 | configuration space.\r | |
1336 | \r | |
1337 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1338 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1339 | configuration registers from a single PCI function to be written. Size is\r | |
1340 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1341 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1342 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1343 | and the end of the range.\r | |
1344 | \r | |
1345 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1346 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1347 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1348 | \r | |
1349 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
1350 | Function and Register.\r | |
1351 | @param Size The size in bytes of the transfer.\r | |
1352 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1353 | \r | |
1354 | @return Size written to StartAddress.\r | |
1355 | \r | |
1356 | **/\r | |
1357 | UINTN\r | |
1358 | EFIAPI\r | |
1359 | PciExpressWriteBuffer (\r | |
1360 | IN UINTN StartAddress,\r | |
1361 | IN UINTN Size,\r | |
1362 | IN VOID *Buffer\r | |
1363 | )\r | |
1364 | {\r | |
1365 | UINTN ReturnValue;\r | |
1366 | \r | |
1367 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1368 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1369 | \r | |
1370 | if (Size == 0) {\r | |
1371 | return 0;\r | |
1372 | }\r | |
1373 | \r | |
1374 | ASSERT (Buffer != NULL);\r | |
1375 | \r | |
1376 | //\r | |
1377 | // Save Size for return\r | |
1378 | //\r | |
1379 | ReturnValue = Size;\r | |
1380 | \r | |
1381 | if ((StartAddress & 1) != 0) {\r | |
1382 | //\r | |
1383 | // Write a byte if StartAddress is byte aligned\r | |
1384 | //\r | |
1385 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1386 | StartAddress += sizeof (UINT8);\r | |
1387 | Size -= sizeof (UINT8);\r | |
1388 | Buffer = (UINT8*)Buffer + 1;\r | |
1389 | }\r | |
1390 | \r | |
1391 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1392 | //\r | |
1393 | // Write a word if StartAddress is word aligned\r | |
1394 | //\r | |
1395 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r | |
1396 | StartAddress += sizeof (UINT16);\r | |
1397 | Size -= sizeof (UINT16);\r | |
1398 | Buffer = (UINT16*)Buffer + 1;\r | |
1399 | }\r | |
1400 | \r | |
1401 | while (Size >= sizeof (UINT32)) {\r | |
1402 | //\r | |
1403 | // Write as many double words as possible\r | |
1404 | //\r | |
1405 | PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r | |
1406 | StartAddress += sizeof (UINT32);\r | |
1407 | Size -= sizeof (UINT32);\r | |
1408 | Buffer = (UINT32*)Buffer + 1;\r | |
1409 | }\r | |
1410 | \r | |
1411 | if (Size >= sizeof (UINT16)) {\r | |
1412 | //\r | |
1413 | // Write the last remaining word if exist\r | |
1414 | //\r | |
1415 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r | |
1416 | StartAddress += sizeof (UINT16);\r | |
1417 | Size -= sizeof (UINT16);\r | |
1418 | Buffer = (UINT16*)Buffer + 1;\r | |
1419 | }\r | |
1420 | \r | |
1421 | if (Size >= sizeof (UINT8)) {\r | |
1422 | //\r | |
1423 | // Write the last remaining byte if exist\r | |
1424 | //\r | |
1425 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1426 | }\r | |
1427 | \r | |
1428 | return ReturnValue;\r | |
1429 | }\r |