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ad3359eb LE |
1 | /** @file\r |
2 | Functions in this library instance make use of MMIO functions in IoLib to\r | |
3 | access memory mapped PCI configuration space.\r | |
4 | \r | |
5 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r | |
6 | Library.\r | |
7 | \r | |
8 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r | |
9792fb0e | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
ad3359eb LE |
10 | \r |
11 | **/\r | |
12 | \r | |
13 | \r | |
14 | #include <Base.h>\r | |
15 | \r | |
16 | #include <Library/BaseLib.h>\r | |
17 | #include <Library/PciExpressLib.h>\r | |
18 | #include <Library/IoLib.h>\r | |
19 | #include <Library/DebugLib.h>\r | |
20 | #include <Library/PcdLib.h>\r | |
21 | \r | |
22 | \r | |
23 | /**\r | |
24 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
25 | only in the low 28 bits.\r | |
26 | \r | |
27 | @param A The address to validate.\r | |
28 | \r | |
29 | **/\r | |
30 | #define ASSERT_INVALID_PCI_ADDRESS(A) \\r | |
31 | ASSERT (((A) & ~0xfffffff) == 0)\r | |
32 | \r | |
33 | /**\r | |
d1c561f9 | 34 | Registers a PCI device so PCI configuration registers may be accessed after\r |
ad3359eb | 35 | SetVirtualAddressMap().\r |
d1c561f9 OM |
36 | \r |
37 | Registers the PCI device specified by Address so all the PCI configuration\r | |
38 | registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r | |
ad3359eb | 39 | is called.\r |
d1c561f9 | 40 | \r |
ad3359eb LE |
41 | If Address > 0x0FFFFFFF, then ASSERT().\r |
42 | \r | |
43 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
44 | Register.\r | |
d1c561f9 | 45 | \r |
ad3359eb | 46 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
d1c561f9 | 47 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
ad3359eb LE |
48 | after ExitBootServices().\r |
49 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
50 | at runtime could not be mapped.\r | |
51 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
52 | complete the registration.\r | |
53 | \r | |
54 | **/\r | |
55 | RETURN_STATUS\r | |
56 | EFIAPI\r | |
57 | PciExpressRegisterForRuntimeAccess (\r | |
58 | IN UINTN Address\r | |
59 | )\r | |
60 | {\r | |
61 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
62 | return RETURN_UNSUPPORTED;\r | |
63 | }\r | |
64 | \r | |
65 | STATIC UINT64 mPciExpressBaseAddress;\r | |
66 | \r | |
67 | RETURN_STATUS\r | |
68 | EFIAPI\r | |
69 | PciExpressLibInitialize (\r | |
70 | VOID\r | |
71 | )\r | |
72 | {\r | |
73 | mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);\r | |
74 | return RETURN_SUCCESS;\r | |
75 | }\r | |
76 | \r | |
77 | \r | |
78 | /**\r | |
79 | Gets the base address of PCI Express.\r | |
d1c561f9 | 80 | \r |
ad3359eb LE |
81 | @return The base address of PCI Express.\r |
82 | \r | |
83 | **/\r | |
84 | VOID*\r | |
85 | GetPciExpressBaseAddress (\r | |
86 | VOID\r | |
87 | )\r | |
88 | {\r | |
89 | return (VOID*)(UINTN) mPciExpressBaseAddress;\r | |
90 | }\r | |
91 | \r | |
92 | /**\r | |
93 | Reads an 8-bit PCI configuration register.\r | |
94 | \r | |
95 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
96 | This function must guarantee that all PCI read and write operations are\r | |
97 | serialized.\r | |
98 | \r | |
99 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
100 | \r | |
101 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
102 | Register.\r | |
103 | \r | |
104 | @return The read value from the PCI configuration register.\r | |
105 | \r | |
106 | **/\r | |
107 | UINT8\r | |
108 | EFIAPI\r | |
109 | PciExpressRead8 (\r | |
110 | IN UINTN Address\r | |
111 | )\r | |
112 | {\r | |
113 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
114 | return MmioRead8 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
115 | }\r | |
116 | \r | |
117 | /**\r | |
118 | Writes an 8-bit PCI configuration register.\r | |
119 | \r | |
120 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
121 | value specified by Value. Value is returned. This function must guarantee\r | |
122 | that all PCI read and write operations are serialized.\r | |
123 | \r | |
124 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
125 | \r | |
126 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
127 | Register.\r | |
128 | @param Value The value to write.\r | |
129 | \r | |
130 | @return The value written to the PCI configuration register.\r | |
131 | \r | |
132 | **/\r | |
133 | UINT8\r | |
134 | EFIAPI\r | |
135 | PciExpressWrite8 (\r | |
136 | IN UINTN Address,\r | |
137 | IN UINT8 Value\r | |
138 | )\r | |
139 | {\r | |
140 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
141 | return MmioWrite8 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
142 | }\r | |
143 | \r | |
144 | /**\r | |
145 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
146 | an 8-bit value.\r | |
147 | \r | |
148 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
149 | bitwise OR between the read result and the value specified by\r | |
150 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
151 | specified by Address. The value written to the PCI configuration register is\r | |
152 | returned. This function must guarantee that all PCI read and write operations\r | |
153 | are serialized.\r | |
154 | \r | |
155 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
156 | \r | |
157 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
158 | Register.\r | |
159 | @param OrData The value to OR with the PCI configuration register.\r | |
160 | \r | |
161 | @return The value written back to the PCI configuration register.\r | |
162 | \r | |
163 | **/\r | |
164 | UINT8\r | |
165 | EFIAPI\r | |
166 | PciExpressOr8 (\r | |
167 | IN UINTN Address,\r | |
168 | IN UINT8 OrData\r | |
169 | )\r | |
170 | {\r | |
171 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
172 | return MmioOr8 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
173 | }\r | |
174 | \r | |
175 | /**\r | |
176 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
177 | value.\r | |
178 | \r | |
179 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
180 | bitwise AND between the read result and the value specified by AndData, and\r | |
181 | writes the result to the 8-bit PCI configuration register specified by\r | |
182 | Address. The value written to the PCI configuration register is returned.\r | |
183 | This function must guarantee that all PCI read and write operations are\r | |
184 | serialized.\r | |
185 | \r | |
186 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
187 | \r | |
188 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
189 | Register.\r | |
190 | @param AndData The value to AND with the PCI configuration register.\r | |
191 | \r | |
192 | @return The value written back to the PCI configuration register.\r | |
193 | \r | |
194 | **/\r | |
195 | UINT8\r | |
196 | EFIAPI\r | |
197 | PciExpressAnd8 (\r | |
198 | IN UINTN Address,\r | |
199 | IN UINT8 AndData\r | |
200 | )\r | |
201 | {\r | |
202 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
203 | return MmioAnd8 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
204 | }\r | |
205 | \r | |
206 | /**\r | |
207 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
208 | value, followed a bitwise OR with another 8-bit value.\r | |
209 | \r | |
210 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
211 | bitwise AND between the read result and the value specified by AndData,\r | |
212 | performs a bitwise OR between the result of the AND operation and\r | |
213 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
214 | configuration register specified by Address. The value written to the PCI\r | |
215 | configuration register is returned. This function must guarantee that all PCI\r | |
216 | read and write operations are serialized.\r | |
217 | \r | |
218 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
219 | \r | |
220 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
221 | Register.\r | |
222 | @param AndData The value to AND with the PCI configuration register.\r | |
223 | @param OrData The value to OR with the result of the AND operation.\r | |
224 | \r | |
225 | @return The value written back to the PCI configuration register.\r | |
226 | \r | |
227 | **/\r | |
228 | UINT8\r | |
229 | EFIAPI\r | |
230 | PciExpressAndThenOr8 (\r | |
231 | IN UINTN Address,\r | |
232 | IN UINT8 AndData,\r | |
233 | IN UINT8 OrData\r | |
234 | )\r | |
235 | {\r | |
236 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
237 | return MmioAndThenOr8 (\r | |
238 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
239 | AndData,\r | |
240 | OrData\r | |
241 | );\r | |
242 | }\r | |
243 | \r | |
244 | /**\r | |
245 | Reads a bit field of a PCI configuration register.\r | |
246 | \r | |
247 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
248 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
249 | returned.\r | |
250 | \r | |
251 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
252 | If StartBit is greater than 7, then ASSERT().\r | |
253 | If EndBit is greater than 7, then ASSERT().\r | |
254 | If EndBit is less than StartBit, then ASSERT().\r | |
255 | \r | |
256 | @param Address The PCI configuration register to read.\r | |
257 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
258 | Range 0..7.\r | |
259 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
260 | Range 0..7.\r | |
261 | \r | |
262 | @return The value of the bit field read from the PCI configuration register.\r | |
263 | \r | |
264 | **/\r | |
265 | UINT8\r | |
266 | EFIAPI\r | |
267 | PciExpressBitFieldRead8 (\r | |
268 | IN UINTN Address,\r | |
269 | IN UINTN StartBit,\r | |
270 | IN UINTN EndBit\r | |
271 | )\r | |
272 | {\r | |
273 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
274 | return MmioBitFieldRead8 (\r | |
275 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
276 | StartBit,\r | |
277 | EndBit\r | |
278 | );\r | |
279 | }\r | |
280 | \r | |
281 | /**\r | |
282 | Writes a bit field to a PCI configuration register.\r | |
283 | \r | |
284 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
285 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
286 | destination PCI configuration register are preserved. The new value of the\r | |
287 | 8-bit register is returned.\r | |
288 | \r | |
289 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
290 | If StartBit is greater than 7, then ASSERT().\r | |
291 | If EndBit is greater than 7, then ASSERT().\r | |
292 | If EndBit is less than StartBit, then ASSERT().\r | |
293 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
294 | \r | |
295 | @param Address The PCI configuration register to write.\r | |
296 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
297 | Range 0..7.\r | |
298 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
299 | Range 0..7.\r | |
300 | @param Value The new value of the bit field.\r | |
301 | \r | |
302 | @return The value written back to the PCI configuration register.\r | |
303 | \r | |
304 | **/\r | |
305 | UINT8\r | |
306 | EFIAPI\r | |
307 | PciExpressBitFieldWrite8 (\r | |
308 | IN UINTN Address,\r | |
309 | IN UINTN StartBit,\r | |
310 | IN UINTN EndBit,\r | |
311 | IN UINT8 Value\r | |
312 | )\r | |
313 | {\r | |
314 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
315 | return MmioBitFieldWrite8 (\r | |
316 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
317 | StartBit,\r | |
318 | EndBit,\r | |
319 | Value\r | |
320 | );\r | |
321 | }\r | |
322 | \r | |
323 | /**\r | |
324 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
325 | writes the result back to the bit field in the 8-bit port.\r | |
326 | \r | |
327 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
328 | bitwise OR between the read result and the value specified by\r | |
329 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
330 | specified by Address. The value written to the PCI configuration register is\r | |
331 | returned. This function must guarantee that all PCI read and write operations\r | |
332 | are serialized. Extra left bits in OrData are stripped.\r | |
333 | \r | |
334 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
335 | If StartBit is greater than 7, then ASSERT().\r | |
336 | If EndBit is greater than 7, then ASSERT().\r | |
337 | If EndBit is less than StartBit, then ASSERT().\r | |
338 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
339 | \r | |
340 | @param Address The PCI configuration register to write.\r | |
341 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
342 | Range 0..7.\r | |
343 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
344 | Range 0..7.\r | |
345 | @param OrData The value to OR with the PCI configuration register.\r | |
346 | \r | |
347 | @return The value written back to the PCI configuration register.\r | |
348 | \r | |
349 | **/\r | |
350 | UINT8\r | |
351 | EFIAPI\r | |
352 | PciExpressBitFieldOr8 (\r | |
353 | IN UINTN Address,\r | |
354 | IN UINTN StartBit,\r | |
355 | IN UINTN EndBit,\r | |
356 | IN UINT8 OrData\r | |
357 | )\r | |
358 | {\r | |
359 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
360 | return MmioBitFieldOr8 (\r | |
361 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
362 | StartBit,\r | |
363 | EndBit,\r | |
364 | OrData\r | |
365 | );\r | |
366 | }\r | |
367 | \r | |
368 | /**\r | |
369 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
370 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
371 | \r | |
372 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
373 | bitwise AND between the read result and the value specified by AndData, and\r | |
374 | writes the result to the 8-bit PCI configuration register specified by\r | |
375 | Address. The value written to the PCI configuration register is returned.\r | |
376 | This function must guarantee that all PCI read and write operations are\r | |
377 | serialized. Extra left bits in AndData are stripped.\r | |
378 | \r | |
379 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
380 | If StartBit is greater than 7, then ASSERT().\r | |
381 | If EndBit is greater than 7, then ASSERT().\r | |
382 | If EndBit is less than StartBit, then ASSERT().\r | |
383 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
384 | \r | |
385 | @param Address The PCI configuration register to write.\r | |
386 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
387 | Range 0..7.\r | |
388 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
389 | Range 0..7.\r | |
390 | @param AndData The value to AND with the PCI configuration register.\r | |
391 | \r | |
392 | @return The value written back to the PCI configuration register.\r | |
393 | \r | |
394 | **/\r | |
395 | UINT8\r | |
396 | EFIAPI\r | |
397 | PciExpressBitFieldAnd8 (\r | |
398 | IN UINTN Address,\r | |
399 | IN UINTN StartBit,\r | |
400 | IN UINTN EndBit,\r | |
401 | IN UINT8 AndData\r | |
402 | )\r | |
403 | {\r | |
404 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
405 | return MmioBitFieldAnd8 (\r | |
406 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
407 | StartBit,\r | |
408 | EndBit,\r | |
409 | AndData\r | |
410 | );\r | |
411 | }\r | |
412 | \r | |
413 | /**\r | |
414 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
415 | bitwise OR, and writes the result back to the bit field in the\r | |
416 | 8-bit port.\r | |
417 | \r | |
418 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
419 | bitwise AND followed by a bitwise OR between the read result and\r | |
420 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
421 | configuration register specified by Address. The value written to the PCI\r | |
422 | configuration register is returned. This function must guarantee that all PCI\r | |
423 | read and write operations are serialized. Extra left bits in both AndData and\r | |
424 | OrData are stripped.\r | |
425 | \r | |
426 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
427 | If StartBit is greater than 7, then ASSERT().\r | |
428 | If EndBit is greater than 7, then ASSERT().\r | |
429 | If EndBit is less than StartBit, then ASSERT().\r | |
430 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
431 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
432 | \r | |
433 | @param Address The PCI configuration register to write.\r | |
434 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
435 | Range 0..7.\r | |
436 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
437 | Range 0..7.\r | |
438 | @param AndData The value to AND with the PCI configuration register.\r | |
439 | @param OrData The value to OR with the result of the AND operation.\r | |
440 | \r | |
441 | @return The value written back to the PCI configuration register.\r | |
442 | \r | |
443 | **/\r | |
444 | UINT8\r | |
445 | EFIAPI\r | |
446 | PciExpressBitFieldAndThenOr8 (\r | |
447 | IN UINTN Address,\r | |
448 | IN UINTN StartBit,\r | |
449 | IN UINTN EndBit,\r | |
450 | IN UINT8 AndData,\r | |
451 | IN UINT8 OrData\r | |
452 | )\r | |
453 | {\r | |
454 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
455 | return MmioBitFieldAndThenOr8 (\r | |
456 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
457 | StartBit,\r | |
458 | EndBit,\r | |
459 | AndData,\r | |
460 | OrData\r | |
461 | );\r | |
462 | }\r | |
463 | \r | |
464 | /**\r | |
465 | Reads a 16-bit PCI configuration register.\r | |
466 | \r | |
467 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
468 | This function must guarantee that all PCI read and write operations are\r | |
469 | serialized.\r | |
470 | \r | |
471 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
472 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
473 | \r | |
474 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
475 | Register.\r | |
476 | \r | |
477 | @return The read value from the PCI configuration register.\r | |
478 | \r | |
479 | **/\r | |
480 | UINT16\r | |
481 | EFIAPI\r | |
482 | PciExpressRead16 (\r | |
483 | IN UINTN Address\r | |
484 | )\r | |
485 | {\r | |
486 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
487 | return MmioRead16 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
488 | }\r | |
489 | \r | |
490 | /**\r | |
491 | Writes a 16-bit PCI configuration register.\r | |
492 | \r | |
493 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
494 | value specified by Value. Value is returned. This function must guarantee\r | |
495 | that all PCI read and write operations are serialized.\r | |
496 | \r | |
497 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
498 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
499 | \r | |
500 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
501 | Register.\r | |
502 | @param Value The value to write.\r | |
503 | \r | |
504 | @return The value written to the PCI configuration register.\r | |
505 | \r | |
506 | **/\r | |
507 | UINT16\r | |
508 | EFIAPI\r | |
509 | PciExpressWrite16 (\r | |
510 | IN UINTN Address,\r | |
511 | IN UINT16 Value\r | |
512 | )\r | |
513 | {\r | |
514 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
515 | return MmioWrite16 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
516 | }\r | |
517 | \r | |
518 | /**\r | |
519 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
520 | a 16-bit value.\r | |
521 | \r | |
522 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
523 | bitwise OR between the read result and the value specified by\r | |
524 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
525 | specified by Address. The value written to the PCI configuration register is\r | |
526 | returned. This function must guarantee that all PCI read and write operations\r | |
527 | are serialized.\r | |
528 | \r | |
529 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
530 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
531 | \r | |
532 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
533 | Register.\r | |
534 | @param OrData The value to OR with the PCI configuration register.\r | |
535 | \r | |
536 | @return The value written back to the PCI configuration register.\r | |
537 | \r | |
538 | **/\r | |
539 | UINT16\r | |
540 | EFIAPI\r | |
541 | PciExpressOr16 (\r | |
542 | IN UINTN Address,\r | |
543 | IN UINT16 OrData\r | |
544 | )\r | |
545 | {\r | |
546 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
547 | return MmioOr16 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
548 | }\r | |
549 | \r | |
550 | /**\r | |
551 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
552 | value.\r | |
553 | \r | |
554 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
555 | bitwise AND between the read result and the value specified by AndData, and\r | |
556 | writes the result to the 16-bit PCI configuration register specified by\r | |
557 | Address. The value written to the PCI configuration register is returned.\r | |
558 | This function must guarantee that all PCI read and write operations are\r | |
559 | serialized.\r | |
560 | \r | |
561 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
562 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
563 | \r | |
564 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
565 | Register.\r | |
566 | @param AndData The value to AND with the PCI configuration register.\r | |
567 | \r | |
568 | @return The value written back to the PCI configuration register.\r | |
569 | \r | |
570 | **/\r | |
571 | UINT16\r | |
572 | EFIAPI\r | |
573 | PciExpressAnd16 (\r | |
574 | IN UINTN Address,\r | |
575 | IN UINT16 AndData\r | |
576 | )\r | |
577 | {\r | |
578 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
579 | return MmioAnd16 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
580 | }\r | |
581 | \r | |
582 | /**\r | |
583 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
584 | value, followed a bitwise OR with another 16-bit value.\r | |
585 | \r | |
586 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
587 | bitwise AND between the read result and the value specified by AndData,\r | |
588 | performs a bitwise OR between the result of the AND operation and\r | |
589 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
590 | configuration register specified by Address. The value written to the PCI\r | |
591 | configuration register is returned. This function must guarantee that all PCI\r | |
592 | read and write operations are serialized.\r | |
593 | \r | |
594 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
595 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
596 | \r | |
597 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
598 | Register.\r | |
599 | @param AndData The value to AND with the PCI configuration register.\r | |
600 | @param OrData The value to OR with the result of the AND operation.\r | |
601 | \r | |
602 | @return The value written back to the PCI configuration register.\r | |
603 | \r | |
604 | **/\r | |
605 | UINT16\r | |
606 | EFIAPI\r | |
607 | PciExpressAndThenOr16 (\r | |
608 | IN UINTN Address,\r | |
609 | IN UINT16 AndData,\r | |
610 | IN UINT16 OrData\r | |
611 | )\r | |
612 | {\r | |
613 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
614 | return MmioAndThenOr16 (\r | |
615 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
616 | AndData,\r | |
617 | OrData\r | |
618 | );\r | |
619 | }\r | |
620 | \r | |
621 | /**\r | |
622 | Reads a bit field of a PCI configuration register.\r | |
623 | \r | |
624 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
625 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
626 | returned.\r | |
627 | \r | |
628 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
629 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
630 | If StartBit is greater than 15, then ASSERT().\r | |
631 | If EndBit is greater than 15, then ASSERT().\r | |
632 | If EndBit is less than StartBit, then ASSERT().\r | |
633 | \r | |
634 | @param Address The PCI configuration register to read.\r | |
635 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
636 | Range 0..15.\r | |
637 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
638 | Range 0..15.\r | |
639 | \r | |
640 | @return The value of the bit field read from the PCI configuration register.\r | |
641 | \r | |
642 | **/\r | |
643 | UINT16\r | |
644 | EFIAPI\r | |
645 | PciExpressBitFieldRead16 (\r | |
646 | IN UINTN Address,\r | |
647 | IN UINTN StartBit,\r | |
648 | IN UINTN EndBit\r | |
649 | )\r | |
650 | {\r | |
651 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
652 | return MmioBitFieldRead16 (\r | |
653 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
654 | StartBit,\r | |
655 | EndBit\r | |
656 | );\r | |
657 | }\r | |
658 | \r | |
659 | /**\r | |
660 | Writes a bit field to a PCI configuration register.\r | |
661 | \r | |
662 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
663 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
664 | destination PCI configuration register are preserved. The new value of the\r | |
665 | 16-bit register is returned.\r | |
666 | \r | |
667 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
668 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
669 | If StartBit is greater than 15, then ASSERT().\r | |
670 | If EndBit is greater than 15, then ASSERT().\r | |
671 | If EndBit is less than StartBit, then ASSERT().\r | |
672 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
673 | \r | |
674 | @param Address The PCI configuration register to write.\r | |
675 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
676 | Range 0..15.\r | |
677 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
678 | Range 0..15.\r | |
679 | @param Value The new value of the bit field.\r | |
680 | \r | |
681 | @return The value written back to the PCI configuration register.\r | |
682 | \r | |
683 | **/\r | |
684 | UINT16\r | |
685 | EFIAPI\r | |
686 | PciExpressBitFieldWrite16 (\r | |
687 | IN UINTN Address,\r | |
688 | IN UINTN StartBit,\r | |
689 | IN UINTN EndBit,\r | |
690 | IN UINT16 Value\r | |
691 | )\r | |
692 | {\r | |
693 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
694 | return MmioBitFieldWrite16 (\r | |
695 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
696 | StartBit,\r | |
697 | EndBit,\r | |
698 | Value\r | |
699 | );\r | |
700 | }\r | |
701 | \r | |
702 | /**\r | |
703 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
704 | writes the result back to the bit field in the 16-bit port.\r | |
705 | \r | |
706 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
707 | bitwise OR between the read result and the value specified by\r | |
708 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
709 | specified by Address. The value written to the PCI configuration register is\r | |
710 | returned. This function must guarantee that all PCI read and write operations\r | |
711 | are serialized. Extra left bits in OrData are stripped.\r | |
712 | \r | |
713 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
714 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
715 | If StartBit is greater than 15, then ASSERT().\r | |
716 | If EndBit is greater than 15, then ASSERT().\r | |
717 | If EndBit is less than StartBit, then ASSERT().\r | |
718 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
719 | \r | |
720 | @param Address The PCI configuration register to write.\r | |
721 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
722 | Range 0..15.\r | |
723 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
724 | Range 0..15.\r | |
725 | @param OrData The value to OR with the PCI configuration register.\r | |
726 | \r | |
727 | @return The value written back to the PCI configuration register.\r | |
728 | \r | |
729 | **/\r | |
730 | UINT16\r | |
731 | EFIAPI\r | |
732 | PciExpressBitFieldOr16 (\r | |
733 | IN UINTN Address,\r | |
734 | IN UINTN StartBit,\r | |
735 | IN UINTN EndBit,\r | |
736 | IN UINT16 OrData\r | |
737 | )\r | |
738 | {\r | |
739 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
740 | return MmioBitFieldOr16 (\r | |
741 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
742 | StartBit,\r | |
743 | EndBit,\r | |
744 | OrData\r | |
745 | );\r | |
746 | }\r | |
747 | \r | |
748 | /**\r | |
749 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
750 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
751 | \r | |
752 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
753 | bitwise AND between the read result and the value specified by AndData, and\r | |
754 | writes the result to the 16-bit PCI configuration register specified by\r | |
755 | Address. The value written to the PCI configuration register is returned.\r | |
756 | This function must guarantee that all PCI read and write operations are\r | |
757 | serialized. Extra left bits in AndData are stripped.\r | |
758 | \r | |
759 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
760 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
761 | If StartBit is greater than 15, then ASSERT().\r | |
762 | If EndBit is greater than 15, then ASSERT().\r | |
763 | If EndBit is less than StartBit, then ASSERT().\r | |
764 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
765 | \r | |
766 | @param Address The PCI configuration register to write.\r | |
767 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
768 | Range 0..15.\r | |
769 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
770 | Range 0..15.\r | |
771 | @param AndData The value to AND with the PCI configuration register.\r | |
772 | \r | |
773 | @return The value written back to the PCI configuration register.\r | |
774 | \r | |
775 | **/\r | |
776 | UINT16\r | |
777 | EFIAPI\r | |
778 | PciExpressBitFieldAnd16 (\r | |
779 | IN UINTN Address,\r | |
780 | IN UINTN StartBit,\r | |
781 | IN UINTN EndBit,\r | |
782 | IN UINT16 AndData\r | |
783 | )\r | |
784 | {\r | |
785 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
786 | return MmioBitFieldAnd16 (\r | |
787 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
788 | StartBit,\r | |
789 | EndBit,\r | |
790 | AndData\r | |
791 | );\r | |
792 | }\r | |
793 | \r | |
794 | /**\r | |
795 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
796 | bitwise OR, and writes the result back to the bit field in the\r | |
797 | 16-bit port.\r | |
798 | \r | |
799 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
800 | bitwise AND followed by a bitwise OR between the read result and\r | |
801 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
802 | configuration register specified by Address. The value written to the PCI\r | |
803 | configuration register is returned. This function must guarantee that all PCI\r | |
804 | read and write operations are serialized. Extra left bits in both AndData and\r | |
805 | OrData are stripped.\r | |
806 | \r | |
807 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
808 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
809 | If StartBit is greater than 15, then ASSERT().\r | |
810 | If EndBit is greater than 15, then ASSERT().\r | |
811 | If EndBit is less than StartBit, then ASSERT().\r | |
812 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
813 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
814 | \r | |
815 | @param Address The PCI configuration register to write.\r | |
816 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
817 | Range 0..15.\r | |
818 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
819 | Range 0..15.\r | |
820 | @param AndData The value to AND with the PCI configuration register.\r | |
821 | @param OrData The value to OR with the result of the AND operation.\r | |
822 | \r | |
823 | @return The value written back to the PCI configuration register.\r | |
824 | \r | |
825 | **/\r | |
826 | UINT16\r | |
827 | EFIAPI\r | |
828 | PciExpressBitFieldAndThenOr16 (\r | |
829 | IN UINTN Address,\r | |
830 | IN UINTN StartBit,\r | |
831 | IN UINTN EndBit,\r | |
832 | IN UINT16 AndData,\r | |
833 | IN UINT16 OrData\r | |
834 | )\r | |
835 | {\r | |
836 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
837 | return MmioBitFieldAndThenOr16 (\r | |
838 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
839 | StartBit,\r | |
840 | EndBit,\r | |
841 | AndData,\r | |
842 | OrData\r | |
843 | );\r | |
844 | }\r | |
845 | \r | |
846 | /**\r | |
847 | Reads a 32-bit PCI configuration register.\r | |
848 | \r | |
849 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
850 | This function must guarantee that all PCI read and write operations are\r | |
851 | serialized.\r | |
852 | \r | |
853 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
854 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
855 | \r | |
856 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
857 | Register.\r | |
858 | \r | |
859 | @return The read value from the PCI configuration register.\r | |
860 | \r | |
861 | **/\r | |
862 | UINT32\r | |
863 | EFIAPI\r | |
864 | PciExpressRead32 (\r | |
865 | IN UINTN Address\r | |
866 | )\r | |
867 | {\r | |
868 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
869 | return MmioRead32 ((UINTN) GetPciExpressBaseAddress () + Address);\r | |
870 | }\r | |
871 | \r | |
872 | /**\r | |
873 | Writes a 32-bit PCI configuration register.\r | |
874 | \r | |
875 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
876 | value specified by Value. Value is returned. This function must guarantee\r | |
877 | that all PCI read and write operations are serialized.\r | |
878 | \r | |
879 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
880 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
881 | \r | |
882 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
883 | Register.\r | |
884 | @param Value The value to write.\r | |
885 | \r | |
886 | @return The value written to the PCI configuration register.\r | |
887 | \r | |
888 | **/\r | |
889 | UINT32\r | |
890 | EFIAPI\r | |
891 | PciExpressWrite32 (\r | |
892 | IN UINTN Address,\r | |
893 | IN UINT32 Value\r | |
894 | )\r | |
895 | {\r | |
896 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
897 | return MmioWrite32 ((UINTN) GetPciExpressBaseAddress () + Address, Value);\r | |
898 | }\r | |
899 | \r | |
900 | /**\r | |
901 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
902 | a 32-bit value.\r | |
903 | \r | |
904 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
905 | bitwise OR between the read result and the value specified by\r | |
906 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
907 | specified by Address. The value written to the PCI configuration register is\r | |
908 | returned. This function must guarantee that all PCI read and write operations\r | |
909 | are serialized.\r | |
910 | \r | |
911 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
912 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
913 | \r | |
914 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
915 | Register.\r | |
916 | @param OrData The value to OR with the PCI configuration register.\r | |
917 | \r | |
918 | @return The value written back to the PCI configuration register.\r | |
919 | \r | |
920 | **/\r | |
921 | UINT32\r | |
922 | EFIAPI\r | |
923 | PciExpressOr32 (\r | |
924 | IN UINTN Address,\r | |
925 | IN UINT32 OrData\r | |
926 | )\r | |
927 | {\r | |
928 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
929 | return MmioOr32 ((UINTN) GetPciExpressBaseAddress () + Address, OrData);\r | |
930 | }\r | |
931 | \r | |
932 | /**\r | |
933 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
934 | value.\r | |
935 | \r | |
936 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
937 | bitwise AND between the read result and the value specified by AndData, and\r | |
938 | writes the result to the 32-bit PCI configuration register specified by\r | |
939 | Address. The value written to the PCI configuration register is returned.\r | |
940 | This function must guarantee that all PCI read and write operations are\r | |
941 | serialized.\r | |
942 | \r | |
943 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
944 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
945 | \r | |
946 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
947 | Register.\r | |
948 | @param AndData The value to AND with the PCI configuration register.\r | |
949 | \r | |
950 | @return The value written back to the PCI configuration register.\r | |
951 | \r | |
952 | **/\r | |
953 | UINT32\r | |
954 | EFIAPI\r | |
955 | PciExpressAnd32 (\r | |
956 | IN UINTN Address,\r | |
957 | IN UINT32 AndData\r | |
958 | )\r | |
959 | {\r | |
960 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
961 | return MmioAnd32 ((UINTN) GetPciExpressBaseAddress () + Address, AndData);\r | |
962 | }\r | |
963 | \r | |
964 | /**\r | |
965 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
966 | value, followed a bitwise OR with another 32-bit value.\r | |
967 | \r | |
968 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
969 | bitwise AND between the read result and the value specified by AndData,\r | |
970 | performs a bitwise OR between the result of the AND operation and\r | |
971 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
972 | configuration register specified by Address. The value written to the PCI\r | |
973 | configuration register is returned. This function must guarantee that all PCI\r | |
974 | read and write operations are serialized.\r | |
975 | \r | |
976 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
977 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
978 | \r | |
979 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
980 | Register.\r | |
981 | @param AndData The value to AND with the PCI configuration register.\r | |
982 | @param OrData The value to OR with the result of the AND operation.\r | |
983 | \r | |
984 | @return The value written back to the PCI configuration register.\r | |
985 | \r | |
986 | **/\r | |
987 | UINT32\r | |
988 | EFIAPI\r | |
989 | PciExpressAndThenOr32 (\r | |
990 | IN UINTN Address,\r | |
991 | IN UINT32 AndData,\r | |
992 | IN UINT32 OrData\r | |
993 | )\r | |
994 | {\r | |
995 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
996 | return MmioAndThenOr32 (\r | |
997 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
998 | AndData,\r | |
999 | OrData\r | |
1000 | );\r | |
1001 | }\r | |
1002 | \r | |
1003 | /**\r | |
1004 | Reads a bit field of a PCI configuration register.\r | |
1005 | \r | |
1006 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1007 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1008 | returned.\r | |
1009 | \r | |
1010 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1011 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1012 | If StartBit is greater than 31, then ASSERT().\r | |
1013 | If EndBit is greater than 31, then ASSERT().\r | |
1014 | If EndBit is less than StartBit, then ASSERT().\r | |
1015 | \r | |
1016 | @param Address The PCI configuration register to read.\r | |
1017 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1018 | Range 0..31.\r | |
1019 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1020 | Range 0..31.\r | |
1021 | \r | |
1022 | @return The value of the bit field read from the PCI configuration register.\r | |
1023 | \r | |
1024 | **/\r | |
1025 | UINT32\r | |
1026 | EFIAPI\r | |
1027 | PciExpressBitFieldRead32 (\r | |
1028 | IN UINTN Address,\r | |
1029 | IN UINTN StartBit,\r | |
1030 | IN UINTN EndBit\r | |
1031 | )\r | |
1032 | {\r | |
1033 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1034 | return MmioBitFieldRead32 (\r | |
1035 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1036 | StartBit,\r | |
1037 | EndBit\r | |
1038 | );\r | |
1039 | }\r | |
1040 | \r | |
1041 | /**\r | |
1042 | Writes a bit field to a PCI configuration register.\r | |
1043 | \r | |
1044 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1045 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1046 | destination PCI configuration register are preserved. The new value of the\r | |
1047 | 32-bit register is returned.\r | |
1048 | \r | |
1049 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1050 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1051 | If StartBit is greater than 31, then ASSERT().\r | |
1052 | If EndBit is greater than 31, then ASSERT().\r | |
1053 | If EndBit is less than StartBit, then ASSERT().\r | |
1054 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1055 | \r | |
1056 | @param Address The PCI configuration register to write.\r | |
1057 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1058 | Range 0..31.\r | |
1059 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1060 | Range 0..31.\r | |
1061 | @param Value The new value of the bit field.\r | |
1062 | \r | |
1063 | @return The value written back to the PCI configuration register.\r | |
1064 | \r | |
1065 | **/\r | |
1066 | UINT32\r | |
1067 | EFIAPI\r | |
1068 | PciExpressBitFieldWrite32 (\r | |
1069 | IN UINTN Address,\r | |
1070 | IN UINTN StartBit,\r | |
1071 | IN UINTN EndBit,\r | |
1072 | IN UINT32 Value\r | |
1073 | )\r | |
1074 | {\r | |
1075 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1076 | return MmioBitFieldWrite32 (\r | |
1077 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1078 | StartBit,\r | |
1079 | EndBit,\r | |
1080 | Value\r | |
1081 | );\r | |
1082 | }\r | |
1083 | \r | |
1084 | /**\r | |
1085 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1086 | writes the result back to the bit field in the 32-bit port.\r | |
1087 | \r | |
1088 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1089 | bitwise OR between the read result and the value specified by\r | |
1090 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1091 | specified by Address. The value written to the PCI configuration register is\r | |
1092 | returned. This function must guarantee that all PCI read and write operations\r | |
1093 | are serialized. Extra left bits in OrData are stripped.\r | |
1094 | \r | |
1095 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1096 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1097 | If StartBit is greater than 31, then ASSERT().\r | |
1098 | If EndBit is greater than 31, then ASSERT().\r | |
1099 | If EndBit is less than StartBit, then ASSERT().\r | |
1100 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1101 | \r | |
1102 | @param Address The PCI configuration register to write.\r | |
1103 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1104 | Range 0..31.\r | |
1105 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1106 | Range 0..31.\r | |
1107 | @param OrData The value to OR with the PCI configuration register.\r | |
1108 | \r | |
1109 | @return The value written back to the PCI configuration register.\r | |
1110 | \r | |
1111 | **/\r | |
1112 | UINT32\r | |
1113 | EFIAPI\r | |
1114 | PciExpressBitFieldOr32 (\r | |
1115 | IN UINTN Address,\r | |
1116 | IN UINTN StartBit,\r | |
1117 | IN UINTN EndBit,\r | |
1118 | IN UINT32 OrData\r | |
1119 | )\r | |
1120 | {\r | |
1121 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1122 | return MmioBitFieldOr32 (\r | |
1123 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1124 | StartBit,\r | |
1125 | EndBit,\r | |
1126 | OrData\r | |
1127 | );\r | |
1128 | }\r | |
1129 | \r | |
1130 | /**\r | |
1131 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1132 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1133 | \r | |
1134 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1135 | bitwise AND between the read result and the value specified by AndData, and\r | |
1136 | writes the result to the 32-bit PCI configuration register specified by\r | |
1137 | Address. The value written to the PCI configuration register is returned.\r | |
1138 | This function must guarantee that all PCI read and write operations are\r | |
1139 | serialized. Extra left bits in AndData are stripped.\r | |
1140 | \r | |
1141 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1142 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1143 | If StartBit is greater than 31, then ASSERT().\r | |
1144 | If EndBit is greater than 31, then ASSERT().\r | |
1145 | If EndBit is less than StartBit, then ASSERT().\r | |
1146 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1147 | \r | |
1148 | @param Address The PCI configuration register to write.\r | |
1149 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1150 | Range 0..31.\r | |
1151 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1152 | Range 0..31.\r | |
1153 | @param AndData The value to AND with the PCI configuration register.\r | |
1154 | \r | |
1155 | @return The value written back to the PCI configuration register.\r | |
1156 | \r | |
1157 | **/\r | |
1158 | UINT32\r | |
1159 | EFIAPI\r | |
1160 | PciExpressBitFieldAnd32 (\r | |
1161 | IN UINTN Address,\r | |
1162 | IN UINTN StartBit,\r | |
1163 | IN UINTN EndBit,\r | |
1164 | IN UINT32 AndData\r | |
1165 | )\r | |
1166 | {\r | |
1167 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1168 | return MmioBitFieldAnd32 (\r | |
1169 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1170 | StartBit,\r | |
1171 | EndBit,\r | |
1172 | AndData\r | |
1173 | );\r | |
1174 | }\r | |
1175 | \r | |
1176 | /**\r | |
1177 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1178 | bitwise OR, and writes the result back to the bit field in the\r | |
1179 | 32-bit port.\r | |
1180 | \r | |
1181 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1182 | bitwise AND followed by a bitwise OR between the read result and\r | |
1183 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1184 | configuration register specified by Address. The value written to the PCI\r | |
1185 | configuration register is returned. This function must guarantee that all PCI\r | |
1186 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1187 | OrData are stripped.\r | |
1188 | \r | |
1189 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1190 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1191 | If StartBit is greater than 31, then ASSERT().\r | |
1192 | If EndBit is greater than 31, then ASSERT().\r | |
1193 | If EndBit is less than StartBit, then ASSERT().\r | |
1194 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1195 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1196 | \r | |
1197 | @param Address The PCI configuration register to write.\r | |
1198 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1199 | Range 0..31.\r | |
1200 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1201 | Range 0..31.\r | |
1202 | @param AndData The value to AND with the PCI configuration register.\r | |
1203 | @param OrData The value to OR with the result of the AND operation.\r | |
1204 | \r | |
1205 | @return The value written back to the PCI configuration register.\r | |
1206 | \r | |
1207 | **/\r | |
1208 | UINT32\r | |
1209 | EFIAPI\r | |
1210 | PciExpressBitFieldAndThenOr32 (\r | |
1211 | IN UINTN Address,\r | |
1212 | IN UINTN StartBit,\r | |
1213 | IN UINTN EndBit,\r | |
1214 | IN UINT32 AndData,\r | |
1215 | IN UINT32 OrData\r | |
1216 | )\r | |
1217 | {\r | |
1218 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1219 | return MmioBitFieldAndThenOr32 (\r | |
1220 | (UINTN) GetPciExpressBaseAddress () + Address,\r | |
1221 | StartBit,\r | |
1222 | EndBit,\r | |
1223 | AndData,\r | |
1224 | OrData\r | |
1225 | );\r | |
1226 | }\r | |
1227 | \r | |
1228 | /**\r | |
1229 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1230 | \r | |
1231 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1232 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1233 | configuration registers from a single PCI function to be read. Size is\r | |
1234 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
7a908953 | 1235 | from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
ad3359eb LE |
1236 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
1237 | end of the range.\r | |
1238 | \r | |
1239 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1240 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1241 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1242 | \r | |
1243 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
1244 | Function and Register.\r | |
1245 | @param Size The size in bytes of the transfer.\r | |
1246 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1247 | \r | |
1248 | @return Size read data from StartAddress.\r | |
1249 | \r | |
1250 | **/\r | |
1251 | UINTN\r | |
1252 | EFIAPI\r | |
1253 | PciExpressReadBuffer (\r | |
1254 | IN UINTN StartAddress,\r | |
1255 | IN UINTN Size,\r | |
1256 | OUT VOID *Buffer\r | |
1257 | )\r | |
1258 | {\r | |
1259 | UINTN ReturnValue;\r | |
1260 | \r | |
1261 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1262 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1263 | \r | |
1264 | if (Size == 0) {\r | |
1265 | return Size;\r | |
1266 | }\r | |
1267 | \r | |
1268 | ASSERT (Buffer != NULL);\r | |
1269 | \r | |
1270 | //\r | |
1271 | // Save Size for return\r | |
1272 | //\r | |
1273 | ReturnValue = Size;\r | |
1274 | \r | |
1275 | if ((StartAddress & 1) != 0) {\r | |
1276 | //\r | |
1277 | // Read a byte if StartAddress is byte aligned\r | |
1278 | //\r | |
1279 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1280 | StartAddress += sizeof (UINT8);\r | |
1281 | Size -= sizeof (UINT8);\r | |
1282 | Buffer = (UINT8*)Buffer + 1;\r | |
1283 | }\r | |
1284 | \r | |
1285 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1286 | //\r | |
1287 | // Read a word if StartAddress is word aligned\r | |
1288 | //\r | |
1289 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r | |
1290 | \r | |
1291 | StartAddress += sizeof (UINT16);\r | |
1292 | Size -= sizeof (UINT16);\r | |
1293 | Buffer = (UINT16*)Buffer + 1;\r | |
1294 | }\r | |
1295 | \r | |
1296 | while (Size >= sizeof (UINT32)) {\r | |
1297 | //\r | |
1298 | // Read as many double words as possible\r | |
1299 | //\r | |
1300 | WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r | |
1301 | \r | |
1302 | StartAddress += sizeof (UINT32);\r | |
1303 | Size -= sizeof (UINT32);\r | |
1304 | Buffer = (UINT32*)Buffer + 1;\r | |
1305 | }\r | |
1306 | \r | |
1307 | if (Size >= sizeof (UINT16)) {\r | |
1308 | //\r | |
1309 | // Read the last remaining word if exist\r | |
1310 | //\r | |
1311 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r | |
1312 | StartAddress += sizeof (UINT16);\r | |
1313 | Size -= sizeof (UINT16);\r | |
1314 | Buffer = (UINT16*)Buffer + 1;\r | |
1315 | }\r | |
1316 | \r | |
1317 | if (Size >= sizeof (UINT8)) {\r | |
1318 | //\r | |
1319 | // Read the last remaining byte if exist\r | |
1320 | //\r | |
1321 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1322 | }\r | |
1323 | \r | |
1324 | return ReturnValue;\r | |
1325 | }\r | |
1326 | \r | |
1327 | /**\r | |
1328 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1329 | configuration space.\r | |
1330 | \r | |
1331 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1332 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1333 | configuration registers from a single PCI function to be written. Size is\r | |
1334 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
7a908953 | 1335 | write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r |
ad3359eb LE |
1336 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
1337 | and the end of the range.\r | |
1338 | \r | |
1339 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1340 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1341 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1342 | \r | |
1343 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
1344 | Function and Register.\r | |
1345 | @param Size The size in bytes of the transfer.\r | |
1346 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1347 | \r | |
1348 | @return Size written to StartAddress.\r | |
1349 | \r | |
1350 | **/\r | |
1351 | UINTN\r | |
1352 | EFIAPI\r | |
1353 | PciExpressWriteBuffer (\r | |
1354 | IN UINTN StartAddress,\r | |
1355 | IN UINTN Size,\r | |
1356 | IN VOID *Buffer\r | |
1357 | )\r | |
1358 | {\r | |
1359 | UINTN ReturnValue;\r | |
1360 | \r | |
1361 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1362 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1363 | \r | |
1364 | if (Size == 0) {\r | |
1365 | return 0;\r | |
1366 | }\r | |
1367 | \r | |
1368 | ASSERT (Buffer != NULL);\r | |
1369 | \r | |
1370 | //\r | |
1371 | // Save Size for return\r | |
1372 | //\r | |
1373 | ReturnValue = Size;\r | |
1374 | \r | |
1375 | if ((StartAddress & 1) != 0) {\r | |
1376 | //\r | |
1377 | // Write a byte if StartAddress is byte aligned\r | |
1378 | //\r | |
1379 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1380 | StartAddress += sizeof (UINT8);\r | |
1381 | Size -= sizeof (UINT8);\r | |
1382 | Buffer = (UINT8*)Buffer + 1;\r | |
1383 | }\r | |
1384 | \r | |
1385 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1386 | //\r | |
1387 | // Write a word if StartAddress is word aligned\r | |
1388 | //\r | |
1389 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r | |
1390 | StartAddress += sizeof (UINT16);\r | |
1391 | Size -= sizeof (UINT16);\r | |
1392 | Buffer = (UINT16*)Buffer + 1;\r | |
1393 | }\r | |
1394 | \r | |
1395 | while (Size >= sizeof (UINT32)) {\r | |
1396 | //\r | |
1397 | // Write as many double words as possible\r | |
1398 | //\r | |
1399 | PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r | |
1400 | StartAddress += sizeof (UINT32);\r | |
1401 | Size -= sizeof (UINT32);\r | |
1402 | Buffer = (UINT32*)Buffer + 1;\r | |
1403 | }\r | |
1404 | \r | |
1405 | if (Size >= sizeof (UINT16)) {\r | |
1406 | //\r | |
1407 | // Write the last remaining word if exist\r | |
1408 | //\r | |
1409 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r | |
1410 | StartAddress += sizeof (UINT16);\r | |
1411 | Size -= sizeof (UINT16);\r | |
1412 | Buffer = (UINT16*)Buffer + 1;\r | |
1413 | }\r | |
1414 | \r | |
1415 | if (Size >= sizeof (UINT8)) {\r | |
1416 | //\r | |
1417 | // Write the last remaining byte if exist\r | |
1418 | //\r | |
1419 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1420 | }\r | |
1421 | \r | |
1422 | return ReturnValue;\r | |
1423 | }\r |