projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| ef42ef7e AB |
1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r | |
| 4 | Copyright (c) 2014 - 2018, Linaro Ltd. All rights reserved.<BR>\r | |
| 5 | \r | |
| 9792fb0e | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| ef42ef7e AB |
7 | \r |
| 8 | **/\r | |
| 9 | \r | |
| 10 | #include <Library/ArmGenericTimerCounterLib.h>\r | |
| 11 | #include <Library/ArmLib.h>\r | |
| 12 | \r | |
| 13 | VOID\r | |
| 14 | EFIAPI\r | |
| 15 | ArmGenericTimerEnableTimer (\r | |
| 16 | VOID\r | |
| 17 | )\r | |
| 18 | {\r | |
| 2b16a4fb | 19 | UINTN TimerCtrlReg;\r |
| ef42ef7e | 20 | \r |
| 2b16a4fb | 21 | TimerCtrlReg = ArmReadCntvCtl ();\r |
| ef42ef7e AB |
22 | TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;\r |
| 23 | ArmWriteCntvCtl (TimerCtrlReg);\r | |
| 24 | }\r | |
| 25 | \r | |
| 26 | VOID\r | |
| 27 | EFIAPI\r | |
| 28 | ArmGenericTimerReenableTimer (\r | |
| 29 | VOID\r | |
| 30 | )\r | |
| 31 | {\r | |
| 2b16a4fb | 32 | UINTN TimerCtrlReg;\r |
| ef42ef7e | 33 | \r |
| 2b16a4fb | 34 | TimerCtrlReg = ArmReadCntvCtl ();\r |
| ef42ef7e AB |
35 | TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;\r |
| 36 | \r | |
| 37 | //\r | |
| 38 | // When running under Xen, we need to unmask the interrupt on the timer side\r | |
| 39 | // as Xen will mask it when servicing the interrupt at the hypervisor level\r | |
| 40 | // and delivering the virtual timer interrupt to the guest. Otherwise, the\r | |
| 41 | // interrupt will fire again, trapping into the hypervisor again, etc. etc.\r | |
| 42 | //\r | |
| 43 | TimerCtrlReg &= ~ARM_ARCH_TIMER_IMASK;\r | |
| 44 | ArmWriteCntvCtl (TimerCtrlReg);\r | |
| 45 | }\r | |
| 46 | \r | |
| 47 | VOID\r | |
| 48 | EFIAPI\r | |
| 49 | ArmGenericTimerDisableTimer (\r | |
| 50 | VOID\r | |
| 51 | )\r | |
| 52 | {\r | |
| 2b16a4fb | 53 | UINTN TimerCtrlReg;\r |
| ef42ef7e | 54 | \r |
| 2b16a4fb | 55 | TimerCtrlReg = ArmReadCntvCtl ();\r |
| ef42ef7e AB |
56 | TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;\r |
| 57 | ArmWriteCntvCtl (TimerCtrlReg);\r | |
| 58 | }\r | |
| 59 | \r | |
| 60 | VOID\r | |
| 61 | EFIAPI\r | |
| 62 | ArmGenericTimerSetTimerFreq (\r | |
| 63 | IN UINTN FreqInHz\r | |
| 64 | )\r | |
| 65 | {\r | |
| 66 | ArmWriteCntFrq (FreqInHz);\r | |
| 67 | }\r | |
| 68 | \r | |
| 69 | UINTN\r | |
| 70 | EFIAPI\r | |
| 71 | ArmGenericTimerGetTimerFreq (\r | |
| 72 | VOID\r | |
| 73 | )\r | |
| 74 | {\r | |
| 75 | return ArmReadCntFrq ();\r | |
| 76 | }\r | |
| 77 | \r | |
| 78 | UINTN\r | |
| 79 | EFIAPI\r | |
| 80 | ArmGenericTimerGetTimerVal (\r | |
| 81 | VOID\r | |
| 82 | )\r | |
| 83 | {\r | |
| 84 | return ArmReadCntvTval ();\r | |
| 85 | }\r | |
| 86 | \r | |
| ef42ef7e AB |
87 | VOID\r |
| 88 | EFIAPI\r | |
| 89 | ArmGenericTimerSetTimerVal (\r | |
| 2b16a4fb | 90 | IN UINTN Value\r |
| ef42ef7e AB |
91 | )\r |
| 92 | {\r | |
| 93 | ArmWriteCntvTval (Value);\r | |
| 94 | }\r | |
| 95 | \r | |
| 96 | UINT64\r | |
| 97 | EFIAPI\r | |
| 98 | ArmGenericTimerGetSystemCount (\r | |
| 99 | VOID\r | |
| 100 | )\r | |
| 101 | {\r | |
| 102 | return ArmReadCntvCt ();\r | |
| 103 | }\r | |
| 104 | \r | |
| 105 | UINTN\r | |
| 106 | EFIAPI\r | |
| 107 | ArmGenericTimerGetTimerCtrlReg (\r | |
| 108 | VOID\r | |
| 109 | )\r | |
| 110 | {\r | |
| 111 | return ArmReadCntvCtl ();\r | |
| 112 | }\r | |
| 113 | \r | |
| 114 | VOID\r | |
| 115 | EFIAPI\r | |
| 116 | ArmGenericTimerSetTimerCtrlReg (\r | |
| 2b16a4fb | 117 | UINTN Value\r |
| ef42ef7e AB |
118 | )\r |
| 119 | {\r | |
| 120 | ArmWriteCntvCtl (Value);\r | |
| 121 | }\r | |
| 122 | \r | |
| 123 | UINT64\r | |
| 124 | EFIAPI\r | |
| 125 | ArmGenericTimerGetCompareVal (\r | |
| 126 | VOID\r | |
| 127 | )\r | |
| 128 | {\r | |
| 129 | return ArmReadCntvCval ();\r | |
| 130 | }\r | |
| 131 | \r | |
| 132 | VOID\r | |
| 133 | EFIAPI\r | |
| 134 | ArmGenericTimerSetCompareVal (\r | |
| 2b16a4fb | 135 | IN UINT64 Value\r |
| ef42ef7e AB |
136 | )\r |
| 137 | {\r | |
| 138 | ArmWriteCntvCval (Value);\r | |
| 139 | }\r |