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9595e3cd LE |
1 | /** @file\r |
2 | Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation\r | |
3 | \r | |
4 | Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>\r | |
5 | This program and the accompanying materials are\r | |
6 | licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
d1c561f9 | 13 | **/\r |
9595e3cd LE |
14 | \r |
15 | #include "PciHostBridge.h"\r | |
16 | \r | |
17 | //\r | |
18 | // Hard code: Root Bridge Number within the host bridge\r | |
19 | // Root Bridge's attribute\r | |
20 | // Root Bridge's device path\r | |
21 | // Root Bridge's resource aperture\r | |
22 | //\r | |
23 | UINTN RootBridgeNumber[1] = { 1 };\r | |
24 | \r | |
25 | UINT64 RootBridgeAttribute[1][1] = { { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } };\r | |
26 | \r | |
27 | EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] = {\r | |
28 | {\r | |
29 | {\r | |
30 | {\r | |
31 | {\r | |
32 | ACPI_DEVICE_PATH,\r | |
33 | ACPI_DP,\r | |
34 | {\r | |
35 | (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),\r | |
36 | (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)\r | |
37 | }\r | |
38 | },\r | |
39 | EISA_PNP_ID(0x0A03),\r | |
40 | 0\r | |
41 | },\r | |
d1c561f9 | 42 | \r |
9595e3cd LE |
43 | {\r |
44 | END_DEVICE_PATH_TYPE,\r | |
45 | END_ENTIRE_DEVICE_PATH_SUBTYPE,\r | |
46 | {\r | |
47 | END_DEVICE_PATH_LENGTH,\r | |
48 | 0\r | |
49 | }\r | |
50 | }\r | |
51 | }\r | |
52 | }\r | |
53 | };\r | |
54 | \r | |
aca7e8b6 | 55 | STATIC PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1];\r |
9595e3cd LE |
56 | \r |
57 | EFI_HANDLE mDriverImageHandle;\r | |
58 | \r | |
59 | PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {\r | |
60 | PCI_HOST_BRIDGE_SIGNATURE, // Signature\r | |
61 | NULL, // HostBridgeHandle\r | |
62 | 0, // RootBridgeNumber\r | |
63 | {NULL, NULL}, // Head\r | |
64 | FALSE, // ResourceSubiteed\r | |
65 | TRUE, // CanRestarted\r | |
66 | {\r | |
67 | NotifyPhase,\r | |
68 | GetNextRootBridge,\r | |
69 | GetAttributes,\r | |
70 | StartBusEnumeration,\r | |
71 | SetBusNumbers,\r | |
72 | SubmitResources,\r | |
73 | GetProposedResources,\r | |
74 | PreprocessController\r | |
75 | }\r | |
76 | };\r | |
77 | \r | |
78 | //\r | |
79 | // Implementation\r | |
80 | //\r | |
81 | \r | |
82 | /**\r | |
83 | Entry point of this driver\r | |
84 | \r | |
85 | @param ImageHandle Handle of driver image\r | |
86 | @param SystemTable Point to EFI_SYSTEM_TABLE\r | |
87 | \r | |
120a25c2 | 88 | @retval EFI_ABORTED PCI host bridge not present\r |
9595e3cd LE |
89 | @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource\r |
90 | @retval EFI_DEVICE_ERROR Can not install the protocol instance\r | |
91 | @retval EFI_SUCCESS Success to initialize the Pci host bridge.\r | |
92 | **/\r | |
93 | EFI_STATUS\r | |
94 | EFIAPI\r | |
95 | InitializePciHostBridge (\r | |
96 | IN EFI_HANDLE ImageHandle,\r | |
97 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
98 | )\r | |
99 | {\r | |
f9a8be42 | 100 | UINT64 MmioAttributes;\r |
9595e3cd LE |
101 | EFI_STATUS Status;\r |
102 | UINTN Loop1;\r | |
103 | UINTN Loop2;\r | |
104 | PCI_HOST_BRIDGE_INSTANCE *HostBridge;\r | |
105 | PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r | |
d1c561f9 | 106 | \r |
120a25c2 LE |
107 | if (PcdGet64 (PcdPciExpressBaseAddress) == 0) {\r |
108 | DEBUG ((EFI_D_INFO, "%a: PCI host bridge not present\n", __FUNCTION__));\r | |
109 | return EFI_ABORTED;\r | |
110 | }\r | |
111 | \r | |
9595e3cd | 112 | mDriverImageHandle = ImageHandle;\r |
d1c561f9 | 113 | \r |
aca7e8b6 LE |
114 | mResAperture[0][0].BusBase = PcdGet32 (PcdPciBusMin);\r |
115 | mResAperture[0][0].BusLimit = PcdGet32 (PcdPciBusMax);\r | |
116 | \r | |
117 | mResAperture[0][0].MemBase = PcdGet32 (PcdPciMmio32Base);\r | |
118 | mResAperture[0][0].MemLimit = (UINT64)PcdGet32 (PcdPciMmio32Base) +\r | |
119 | PcdGet32 (PcdPciMmio32Size) - 1;\r | |
120 | \r | |
121 | mResAperture[0][0].IoBase = PcdGet64 (PcdPciIoBase);\r | |
122 | mResAperture[0][0].IoLimit = PcdGet64 (PcdPciIoBase) +\r | |
123 | PcdGet64 (PcdPciIoSize) - 1;\r | |
124 | mResAperture[0][0].IoTranslation = PcdGet64 (PcdPciIoTranslation);\r | |
125 | \r | |
807c26d3 LE |
126 | //\r |
127 | // Add IO and MMIO memory space, so that resources can be allocated in the\r | |
128 | // EfiPciHostBridgeAllocateResources phase.\r | |
129 | //\r | |
130 | Status = gDS->AddIoSpace (\r | |
131 | EfiGcdIoTypeIo,\r | |
132 | PcdGet64 (PcdPciIoBase),\r | |
133 | PcdGet64 (PcdPciIoSize)\r | |
134 | );\r | |
135 | ASSERT_EFI_ERROR (Status);\r | |
136 | \r | |
f9a8be42 LE |
137 | MmioAttributes = FeaturePcdGet (PcdKludgeMapPciMmioAsCached) ?\r |
138 | EFI_MEMORY_WB : EFI_MEMORY_UC;\r | |
139 | \r | |
807c26d3 LE |
140 | Status = gDS->AddMemorySpace (\r |
141 | EfiGcdMemoryTypeMemoryMappedIo,\r | |
142 | PcdGet32 (PcdPciMmio32Base),\r | |
143 | PcdGet32 (PcdPciMmio32Size),\r | |
f9a8be42 | 144 | MmioAttributes\r |
807c26d3 LE |
145 | );\r |
146 | if (EFI_ERROR (Status)) {\r | |
147 | DEBUG ((EFI_D_ERROR, "%a: AddMemorySpace: %r\n", __FUNCTION__, Status));\r | |
148 | return Status;\r | |
149 | }\r | |
150 | \r | |
f9a8be42 LE |
151 | Status = gDS->SetMemorySpaceAttributes (\r |
152 | PcdGet32 (PcdPciMmio32Base),\r | |
153 | PcdGet32 (PcdPciMmio32Size),\r | |
154 | MmioAttributes\r | |
155 | );\r | |
156 | if (EFI_ERROR (Status)) {\r | |
157 | DEBUG ((EFI_D_ERROR, "%a: SetMemorySpaceAttributes: %r\n", __FUNCTION__,\r | |
158 | Status));\r | |
159 | return Status;\r | |
160 | }\r | |
161 | \r | |
9595e3cd LE |
162 | //\r |
163 | // Create Host Bridge Device Handle\r | |
164 | //\r | |
165 | for (Loop1 = 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) {\r | |
166 | HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);\r | |
167 | if (HostBridge == NULL) {\r | |
168 | return EFI_OUT_OF_RESOURCES;\r | |
169 | }\r | |
d1c561f9 | 170 | \r |
9595e3cd LE |
171 | HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];\r |
172 | InitializeListHead (&HostBridge->Head);\r | |
173 | \r | |
174 | Status = gBS->InstallMultipleProtocolInterfaces (\r | |
d1c561f9 | 175 | &HostBridge->HostBridgeHandle,\r |
9595e3cd LE |
176 | &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,\r |
177 | NULL\r | |
178 | );\r | |
179 | if (EFI_ERROR (Status)) {\r | |
180 | FreePool (HostBridge);\r | |
181 | return EFI_DEVICE_ERROR;\r | |
182 | }\r | |
d1c561f9 | 183 | \r |
9595e3cd LE |
184 | //\r |
185 | // Create Root Bridge Device Handle in this Host Bridge\r | |
186 | //\r | |
d1c561f9 | 187 | \r |
9595e3cd LE |
188 | for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {\r |
189 | PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));\r | |
190 | if (PrivateData == NULL) {\r | |
191 | return EFI_OUT_OF_RESOURCES;\r | |
192 | }\r | |
193 | \r | |
194 | PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;\r | |
195 | PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];\r | |
196 | \r | |
197 | RootBridgeConstructor (\r | |
d1c561f9 OM |
198 | &PrivateData->Io,\r |
199 | HostBridge->HostBridgeHandle,\r | |
200 | RootBridgeAttribute[Loop1][Loop2],\r | |
9595e3cd LE |
201 | &mResAperture[Loop1][Loop2]\r |
202 | );\r | |
d1c561f9 | 203 | \r |
9595e3cd | 204 | Status = gBS->InstallMultipleProtocolInterfaces(\r |
d1c561f9 | 205 | &PrivateData->Handle,\r |
9595e3cd LE |
206 | &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,\r |
207 | &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,\r | |
208 | NULL\r | |
209 | );\r | |
210 | if (EFI_ERROR (Status)) {\r | |
211 | FreePool(PrivateData);\r | |
212 | return EFI_DEVICE_ERROR;\r | |
213 | }\r | |
d1c561f9 | 214 | \r |
9595e3cd LE |
215 | InsertTailList (&HostBridge->Head, &PrivateData->Link);\r |
216 | }\r | |
d1c561f9 | 217 | }\r |
9595e3cd LE |
218 | \r |
219 | return EFI_SUCCESS;\r | |
220 | }\r | |
221 | \r | |
222 | \r | |
223 | /**\r | |
224 | These are the notifications from the PCI bus driver that it is about to enter a certain\r | |
225 | phase of the PCI enumeration process.\r | |
226 | \r | |
227 | This member function can be used to notify the host bridge driver to perform specific actions,\r | |
228 | including any chipset-specific initialization, so that the chipset is ready to enter the next phase.\r | |
229 | Eight notification points are defined at this time. See belows:\r | |
230 | EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data\r | |
231 | structures. The PCI enumerator should issue this notification\r | |
232 | before starting a fresh enumeration process. Enumeration cannot\r | |
233 | be restarted after sending any other notification such as\r | |
234 | EfiPciHostBridgeBeginBusAllocation.\r | |
235 | EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is\r | |
236 | required here. This notification can be used to perform any\r | |
237 | chipset-specific programming.\r | |
238 | EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No\r | |
239 | specific action is required here. This notification can be used to\r | |
240 | perform any chipset-specific programming.\r | |
241 | EfiPciHostBridgeBeginResourceAllocation\r | |
242 | The resource allocation phase is about to begin. No specific\r | |
243 | action is required here. This notification can be used to perform\r | |
244 | any chipset-specific programming.\r | |
245 | EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI\r | |
246 | root bridges. These resource settings are returned on the next call to\r | |
247 | GetProposedResources(). Before calling NotifyPhase() with a Phase of\r | |
248 | EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible\r | |
249 | for gathering I/O and memory requests for\r | |
250 | all the PCI root bridges and submitting these requests using\r | |
251 | SubmitResources(). This function pads the resource amount\r | |
252 | to suit the root bridge hardware, takes care of dependencies between\r | |
253 | the PCI root bridges, and calls the Global Coherency Domain (GCD)\r | |
254 | with the allocation request. In the case of padding, the allocated range\r | |
255 | could be bigger than what was requested.\r | |
256 | EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated\r | |
257 | resources (proposed resources) for all the PCI root bridges. After the\r | |
258 | hardware is programmed, reassigning resources will not be supported.\r | |
259 | The bus settings are not affected.\r | |
260 | EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI\r | |
261 | root bridges and resets the I/O and memory apertures to their initial\r | |
262 | state. The bus settings are not affected. If the request to allocate\r | |
263 | resources fails, the PCI enumerator can use this notification to\r | |
264 | deallocate previous resources, adjust the requests, and retry\r | |
265 | allocation.\r | |
266 | EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is\r | |
267 | required here. This notification can be used to perform any chipsetspecific\r | |
268 | programming.\r | |
269 | \r | |
270 | @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
271 | @param[in] Phase The phase during enumeration\r | |
272 | \r | |
273 | @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error\r | |
274 | is valid for a Phase of EfiPciHostBridgeAllocateResources if\r | |
275 | SubmitResources() has not been called for one or more\r | |
276 | PCI root bridges before this call\r | |
277 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid\r | |
278 | for a Phase of EfiPciHostBridgeSetResources.\r | |
279 | @retval EFI_INVALID_PARAMETER Invalid phase parameter\r | |
280 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
281 | This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the\r | |
282 | previously submitted resource requests cannot be fulfilled or\r | |
283 | were only partially fulfilled.\r | |
284 | @retval EFI_SUCCESS The notification was accepted without any errors.\r | |
285 | \r | |
286 | **/\r | |
287 | EFI_STATUS\r | |
288 | EFIAPI\r | |
289 | NotifyPhase(\r | |
290 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
291 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase\r | |
292 | )\r | |
293 | {\r | |
294 | PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r | |
295 | PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r | |
296 | PCI_RESOURCE_TYPE Index;\r | |
297 | LIST_ENTRY *List;\r | |
298 | EFI_PHYSICAL_ADDRESS BaseAddress;\r | |
299 | UINT64 AddrLen;\r | |
300 | UINTN BitsOfAlignment;\r | |
301 | EFI_STATUS Status;\r | |
302 | EFI_STATUS ReturnStatus;\r | |
d1c561f9 | 303 | \r |
9595e3cd | 304 | HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r |
d1c561f9 | 305 | \r |
9595e3cd LE |
306 | switch (Phase) {\r |
307 | \r | |
308 | case EfiPciHostBridgeBeginEnumeration:\r | |
309 | if (HostBridgeInstance->CanRestarted) {\r | |
310 | //\r | |
d1c561f9 | 311 | // Reset the Each Root Bridge\r |
9595e3cd LE |
312 | //\r |
313 | List = HostBridgeInstance->Head.ForwardLink;\r | |
d1c561f9 | 314 | \r |
9595e3cd LE |
315 | while (List != &HostBridgeInstance->Head) {\r |
316 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
317 | for (Index = TypeIo; Index < TypeMax; Index++) {\r | |
318 | RootBridgeInstance->ResAllocNode[Index].Type = Index;\r | |
319 | RootBridgeInstance->ResAllocNode[Index].Base = 0;\r | |
320 | RootBridgeInstance->ResAllocNode[Index].Length = 0;\r | |
321 | RootBridgeInstance->ResAllocNode[Index].Status = ResNone;\r | |
322 | }\r | |
d1c561f9 | 323 | \r |
9595e3cd LE |
324 | List = List->ForwardLink;\r |
325 | }\r | |
d1c561f9 | 326 | \r |
9595e3cd LE |
327 | HostBridgeInstance->ResourceSubmited = FALSE;\r |
328 | HostBridgeInstance->CanRestarted = TRUE;\r | |
329 | } else {\r | |
330 | //\r | |
331 | // Can not restart\r | |
d1c561f9 | 332 | //\r |
9595e3cd | 333 | return EFI_NOT_READY;\r |
d1c561f9 | 334 | }\r |
9595e3cd LE |
335 | break;\r |
336 | \r | |
337 | case EfiPciHostBridgeEndEnumeration:\r | |
338 | break;\r | |
339 | \r | |
340 | case EfiPciHostBridgeBeginBusAllocation:\r | |
341 | //\r | |
342 | // No specific action is required here, can perform any chipset specific programing\r | |
343 | //\r | |
344 | HostBridgeInstance->CanRestarted = FALSE;\r | |
345 | break;\r | |
346 | \r | |
347 | case EfiPciHostBridgeEndBusAllocation:\r | |
348 | //\r | |
349 | // No specific action is required here, can perform any chipset specific programing\r | |
350 | //\r | |
351 | //HostBridgeInstance->CanRestarted = FALSE;\r | |
352 | break;\r | |
353 | \r | |
354 | case EfiPciHostBridgeBeginResourceAllocation:\r | |
355 | //\r | |
356 | // No specific action is required here, can perform any chipset specific programing\r | |
357 | //\r | |
358 | //HostBridgeInstance->CanRestarted = FALSE;\r | |
359 | break;\r | |
360 | \r | |
361 | case EfiPciHostBridgeAllocateResources:\r | |
362 | ReturnStatus = EFI_SUCCESS;\r | |
363 | if (HostBridgeInstance->ResourceSubmited) {\r | |
364 | //\r | |
d1c561f9 | 365 | // Take care of the resource dependencies between the root bridges\r |
9595e3cd LE |
366 | //\r |
367 | List = HostBridgeInstance->Head.ForwardLink;\r | |
368 | \r | |
369 | while (List != &HostBridgeInstance->Head) {\r | |
370 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
371 | for (Index = TypeIo; Index < TypeBus; Index++) {\r | |
372 | if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r | |
d1c561f9 | 373 | \r |
9595e3cd | 374 | AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r |
d1c561f9 | 375 | \r |
9595e3cd LE |
376 | //\r |
377 | // Get the number of '1' in Alignment.\r | |
378 | //\r | |
379 | BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);\r | |
d1c561f9 | 380 | \r |
9595e3cd LE |
381 | switch (Index) {\r |
382 | \r | |
d1c561f9 | 383 | case TypeIo:\r |
9595e3cd LE |
384 | //\r |
385 | // It is impossible for this chipset to align 0xFFFF for IO16\r | |
386 | // So clear it\r | |
387 | //\r | |
388 | if (BitsOfAlignment >= 16) {\r | |
389 | BitsOfAlignment = 0;\r | |
390 | }\r | |
d1c561f9 | 391 | \r |
ef8dba7d | 392 | BaseAddress = mResAperture[0][0].IoLimit;\r |
9595e3cd | 393 | Status = gDS->AllocateIoSpace (\r |
ef8dba7d | 394 | EfiGcdAllocateMaxAddressSearchTopDown,\r |
d1c561f9 | 395 | EfiGcdIoTypeIo,\r |
9595e3cd LE |
396 | BitsOfAlignment,\r |
397 | AddrLen,\r | |
398 | &BaseAddress,\r | |
399 | mDriverImageHandle,\r | |
400 | NULL\r | |
401 | );\r | |
d1c561f9 | 402 | \r |
9595e3cd LE |
403 | if (!EFI_ERROR (Status)) {\r |
404 | RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;\r | |
d1c561f9 | 405 | RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r |
9595e3cd | 406 | } else {\r |
d1c561f9 | 407 | ReturnStatus = Status;\r |
9595e3cd LE |
408 | if (Status != EFI_OUT_OF_RESOURCES) {\r |
409 | RootBridgeInstance->ResAllocNode[Index].Length = 0;\r | |
410 | }\r | |
411 | }\r | |
412 | \r | |
413 | break;\r | |
414 | \r | |
415 | \r | |
416 | case TypeMem32:\r | |
417 | //\r | |
418 | // It is impossible for this chipset to align 0xFFFFFFFF for Mem32\r | |
d1c561f9 | 419 | // So clear it\r |
9595e3cd | 420 | //\r |
d1c561f9 | 421 | \r |
9595e3cd LE |
422 | if (BitsOfAlignment >= 32) {\r |
423 | BitsOfAlignment = 0;\r | |
424 | }\r | |
d1c561f9 | 425 | \r |
b9a44dca | 426 | BaseAddress = mResAperture[0][0].MemLimit;\r |
9595e3cd | 427 | Status = gDS->AllocateMemorySpace (\r |
b9a44dca | 428 | EfiGcdAllocateMaxAddressSearchTopDown,\r |
d1c561f9 | 429 | EfiGcdMemoryTypeMemoryMappedIo,\r |
9595e3cd LE |
430 | BitsOfAlignment,\r |
431 | AddrLen,\r | |
432 | &BaseAddress,\r | |
433 | mDriverImageHandle,\r | |
434 | NULL\r | |
435 | );\r | |
d1c561f9 | 436 | \r |
9595e3cd LE |
437 | if (!EFI_ERROR (Status)) {\r |
438 | // We were able to allocate the PCI memory\r | |
439 | RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;\r | |
440 | RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;\r | |
d1c561f9 | 441 | \r |
9595e3cd LE |
442 | } else {\r |
443 | // Not able to allocate enough PCI memory\r | |
d1c561f9 OM |
444 | ReturnStatus = Status;\r |
445 | \r | |
9595e3cd LE |
446 | if (Status != EFI_OUT_OF_RESOURCES) {\r |
447 | RootBridgeInstance->ResAllocNode[Index].Length = 0;\r | |
d1c561f9 | 448 | }\r |
9595e3cd LE |
449 | ASSERT (FALSE);\r |
450 | }\r | |
451 | break;\r | |
d1c561f9 OM |
452 | \r |
453 | case TypePMem32:\r | |
454 | case TypeMem64:\r | |
9595e3cd LE |
455 | case TypePMem64:\r |
456 | ReturnStatus = EFI_ABORTED;\r | |
d1c561f9 | 457 | break;\r |
9595e3cd LE |
458 | default:\r |
459 | ASSERT (FALSE);\r | |
460 | break;\r | |
461 | }; //end switch\r | |
462 | }\r | |
463 | }\r | |
d1c561f9 | 464 | \r |
9595e3cd LE |
465 | List = List->ForwardLink;\r |
466 | }\r | |
d1c561f9 | 467 | \r |
9595e3cd | 468 | return ReturnStatus;\r |
9595e3cd LE |
469 | } else {\r |
470 | return EFI_NOT_READY;\r | |
471 | }\r | |
9595e3cd LE |
472 | \r |
473 | case EfiPciHostBridgeSetResources:\r | |
474 | break;\r | |
475 | \r | |
476 | case EfiPciHostBridgeFreeResources:\r | |
477 | ReturnStatus = EFI_SUCCESS;\r | |
478 | List = HostBridgeInstance->Head.ForwardLink;\r | |
479 | while (List != &HostBridgeInstance->Head) {\r | |
480 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
481 | for (Index = TypeIo; Index < TypeBus; Index++) {\r | |
482 | if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {\r | |
483 | AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r | |
484 | BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;\r | |
485 | switch (Index) {\r | |
486 | \r | |
d1c561f9 OM |
487 | case TypeIo:\r |
488 | Status = gDS->FreeIoSpace (BaseAddress, AddrLen);\r | |
9595e3cd LE |
489 | if (EFI_ERROR (Status)) {\r |
490 | ReturnStatus = Status;\r | |
491 | }\r | |
492 | break;\r | |
493 | \r | |
494 | case TypeMem32:\r | |
495 | Status = gDS->FreeMemorySpace (BaseAddress, AddrLen);\r | |
496 | if (EFI_ERROR (Status)) {\r | |
497 | ReturnStatus = Status;\r | |
498 | }\r | |
499 | break;\r | |
500 | \r | |
501 | case TypePMem32:\r | |
502 | break;\r | |
503 | \r | |
504 | case TypeMem64:\r | |
505 | break;\r | |
506 | \r | |
507 | case TypePMem64:\r | |
d1c561f9 | 508 | break;\r |
9595e3cd LE |
509 | \r |
510 | default:\r | |
511 | ASSERT (FALSE);\r | |
512 | break;\r | |
513 | \r | |
514 | }; //end switch\r | |
515 | RootBridgeInstance->ResAllocNode[Index].Type = Index;\r | |
516 | RootBridgeInstance->ResAllocNode[Index].Base = 0;\r | |
517 | RootBridgeInstance->ResAllocNode[Index].Length = 0;\r | |
518 | RootBridgeInstance->ResAllocNode[Index].Status = ResNone;\r | |
519 | }\r | |
520 | }\r | |
d1c561f9 | 521 | \r |
9595e3cd LE |
522 | List = List->ForwardLink;\r |
523 | }\r | |
d1c561f9 | 524 | \r |
9595e3cd | 525 | HostBridgeInstance->ResourceSubmited = FALSE;\r |
d1c561f9 | 526 | HostBridgeInstance->CanRestarted = TRUE;\r |
9595e3cd LE |
527 | return ReturnStatus;\r |
528 | \r | |
529 | case EfiPciHostBridgeEndResourceAllocation:\r | |
530 | HostBridgeInstance->CanRestarted = FALSE;\r | |
531 | break;\r | |
532 | \r | |
533 | default:\r | |
534 | return EFI_INVALID_PARAMETER;\r | |
535 | }\r | |
d1c561f9 OM |
536 | \r |
537 | return EFI_SUCCESS;\r | |
9595e3cd LE |
538 | }\r |
539 | \r | |
540 | /**\r | |
541 | Return the device handle of the next PCI root bridge that is associated with this Host Bridge.\r | |
542 | \r | |
543 | This function is called multiple times to retrieve the device handles of all the PCI root bridges that\r | |
544 | are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI\r | |
545 | root bridges. On each call, the handle that was returned by the previous call is passed into the\r | |
546 | interface, and on output the interface returns the device handle of the next PCI root bridge. The\r | |
547 | caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r | |
548 | for that root bridge. When there are no more PCI root bridges to report, the interface returns\r | |
549 | EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they\r | |
550 | are returned by this function.\r | |
551 | For D945 implementation, there is only one root bridge in PCI host bridge.\r | |
552 | \r | |
553 | @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
554 | @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.\r | |
d1c561f9 | 555 | \r |
9595e3cd | 556 | @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the\r |
d1c561f9 | 557 | specific Host bridge and return EFI_SUCCESS.\r |
9595e3cd LE |
558 | @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.\r |
559 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was\r | |
560 | returned on a previous call to GetNextRootBridge().\r | |
561 | **/\r | |
562 | EFI_STATUS\r | |
563 | EFIAPI\r | |
564 | GetNextRootBridge(\r | |
565 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
566 | IN OUT EFI_HANDLE *RootBridgeHandle\r | |
567 | )\r | |
568 | {\r | |
d1c561f9 OM |
569 | BOOLEAN NoRootBridge;\r |
570 | LIST_ENTRY *List;\r | |
9595e3cd LE |
571 | PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r |
572 | PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r | |
d1c561f9 | 573 | \r |
9595e3cd LE |
574 | NoRootBridge = TRUE;\r |
575 | HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r | |
576 | List = HostBridgeInstance->Head.ForwardLink;\r | |
d1c561f9 OM |
577 | \r |
578 | \r | |
9595e3cd LE |
579 | while (List != &HostBridgeInstance->Head) {\r |
580 | NoRootBridge = FALSE;\r | |
581 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
582 | if (*RootBridgeHandle == NULL) {\r | |
583 | //\r | |
584 | // Return the first Root Bridge Handle of the Host Bridge\r | |
585 | //\r | |
586 | *RootBridgeHandle = RootBridgeInstance->Handle;\r | |
587 | return EFI_SUCCESS;\r | |
588 | } else {\r | |
589 | if (*RootBridgeHandle == RootBridgeInstance->Handle) {\r | |
590 | //\r | |
591 | // Get next if have\r | |
592 | //\r | |
593 | List = List->ForwardLink;\r | |
594 | if (List!=&HostBridgeInstance->Head) {\r | |
595 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
596 | *RootBridgeHandle = RootBridgeInstance->Handle;\r | |
d1c561f9 | 597 | return EFI_SUCCESS;\r |
9595e3cd LE |
598 | } else {\r |
599 | return EFI_NOT_FOUND;\r | |
600 | }\r | |
601 | }\r | |
602 | }\r | |
d1c561f9 | 603 | \r |
9595e3cd LE |
604 | List = List->ForwardLink;\r |
605 | } //end while\r | |
d1c561f9 | 606 | \r |
9595e3cd LE |
607 | if (NoRootBridge) {\r |
608 | return EFI_NOT_FOUND;\r | |
609 | } else {\r | |
610 | return EFI_INVALID_PARAMETER;\r | |
611 | }\r | |
612 | }\r | |
613 | \r | |
614 | /**\r | |
615 | Returns the allocation attributes of a PCI root bridge.\r | |
616 | \r | |
617 | The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary\r | |
618 | from one PCI root bridge to another. These attributes are different from the decode-related\r | |
619 | attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The\r | |
620 | RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device\r | |
621 | handles of all the root bridges that are associated with this host bridge must be obtained by calling\r | |
622 | GetNextRootBridge(). The attributes are static in the sense that they do not change during or\r | |
623 | after the enumeration process. The hardware may provide mechanisms to change the attributes on\r | |
d1c561f9 | 624 | the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is\r |
9595e3cd LE |
625 | installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in\r |
626 | "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.\r | |
d1c561f9 OM |
627 | For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to\r |
628 | include requests for the prefetchable memory in the nonprefetchable memory pool and not request any\r | |
9595e3cd LE |
629 | prefetchable memory.\r |
630 | Attribute Description\r | |
631 | ------------------------------------ ----------------------------------------------------------------------\r | |
632 | EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate\r | |
633 | windows for nonprefetchable and prefetchable memory. A PCI bus\r | |
634 | driver needs to include requests for prefetchable memory in the\r | |
635 | nonprefetchable memory pool.\r | |
636 | \r | |
637 | EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory\r | |
638 | windows. If this bit is not set, the PCI bus driver needs to include\r | |
639 | requests for a 64-bit memory address in the corresponding 32-bit\r | |
640 | memory pool.\r | |
641 | \r | |
642 | @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL\r | |
643 | @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type\r | |
644 | EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r | |
645 | @param[out] Attributes The pointer to attribte of root bridge, it is output parameter\r | |
d1c561f9 | 646 | \r |
9595e3cd LE |
647 | @retval EFI_INVALID_PARAMETER Attribute pointer is NULL\r |
648 | @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.\r | |
649 | @retval EFI_SUCCESS Success to get attribute of interested root bridge.\r | |
650 | \r | |
651 | **/\r | |
652 | EFI_STATUS\r | |
653 | EFIAPI\r | |
654 | GetAttributes(\r | |
655 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
656 | IN EFI_HANDLE RootBridgeHandle,\r | |
657 | OUT UINT64 *Attributes\r | |
658 | )\r | |
659 | {\r | |
d1c561f9 | 660 | LIST_ENTRY *List;\r |
9595e3cd LE |
661 | PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r |
662 | PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r | |
d1c561f9 | 663 | \r |
9595e3cd LE |
664 | if (Attributes == NULL) {\r |
665 | return EFI_INVALID_PARAMETER;\r | |
666 | }\r | |
d1c561f9 | 667 | \r |
9595e3cd LE |
668 | HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r |
669 | List = HostBridgeInstance->Head.ForwardLink;\r | |
d1c561f9 | 670 | \r |
9595e3cd LE |
671 | while (List != &HostBridgeInstance->Head) {\r |
672 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
673 | if (RootBridgeHandle == RootBridgeInstance->Handle) {\r | |
674 | *Attributes = RootBridgeInstance->RootBridgeAttrib;\r | |
675 | return EFI_SUCCESS;\r | |
676 | }\r | |
677 | List = List->ForwardLink;\r | |
678 | }\r | |
d1c561f9 | 679 | \r |
9595e3cd | 680 | //\r |
d1c561f9 | 681 | // RootBridgeHandle is not an EFI_HANDLE\r |
9595e3cd LE |
682 | // that was returned on a previous call to GetNextRootBridge()\r |
683 | //\r | |
684 | return EFI_INVALID_PARAMETER;\r | |
685 | }\r | |
686 | \r | |
687 | /**\r | |
688 | Sets up the specified PCI root bridge for the bus enumeration process.\r | |
689 | \r | |
690 | This member function sets up the root bridge for bus enumeration and returns the PCI bus range\r | |
691 | over which the search should be performed in ACPI 2.0 resource descriptor format.\r | |
692 | \r | |
693 | @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.\r | |
694 | @param[in] RootBridgeHandle The PCI Root Bridge to be set up.\r | |
695 | @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.\r | |
d1c561f9 | 696 | \r |
9595e3cd LE |
697 | @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle\r |
698 | @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.\r | |
699 | @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.\r | |
700 | \r | |
701 | **/\r | |
702 | EFI_STATUS\r | |
703 | EFIAPI\r | |
704 | StartBusEnumeration(\r | |
705 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
706 | IN EFI_HANDLE RootBridgeHandle,\r | |
707 | OUT VOID **Configuration\r | |
708 | )\r | |
709 | {\r | |
d1c561f9 | 710 | LIST_ENTRY *List;\r |
9595e3cd LE |
711 | PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r |
712 | PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r | |
713 | VOID *Buffer;\r | |
714 | UINT8 *Temp;\r | |
715 | UINT64 BusStart;\r | |
716 | UINT64 BusEnd;\r | |
d1c561f9 | 717 | \r |
9595e3cd LE |
718 | HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r |
719 | List = HostBridgeInstance->Head.ForwardLink;\r | |
d1c561f9 | 720 | \r |
9595e3cd LE |
721 | while (List != &HostBridgeInstance->Head) {\r |
722 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
723 | if (RootBridgeHandle == RootBridgeInstance->Handle) {\r | |
724 | //\r | |
725 | // Set up the Root Bridge for Bus Enumeration\r | |
726 | //\r | |
727 | BusStart = RootBridgeInstance->BusBase;\r | |
728 | BusEnd = RootBridgeInstance->BusLimit;\r | |
729 | //\r | |
730 | // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR\r | |
731 | //\r | |
d1c561f9 | 732 | \r |
9595e3cd LE |
733 | Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));\r |
734 | if (Buffer == NULL) {\r | |
735 | return EFI_OUT_OF_RESOURCES;\r | |
736 | }\r | |
d1c561f9 | 737 | \r |
9595e3cd | 738 | Temp = (UINT8 *)Buffer;\r |
d1c561f9 | 739 | \r |
9595e3cd LE |
740 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;\r |
741 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;\r | |
742 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;\r | |
d1c561f9 | 743 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;\r |
9595e3cd LE |
744 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;\r |
745 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;\r | |
746 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;\r | |
747 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;\r | |
d1c561f9 | 748 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;\r |
9595e3cd | 749 | ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;\r |
d1c561f9 | 750 | \r |
9595e3cd | 751 | Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r |
d1c561f9 | 752 | ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r |
9595e3cd | 753 | ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r |
d1c561f9 OM |
754 | \r |
755 | *Configuration = Buffer;\r | |
9595e3cd LE |
756 | return EFI_SUCCESS;\r |
757 | }\r | |
758 | List = List->ForwardLink;\r | |
759 | }\r | |
d1c561f9 | 760 | \r |
9595e3cd LE |
761 | return EFI_INVALID_PARAMETER;\r |
762 | }\r | |
763 | \r | |
764 | /**\r | |
765 | Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.\r | |
766 | \r | |
767 | This member function programs the specified PCI root bridge to decode the bus range that is\r | |
768 | specified by the input parameter Configuration.\r | |
769 | The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.\r | |
770 | \r | |
771 | @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance\r | |
772 | @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed\r | |
773 | @param[in] Configuration The pointer to the PCI bus resource descriptor\r | |
d1c561f9 | 774 | \r |
9595e3cd LE |
775 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r |
776 | @retval EFI_INVALID_PARAMETER Configuration is NULL.\r | |
777 | @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r | |
778 | @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.\r | |
d1c561f9 | 779 | @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than\r |
9595e3cd LE |
780 | bus descriptors.\r |
781 | @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.\r | |
782 | @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.\r | |
783 | @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.\r | |
784 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r | |
785 | @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.\r | |
786 | \r | |
787 | **/\r | |
788 | EFI_STATUS\r | |
789 | EFIAPI\r | |
790 | SetBusNumbers(\r | |
791 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
792 | IN EFI_HANDLE RootBridgeHandle,\r | |
793 | IN VOID *Configuration\r | |
794 | )\r | |
795 | {\r | |
d1c561f9 | 796 | LIST_ENTRY *List;\r |
9595e3cd LE |
797 | PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r |
798 | PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r | |
799 | UINT8 *Ptr;\r | |
800 | UINTN BusStart;\r | |
801 | UINTN BusEnd;\r | |
802 | UINTN BusLen;\r | |
d1c561f9 | 803 | \r |
9595e3cd LE |
804 | if (Configuration == NULL) {\r |
805 | return EFI_INVALID_PARAMETER;\r | |
806 | }\r | |
d1c561f9 | 807 | \r |
9595e3cd | 808 | Ptr = Configuration;\r |
d1c561f9 | 809 | \r |
9595e3cd LE |
810 | //\r |
811 | // Check the Configuration is valid\r | |
812 | //\r | |
813 | if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r | |
814 | return EFI_INVALID_PARAMETER;\r | |
815 | }\r | |
d1c561f9 | 816 | \r |
9595e3cd LE |
817 | if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {\r |
818 | return EFI_INVALID_PARAMETER;\r | |
819 | }\r | |
820 | \r | |
821 | Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r | |
822 | if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {\r | |
823 | return EFI_INVALID_PARAMETER;\r | |
824 | }\r | |
d1c561f9 | 825 | \r |
9595e3cd LE |
826 | HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r |
827 | List = HostBridgeInstance->Head.ForwardLink;\r | |
d1c561f9 | 828 | \r |
9595e3cd | 829 | Ptr = Configuration;\r |
d1c561f9 | 830 | \r |
9595e3cd LE |
831 | while (List != &HostBridgeInstance->Head) {\r |
832 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
833 | if (RootBridgeHandle == RootBridgeInstance->Handle) {\r | |
834 | BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;\r | |
835 | BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;\r | |
836 | BusEnd = BusStart + BusLen - 1;\r | |
d1c561f9 | 837 | \r |
9595e3cd LE |
838 | if (BusStart > BusEnd) {\r |
839 | return EFI_INVALID_PARAMETER;\r | |
840 | }\r | |
d1c561f9 | 841 | \r |
9595e3cd LE |
842 | if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {\r |
843 | return EFI_INVALID_PARAMETER;\r | |
844 | }\r | |
d1c561f9 | 845 | \r |
9595e3cd LE |
846 | //\r |
847 | // Update the Bus Range\r | |
848 | //\r | |
849 | RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;\r | |
850 | RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;\r | |
851 | RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;\r | |
d1c561f9 | 852 | \r |
9595e3cd LE |
853 | //\r |
854 | // Program the Root Bridge Hardware\r | |
855 | //\r | |
d1c561f9 | 856 | \r |
9595e3cd LE |
857 | return EFI_SUCCESS;\r |
858 | }\r | |
d1c561f9 | 859 | \r |
9595e3cd LE |
860 | List = List->ForwardLink;\r |
861 | }\r | |
d1c561f9 | 862 | \r |
9595e3cd LE |
863 | return EFI_INVALID_PARAMETER;\r |
864 | }\r | |
865 | \r | |
866 | \r | |
867 | /**\r | |
868 | Submits the I/O and memory resource requirements for the specified PCI root bridge.\r | |
869 | \r | |
870 | This function is used to submit all the I/O and memory resources that are required by the specified\r | |
871 | PCI root bridge. The input parameter Configuration is used to specify the following:\r | |
872 | - The various types of resources that are required\r | |
873 | - The associated lengths in terms of ACPI 2.0 resource descriptor format\r | |
874 | \r | |
875 | @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r | |
876 | @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.\r | |
877 | @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.\r | |
d1c561f9 | 878 | \r |
9595e3cd LE |
879 | @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.\r |
880 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r | |
881 | @retval EFI_INVALID_PARAMETER Configuration is NULL.\r | |
882 | @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.\r | |
d1c561f9 OM |
883 | @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are\r |
884 | not supported by this PCI root bridge. This error will happen if the caller\r | |
9595e3cd LE |
885 | did not combine resources according to Attributes that were returned by\r |
886 | GetAllocAttributes().\r | |
887 | @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.\r | |
888 | @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.\r | |
889 | @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.\r | |
890 | \r | |
891 | **/\r | |
892 | EFI_STATUS\r | |
893 | EFIAPI\r | |
894 | SubmitResources(\r | |
895 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
896 | IN EFI_HANDLE RootBridgeHandle,\r | |
897 | IN VOID *Configuration\r | |
898 | )\r | |
899 | {\r | |
d1c561f9 | 900 | LIST_ENTRY *List;\r |
9595e3cd LE |
901 | PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r |
902 | PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r | |
903 | UINT8 *Temp;\r | |
904 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r | |
905 | UINT64 AddrLen;\r | |
906 | UINT64 Alignment;\r | |
d1c561f9 | 907 | \r |
9595e3cd LE |
908 | //\r |
909 | // Check the input parameter: Configuration\r | |
910 | //\r | |
911 | if (Configuration == NULL) {\r | |
912 | return EFI_INVALID_PARAMETER;\r | |
913 | }\r | |
d1c561f9 | 914 | \r |
9595e3cd LE |
915 | HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r |
916 | List = HostBridgeInstance->Head.ForwardLink;\r | |
d1c561f9 | 917 | \r |
9595e3cd | 918 | Temp = (UINT8 *)Configuration;\r |
d1c561f9 | 919 | while ( *Temp == 0x8A) {\r |
9595e3cd LE |
920 | Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;\r |
921 | }\r | |
922 | if (*Temp != 0x79) {\r | |
923 | return EFI_INVALID_PARAMETER;\r | |
924 | }\r | |
d1c561f9 | 925 | \r |
9595e3cd LE |
926 | Temp = (UINT8 *)Configuration;\r |
927 | while (List != &HostBridgeInstance->Head) {\r | |
928 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
929 | if (RootBridgeHandle == RootBridgeInstance->Handle) {\r | |
1a1d6376 LE |
930 | for (;\r |
931 | *Temp == 0x8A;\r | |
932 | Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR)\r | |
933 | ) {\r | |
9595e3cd LE |
934 | Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r |
935 | \r | |
936 | //\r | |
937 | // Check Address Length\r | |
938 | //\r | |
1a1d6376 LE |
939 | if (Ptr->AddrLen == 0) {\r |
940 | HostBridgeInstance->ResourceSubmited = TRUE;\r | |
941 | continue;\r | |
942 | }\r | |
9595e3cd LE |
943 | if (Ptr->AddrLen > 0xffffffff) {\r |
944 | return EFI_INVALID_PARAMETER;\r | |
945 | }\r | |
946 | \r | |
947 | //\r | |
948 | // Check address range alignment\r | |
949 | //\r | |
950 | if (Ptr->AddrRangeMax >= 0xffffffff || Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {\r | |
951 | return EFI_INVALID_PARAMETER;\r | |
952 | }\r | |
d1c561f9 | 953 | \r |
9595e3cd LE |
954 | switch (Ptr->ResType) {\r |
955 | \r | |
956 | case 0:\r | |
d1c561f9 | 957 | \r |
9595e3cd LE |
958 | //\r |
959 | // Check invalid Address Sapce Granularity\r | |
960 | //\r | |
961 | if (Ptr->AddrSpaceGranularity != 32) {\r | |
962 | return EFI_INVALID_PARAMETER;\r | |
963 | }\r | |
d1c561f9 | 964 | \r |
9595e3cd LE |
965 | //\r |
966 | // check the memory resource request is supported by PCI root bridge\r | |
967 | //\r | |
968 | if (RootBridgeInstance->RootBridgeAttrib == EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM &&\r | |
969 | Ptr->SpecificFlag == 0x06) {\r | |
970 | return EFI_INVALID_PARAMETER;\r | |
971 | }\r | |
d1c561f9 | 972 | \r |
9595e3cd LE |
973 | AddrLen = Ptr->AddrLen;\r |
974 | Alignment = Ptr->AddrRangeMax;\r | |
975 | if (Ptr->AddrSpaceGranularity == 32) {\r | |
976 | if (Ptr->SpecificFlag == 0x06) {\r | |
977 | //\r | |
978 | // Apply from GCD\r | |
979 | //\r | |
980 | RootBridgeInstance->ResAllocNode[TypePMem32].Status = ResSubmitted;\r | |
981 | } else {\r | |
982 | RootBridgeInstance->ResAllocNode[TypeMem32].Length = AddrLen;\r | |
983 | RootBridgeInstance->ResAllocNode[TypeMem32].Alignment = Alignment;\r | |
d1c561f9 | 984 | RootBridgeInstance->ResAllocNode[TypeMem32].Status = ResRequested;\r |
9595e3cd LE |
985 | HostBridgeInstance->ResourceSubmited = TRUE;\r |
986 | }\r | |
987 | }\r | |
988 | \r | |
989 | if (Ptr->AddrSpaceGranularity == 64) {\r | |
990 | if (Ptr->SpecificFlag == 0x06) {\r | |
991 | RootBridgeInstance->ResAllocNode[TypePMem64].Status = ResSubmitted;\r | |
992 | } else {\r | |
993 | RootBridgeInstance->ResAllocNode[TypeMem64].Status = ResSubmitted;\r | |
994 | }\r | |
995 | }\r | |
996 | break;\r | |
997 | \r | |
998 | case 1:\r | |
999 | AddrLen = (UINTN) Ptr->AddrLen;\r | |
1000 | Alignment = (UINTN) Ptr->AddrRangeMax;\r | |
1001 | RootBridgeInstance->ResAllocNode[TypeIo].Length = AddrLen;\r | |
1002 | RootBridgeInstance->ResAllocNode[TypeIo].Alignment = Alignment;\r | |
1003 | RootBridgeInstance->ResAllocNode[TypeIo].Status = ResRequested;\r | |
d1c561f9 | 1004 | HostBridgeInstance->ResourceSubmited = TRUE;\r |
9595e3cd LE |
1005 | break;\r |
1006 | \r | |
1007 | default:\r | |
1008 | break;\r | |
1009 | };\r | |
d1c561f9 OM |
1010 | }\r |
1011 | \r | |
9595e3cd LE |
1012 | return EFI_SUCCESS;\r |
1013 | }\r | |
d1c561f9 | 1014 | \r |
9595e3cd LE |
1015 | List = List->ForwardLink;\r |
1016 | }\r | |
d1c561f9 | 1017 | \r |
9595e3cd LE |
1018 | return EFI_INVALID_PARAMETER;\r |
1019 | }\r | |
1020 | \r | |
1021 | /**\r | |
1022 | Returns the proposed resource settings for the specified PCI root bridge.\r | |
1023 | \r | |
1024 | This member function returns the proposed resource settings for the specified PCI root bridge. The\r | |
1025 | proposed resource settings are prepared when NotifyPhase() is called with a Phase of\r | |
1026 | EfiPciHostBridgeAllocateResources. The output parameter Configuration\r | |
1027 | specifies the following:\r | |
1028 | - The various types of resources, excluding bus resources, that are allocated\r | |
1029 | - The associated lengths in terms of ACPI 2.0 resource descriptor format\r | |
1030 | \r | |
1031 | @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r | |
1032 | @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.\r | |
1033 | @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.\r | |
d1c561f9 | 1034 | \r |
9595e3cd LE |
1035 | @retval EFI_SUCCESS The requested parameters were returned.\r |
1036 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r | |
1037 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.\r | |
1038 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
1039 | \r | |
1040 | **/\r | |
1041 | EFI_STATUS\r | |
1042 | EFIAPI\r | |
1043 | GetProposedResources(\r | |
1044 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
1045 | IN EFI_HANDLE RootBridgeHandle,\r | |
1046 | OUT VOID **Configuration\r | |
1047 | )\r | |
1048 | {\r | |
d1c561f9 | 1049 | LIST_ENTRY *List;\r |
9595e3cd LE |
1050 | PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r |
1051 | PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r | |
1052 | UINTN Index;\r | |
d1c561f9 OM |
1053 | UINTN Number;\r |
1054 | VOID *Buffer;\r | |
9595e3cd LE |
1055 | UINT8 *Temp;\r |
1056 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;\r | |
1057 | UINT64 ResStatus;\r | |
d1c561f9 | 1058 | \r |
9595e3cd LE |
1059 | Buffer = NULL;\r |
1060 | Number = 0;\r | |
1061 | //\r | |
1062 | // Get the Host Bridge Instance from the resource allocation protocol\r | |
1063 | //\r | |
1064 | HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r | |
1065 | List = HostBridgeInstance->Head.ForwardLink;\r | |
d1c561f9 | 1066 | \r |
9595e3cd LE |
1067 | //\r |
1068 | // Enumerate the root bridges in this host bridge\r | |
1069 | //\r | |
1070 | while (List != &HostBridgeInstance->Head) {\r | |
1071 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
1072 | if (RootBridgeHandle == RootBridgeInstance->Handle) {\r | |
1073 | for (Index = 0; Index < TypeBus; Index ++) {\r | |
1074 | if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r | |
1075 | Number ++;\r | |
d1c561f9 | 1076 | }\r |
9595e3cd | 1077 | }\r |
d1c561f9 | 1078 | \r |
9595e3cd | 1079 | if (Number == 0) {\r |
e5ceb6c9 LE |
1080 | EFI_ACPI_END_TAG_DESCRIPTOR *End;\r |
1081 | \r | |
1082 | End = AllocateZeroPool (sizeof *End);\r | |
1083 | if (End == NULL) {\r | |
1084 | return EFI_OUT_OF_RESOURCES;\r | |
1085 | }\r | |
1086 | End->Desc = ACPI_END_TAG_DESCRIPTOR;\r | |
1087 | *Configuration = End;\r | |
1088 | return EFI_SUCCESS;\r | |
9595e3cd LE |
1089 | }\r |
1090 | \r | |
1091 | Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));\r | |
1092 | if (Buffer == NULL) {\r | |
1093 | return EFI_OUT_OF_RESOURCES;\r | |
1094 | }\r | |
d1c561f9 | 1095 | \r |
9595e3cd LE |
1096 | Temp = Buffer;\r |
1097 | for (Index = 0; Index < TypeBus; Index ++) {\r | |
1098 | if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {\r | |
1099 | Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;\r | |
1100 | ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;\r | |
d1c561f9 | 1101 | \r |
9595e3cd LE |
1102 | switch (Index) {\r |
1103 | \r | |
1104 | case TypeIo:\r | |
1105 | //\r | |
1106 | // Io\r | |
1107 | //\r | |
1108 | Ptr->Desc = 0x8A;\r | |
1109 | Ptr->Len = 0x2B;\r | |
1110 | Ptr->ResType = 1;\r | |
d1c561f9 | 1111 | Ptr->GenFlag = 0;\r |
9595e3cd LE |
1112 | Ptr->SpecificFlag = 0;\r |
1113 | Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r | |
1114 | Ptr->AddrRangeMax = 0;\r | |
1115 | Ptr->AddrTranslationOffset = \\r | |
1116 | (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r | |
1117 | Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r | |
1118 | break;\r | |
1119 | \r | |
1120 | case TypeMem32:\r | |
1121 | //\r | |
1122 | // Memory 32\r | |
d1c561f9 | 1123 | //\r |
9595e3cd LE |
1124 | Ptr->Desc = 0x8A;\r |
1125 | Ptr->Len = 0x2B;\r | |
1126 | Ptr->ResType = 0;\r | |
d1c561f9 | 1127 | Ptr->GenFlag = 0;\r |
9595e3cd LE |
1128 | Ptr->SpecificFlag = 0;\r |
1129 | Ptr->AddrSpaceGranularity = 32;\r | |
1130 | Ptr->AddrRangeMin = RootBridgeInstance->ResAllocNode[Index].Base;\r | |
1131 | Ptr->AddrRangeMax = 0;\r | |
1132 | Ptr->AddrTranslationOffset = \\r | |
d1c561f9 | 1133 | (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;\r |
9595e3cd LE |
1134 | Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;\r |
1135 | break;\r | |
1136 | \r | |
1137 | case TypePMem32:\r | |
1138 | //\r | |
1139 | // Prefetch memory 32\r | |
1140 | //\r | |
1141 | Ptr->Desc = 0x8A;\r | |
1142 | Ptr->Len = 0x2B;\r | |
1143 | Ptr->ResType = 0;\r | |
d1c561f9 | 1144 | Ptr->GenFlag = 0;\r |
9595e3cd LE |
1145 | Ptr->SpecificFlag = 6;\r |
1146 | Ptr->AddrSpaceGranularity = 32;\r | |
1147 | Ptr->AddrRangeMin = 0;\r | |
1148 | Ptr->AddrRangeMax = 0;\r | |
d1c561f9 | 1149 | Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r |
9595e3cd LE |
1150 | Ptr->AddrLen = 0;\r |
1151 | break;\r | |
1152 | \r | |
1153 | case TypeMem64:\r | |
1154 | //\r | |
1155 | // Memory 64\r | |
1156 | //\r | |
1157 | Ptr->Desc = 0x8A;\r | |
1158 | Ptr->Len = 0x2B;\r | |
1159 | Ptr->ResType = 0;\r | |
d1c561f9 | 1160 | Ptr->GenFlag = 0;\r |
9595e3cd LE |
1161 | Ptr->SpecificFlag = 0;\r |
1162 | Ptr->AddrSpaceGranularity = 64;\r | |
1163 | Ptr->AddrRangeMin = 0;\r | |
1164 | Ptr->AddrRangeMax = 0;\r | |
d1c561f9 | 1165 | Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r |
9595e3cd LE |
1166 | Ptr->AddrLen = 0;\r |
1167 | break;\r | |
1168 | \r | |
1169 | case TypePMem64:\r | |
1170 | //\r | |
1171 | // Prefetch memory 64\r | |
1172 | //\r | |
1173 | Ptr->Desc = 0x8A;\r | |
1174 | Ptr->Len = 0x2B;\r | |
1175 | Ptr->ResType = 0;\r | |
d1c561f9 | 1176 | Ptr->GenFlag = 0;\r |
9595e3cd LE |
1177 | Ptr->SpecificFlag = 6;\r |
1178 | Ptr->AddrSpaceGranularity = 64;\r | |
1179 | Ptr->AddrRangeMin = 0;\r | |
1180 | Ptr->AddrRangeMax = 0;\r | |
d1c561f9 | 1181 | Ptr->AddrTranslationOffset = EFI_RESOURCE_NONEXISTENT;\r |
9595e3cd LE |
1182 | Ptr->AddrLen = 0;\r |
1183 | break;\r | |
1184 | };\r | |
d1c561f9 | 1185 | \r |
9595e3cd | 1186 | Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);\r |
d1c561f9 | 1187 | }\r |
9595e3cd | 1188 | }\r |
d1c561f9 OM |
1189 | \r |
1190 | ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;\r | |
9595e3cd | 1191 | ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;\r |
d1c561f9 OM |
1192 | \r |
1193 | *Configuration = Buffer;\r | |
1194 | \r | |
9595e3cd LE |
1195 | return EFI_SUCCESS;\r |
1196 | }\r | |
d1c561f9 | 1197 | \r |
9595e3cd LE |
1198 | List = List->ForwardLink;\r |
1199 | }\r | |
d1c561f9 | 1200 | \r |
9595e3cd LE |
1201 | return EFI_INVALID_PARAMETER;\r |
1202 | }\r | |
1203 | \r | |
1204 | /**\r | |
1205 | Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various\r | |
1206 | stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual\r | |
1207 | PCI controllers before enumeration.\r | |
1208 | \r | |
1209 | This function is called during the PCI enumeration process. No specific action is expected from this\r | |
1210 | member function. It allows the host bridge driver to preinitialize individual PCI controllers before\r | |
1211 | enumeration.\r | |
1212 | \r | |
1213 | @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.\r | |
1214 | @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in\r | |
1215 | InstallProtocolInterface() in the UEFI 2.0 Specification.\r | |
1216 | @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the\r | |
1217 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI\r | |
1218 | configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for\r | |
1219 | the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.\r | |
d1c561f9 OM |
1220 | @param Phase The phase of the PCI device enumeration.\r |
1221 | \r | |
9595e3cd LE |
1222 | @retval EFI_SUCCESS The requested parameters were returned.\r |
1223 | @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.\r | |
1224 | @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in\r | |
1225 | EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.\r | |
1226 | @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should\r | |
1227 | not enumerate this device, including its child devices if it is a PCI-to-PCI\r | |
1228 | bridge.\r | |
1229 | \r | |
1230 | **/\r | |
1231 | EFI_STATUS\r | |
1232 | EFIAPI\r | |
1233 | PreprocessController (\r | |
1234 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,\r | |
1235 | IN EFI_HANDLE RootBridgeHandle,\r | |
1236 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,\r | |
1237 | IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase\r | |
1238 | )\r | |
1239 | {\r | |
1240 | PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;\r | |
1241 | PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;\r | |
d1c561f9 | 1242 | LIST_ENTRY *List;\r |
9595e3cd LE |
1243 | \r |
1244 | HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);\r | |
1245 | List = HostBridgeInstance->Head.ForwardLink;\r | |
1246 | \r | |
1247 | //\r | |
1248 | // Enumerate the root bridges in this host bridge\r | |
1249 | //\r | |
1250 | while (List != &HostBridgeInstance->Head) {\r | |
1251 | RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);\r | |
1252 | if (RootBridgeHandle == RootBridgeInstance->Handle) {\r | |
1253 | break;\r | |
1254 | }\r | |
1255 | List = List->ForwardLink;\r | |
1256 | }\r | |
1257 | if (List == &HostBridgeInstance->Head) {\r | |
1258 | return EFI_INVALID_PARAMETER;\r | |
1259 | }\r | |
1260 | \r | |
1261 | if ((UINT32)Phase > EfiPciBeforeResourceCollection) {\r | |
1262 | return EFI_INVALID_PARAMETER;\r | |
1263 | }\r | |
1264 | \r | |
1265 | return EFI_SUCCESS;\r | |
1266 | }\r |