[mirror_edk2.git] / ArmVirtPkg / PciHostBridgeDxe / PciRootBridgeIo.c

/** @file\r
  PCI Root Bridge Io Protocol implementation\r
\r
Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials are\r
licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PciHostBridge.h"\r
\r
typedef struct {\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR     SpaceDesp[TypeMax];\r
  EFI_ACPI_END_TAG_DESCRIPTOR           EndDesp;\r
} RESOURCE_CONFIGURATION;\r
\r
RESOURCE_CONFIGURATION Configuration = {\r
  {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},\r
  {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},\r
  {0x79, 0}\r
};\r
\r
//\r
// Protocol Member Function Prototypes\r
//\r
\r
/**\r
   Polls an address in memory mapped I/O space until an exit condition is met, or\r
   a timeout occurs.\r
\r
   This function provides a standard way to poll a PCI memory location. A PCI memory read\r
   operation is performed at the PCI memory address specified by Address for the width specified\r
   by Width. The result of this PCI memory read operation is stored in Result. This PCI memory\r
   read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &\r
   Mask) is equal to Value.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operations.\r
   @param[in]   Address   The base address of the memory operations. The caller is\r
                          responsible for aligning Address if required.\r
   @param[in]   Mask      Mask used for the polling criteria. Bytes above Width in Mask\r
                          are ignored. The bits in the bytes below Width which are zero in\r
                          Mask are ignored when polling the memory address.\r
   @param[in]   Value     The comparison value used for the polling exit criteria.\r
   @param[in]   Delay     The number of 100 ns units to poll. Note that timer available may\r
                          be of poorer granularity.\r
   @param[out]  Result    Pointer to the last value read from the memory location.\r
\r
   @retval EFI_SUCCESS            The last data returned from the access matched the poll exit criteria.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid.\r
   @retval EFI_INVALID_PARAMETER  Result is NULL.\r
   @retval EFI_TIMEOUT            Delay expired before a match occurred.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollMem (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  );\r
\r
/**\r
   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
   satisfied or after a defined duration.\r
\r
   This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is\r
   performed at the PCI I/O address specified by Address for the width specified by Width.\r
   The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is\r
   repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal\r
   to Value.\r
\r
   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in] Width     Signifies the width of the I/O operations.\r
   @param[in] Address   The base address of the I/O operations. The caller is responsible\r
                        for aligning Address if required.\r
   @param[in] Mask      Mask used for the polling criteria. Bytes above Width in Mask\r
                        are ignored. The bits in the bytes below Width which are zero in\r
                        Mask are ignored when polling the I/O address.\r
   @param[in] Value     The comparison value used for the polling exit criteria.\r
   @param[in] Delay     The number of 100 ns units to poll. Note that timer available may\r
                        be of poorer granularity.\r
   @param[out] Result   Pointer to the last value read from the memory location.\r
\r
   @retval EFI_SUCCESS            The last data returned from the access matched the poll exit criteria.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid.\r
   @retval EFI_INVALID_PARAMETER  Result is NULL.\r
   @retval EFI_TIMEOUT            Delay expired before a match occurred.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollIo (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  );\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
\r
   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
   registers in the PCI root bridge memory space.\r
   The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
   any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operation.\r
   @param[in]   Address   The base address of the memory operation. The caller is\r
                          responsible for aligning the Address if required.\r
   @param[in]   Count     The number of memory operations to perform. Bytes moved is\r
                          Width size * Count, starting at Address.\r
   @param[out]  Buffer    For read operations, the destination buffer to store the results. For\r
                          write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  OUT    VOID                                   *Buffer\r
  );\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
\r
   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
   registers in the PCI root bridge memory space.\r
   The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
   any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operation.\r
   @param[in]   Address   The base address of the memory operation. The caller is\r
                          responsible for aligning the Address if required.\r
   @param[in]   Count     The number of memory operations to perform. Bytes moved is\r
                          Width size * Count, starting at Address.\r
   @param[in]   Buffer    For read operations, the destination buffer to store the results. For\r
                          write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN     VOID                                   *Buffer\r
  );\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
\r
   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width       Signifies the width of the memory operations.\r
   @param[in]   UserAddress The base address of the I/O operation. The caller is responsible for\r
                            aligning the Address if required.\r
   @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                            size * Count, starting at Address.\r
   @param[out]  UserBuffer  For read operations, the destination buffer to store the results. For\r
                            write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER    Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 UserAddress,\r
  IN     UINTN                                  Count,\r
  OUT    VOID                                   *UserBuffer\r
  );\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
\r
   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width       Signifies the width of the memory operations.\r
   @param[in]   UserAddress The base address of the I/O operation. The caller is responsible for\r
                            aligning the Address if required.\r
   @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                            size * Count, starting at Address.\r
   @param[in]   UserBuffer  For read operations, the destination buffer to store the results. For\r
                            write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER    Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 UserAddress,\r
  IN     UINTN                                  Count,\r
  IN     VOID                                   *UserBuffer\r
  );\r
\r
/**\r
   Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
   root bridge memory space.\r
\r
   The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory\r
   space to another region of PCI root bridge memory space. This is especially useful for video scroll\r
   operation on a memory mapped video buffer.\r
   The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
   any alignment and memory width restrictions that a PCI root bridge on a platform might require.\r
\r
   @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
   @param[in] Width       Signifies the width of the memory operations.\r
   @param[in] DestAddress The destination address of the memory operation. The caller is\r
                          responsible for aligning the DestAddress if required.\r
   @param[in] SrcAddress  The source address of the memory operation. The caller is\r
                          responsible for aligning the SrcAddress if required.\r
   @param[in] Count       The number of memory operations to perform. Bytes moved is\r
                          Width size * Count, starting at DestAddress and SrcAddress.\r
\r
   @retval  EFI_SUCCESS             The data was copied from one memory region to another memory region.\r
   @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.\r
   @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoCopyMem (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 DestAddress,\r
  IN     UINT64                                 SrcAddress,\r
  IN     UINTN                                  Count\r
  );\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
\r
   The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
   registers for a PCI controller.\r
   The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
   any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
   require.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operations.\r
   @param[in]   Address   The address within the PCI configuration space for the PCI controller.\r
   @param[in]   Count     The number of PCI configuration operations to perform. Bytes\r
                          moved is Width size * Count, starting at Address.\r
   @param[out]  Buffer    For read operations, the destination buffer to store the results. For\r
                          write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  OUT    VOID                                   *Buffer\r
  );\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
\r
   The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
   registers for a PCI controller.\r
   The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
   any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
   require.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operations.\r
   @param[in]   Address   The address within the PCI configuration space for the PCI controller.\r
   @param[in]   Count     The number of PCI configuration operations to perform. Bytes\r
                          moved is Width size * Count, starting at Address.\r
   @param[in]   Buffer    For read operations, the destination buffer to store the results. For\r
                          write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN     VOID                                   *Buffer\r
  );\r
\r
/**\r
   Provides the PCI controller-specific addresses required to access system memory from a\r
   DMA bus master.\r
\r
   The Map() function provides the PCI controller specific addresses needed to access system\r
   memory. This function is used to map system memory for PCI bus master DMA accesses.\r
\r
   @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]       Operation       Indicates if the bus master is going to read or write to system memory.\r
   @param[in]       HostAddress     The system memory address to map to the PCI controller.\r
   @param[in, out]  NumberOfBytes   On input the number of bytes to map. On output the number of bytes that were mapped.\r
   @param[out]      DeviceAddress   The resulting map address for the bus master PCI controller to use\r
                                    to access the system memory's HostAddress.\r
   @param[out]      Mapping         The value to pass to Unmap() when the bus master DMA operation is complete.\r
\r
   @retval EFI_SUCCESS            The range was mapped for the returned NumberOfBytes.\r
   @retval EFI_INVALID_PARAMETER  Operation is invalid.\r
   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.\r
   @retval EFI_INVALID_PARAMETER  NumberOfBytes is NULL.\r
   @retval EFI_INVALID_PARAMETER  DeviceAddress is NULL.\r
   @retval EFI_INVALID_PARAMETER  Mapping is NULL.\r
   @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.\r
   @retval EFI_DEVICE_ERROR       The system hardware could not map the requested address.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMap (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                                       *HostAddress,\r
  IN OUT UINTN                                      *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
  OUT    VOID                                       **Mapping\r
  );\r
\r
/**\r
   Completes the Map() operation and releases any corresponding resources.\r
\r
   The Unmap() function completes the Map() operation and releases any corresponding resources.\r
   If the operation was an EfiPciOperationBusMasterWrite or\r
   EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.\r
   Any resources used for the mapping are freed.\r
\r
   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in] Mapping   The mapping value returned from Map().\r
\r
   @retval EFI_SUCCESS            The range was unmapped.\r
   @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().\r
   @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoUnmap (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  VOID                             *Mapping\r
  );\r
\r
/**\r
   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
   EfiPciOperationBusMasterCommonBuffer64 mapping.\r
\r
   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param Type        This parameter is not used and must be ignored.\r
   @param MemoryType  The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.\r
   @param Pages       The number of pages to allocate.\r
   @param HostAddress A pointer to store the base system memory address of the allocated range.\r
   @param Attributes  The requested bit mask of attributes for the allocated range. Only\r
                      the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,\r
                      and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.\r
\r
   @retval EFI_SUCCESS            The requested memory pages were allocated.\r
   @retval EFI_INVALID_PARAMETER  MemoryType is invalid.\r
   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.\r
   @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal attribute bits are\r
                                  MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
   @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoAllocateBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  EFI_ALLOCATE_TYPE                Type,\r
  IN  EFI_MEMORY_TYPE                  MemoryType,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             **HostAddress,\r
  IN  UINT64                           Attributes\r
  );\r
\r
/**\r
   Frees memory that was allocated with AllocateBuffer().\r
\r
   The FreeBuffer() function frees memory that was allocated with AllocateBuffer().\r
\r
   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param Pages       The number of pages to free.\r
   @param HostAddress The base system memory address of the allocated range.\r
\r
   @retval EFI_SUCCESS            The requested memory pages were freed.\r
   @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and Pages\r
                                  was not allocated with AllocateBuffer().\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFreeBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             *HostAddress\r
  );\r
\r
/**\r
   Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
\r
   The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system\r
   memory. Posted write transactions are generated by PCI bus masters when they perform write\r
   transactions to target addresses in system memory.\r
   This function does not flush posted write transactions from any PCI bridges. A PCI controller\r
   specific action must be taken to guarantee that the posted write transactions have been flushed from\r
   the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with\r
   a PCI read transaction from the PCI controller prior to calling Flush().\r
\r
   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
\r
   @retval EFI_SUCCESS        The PCI posted write transactions were flushed from the PCI host\r
                              bridge to system memory.\r
   @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed from the PCI\r
                              host bridge due to a hardware error.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFlush (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This\r
  );\r
\r
/**\r
   Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
   attributes that a PCI root bridge is currently using.\r
\r
   The GetAttributes() function returns the mask of attributes that this PCI root bridge supports\r
   and the mask of attributes that the PCI root bridge is currently using.\r
\r
   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param Supported   A pointer to the mask of attributes that this PCI root bridge\r
                      supports setting with SetAttributes().\r
   @param Attributes  A pointer to the mask of attributes that this PCI root bridge is\r
                      currently using.\r
\r
   @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI root\r
                                  bridge supports is returned in Supports. If Attributes is\r
                                  not NULL, then the attributes that the PCI root bridge is currently\r
                                  using is returned in Attributes.\r
   @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoGetAttributes (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  OUT UINT64                           *Supported,\r
  OUT UINT64                           *Attributes\r
  );\r
\r
/**\r
   Sets attributes for a resource range on a PCI root bridge.\r
\r
   The SetAttributes() function sets the attributes specified in Attributes for the PCI root\r
   bridge on the resource range specified by ResourceBase and ResourceLength. Since the\r
   granularity of setting these attributes may vary from resource type to resource type, and from\r
   platform to platform, the actual resource range and the one passed in by the caller may differ. As a\r
   result, this function may set the attributes specified by Attributes on a larger resource range\r
   than the caller requested. The actual range is returned in ResourceBase and\r
   ResourceLength. The caller is responsible for verifying that the actual range for which the\r
   attributes were set is acceptable.\r
\r
   @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]       Attributes      The mask of attributes to set. If the attribute bit\r
                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, or\r
                                    MEMORY_DISABLE is set, then the resource range is specified by\r
                                    ResourceBase and ResourceLength. If\r
                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
                                    MEMORY_DISABLE are not set, then ResourceBase and\r
                                    ResourceLength are ignored, and may be NULL.\r
   @param[in, out]  ResourceBase    A pointer to the base address of the resource range to be modified\r
                                    by the attributes specified by Attributes.\r
   @param[in, out]  ResourceLength  A pointer to the length of the resource range to be modified by the\r
                                    attributes specified by Attributes.\r
\r
   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.\r
   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
   @retval  EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoSetAttributes (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN     UINT64                           Attributes,\r
  IN OUT UINT64                           *ResourceBase,\r
  IN OUT UINT64                           *ResourceLength\r
  );\r
\r
/**\r
   Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0\r
   resource descriptors.\r
\r
   There are only two resource descriptor types from the ACPI Specification that may be used to\r
   describe the current resources allocated to a PCI root bridge. These are the QWORD Address\r
   Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The\r
   QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic\r
   or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD\r
   Address Space Descriptors followed by an End Tag.\r
\r
   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[out]  Resources   A pointer to the ACPI 2.0 resource descriptors that describe the\r
                            current configuration of this PCI root bridge. The storage for the\r
                            ACPI 2.0 resource descriptors is allocated by this function. The\r
                            caller must treat the return buffer as read-only data, and the buffer\r
                            must not be freed by the caller.\r
\r
   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.\r
   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
   @retval  EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoConfiguration (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  OUT    VOID                             **Resources\r
  );\r
\r
//\r
// Memory Controller Pci Root Bridge Io Module Variables\r
//\r
EFI_METRONOME_ARCH_PROTOCOL *mMetronome;\r
\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
UINT8 mInStride[] = {\r
  1, // EfiPciWidthUint8\r
  2, // EfiPciWidthUint16\r
  4, // EfiPciWidthUint32\r
  8, // EfiPciWidthUint64\r
  0, // EfiPciWidthFifoUint8\r
  0, // EfiPciWidthFifoUint16\r
  0, // EfiPciWidthFifoUint32\r
  0, // EfiPciWidthFifoUint64\r
  1, // EfiPciWidthFillUint8\r
  2, // EfiPciWidthFillUint16\r
  4, // EfiPciWidthFillUint32\r
  8  // EfiPciWidthFillUint64\r
};\r
\r
//\r
// Lookup table for increment values based on transfer widths\r
//\r
UINT8 mOutStride[] = {\r
  1, // EfiPciWidthUint8\r
  2, // EfiPciWidthUint16\r
  4, // EfiPciWidthUint32\r
  8, // EfiPciWidthUint64\r
  1, // EfiPciWidthFifoUint8\r
  2, // EfiPciWidthFifoUint16\r
  4, // EfiPciWidthFifoUint32\r
  8, // EfiPciWidthFifoUint64\r
  0, // EfiPciWidthFillUint8\r
  0, // EfiPciWidthFillUint16\r
  0, // EfiPciWidthFillUint32\r
  0  // EfiPciWidthFillUint64\r
};\r
\r
/**\r
\r
  Construct the Pci Root Bridge Io protocol\r
\r
  @param Protocol         Point to protocol instance\r
  @param HostBridgeHandle Handle of host bridge\r
  @param Attri            Attribute of host bridge\r
  @param ResAperture      ResourceAperture for host bridge\r
\r
  @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.\r
\r
**/\r
EFI_STATUS\r
RootBridgeConstructor (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL    *Protocol,\r
  IN EFI_HANDLE                         HostBridgeHandle,\r
  IN UINT64                             Attri,\r
  IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE  *ResAperture\r
  )\r
{\r
  EFI_STATUS                        Status;\r
  PCI_ROOT_BRIDGE_INSTANCE          *PrivateData;\r
  PCI_RESOURCE_TYPE                 Index;\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);\r
\r
  //\r
  // The host to PCI bridge. The host memory addresses are direct mapped to PCI\r
  // addresses, so there's no need to translate them. IO addresses need\r
  // translation however.\r
  //\r
  PrivateData->MemBase       = ResAperture->MemBase;\r
  PrivateData->IoBase        = ResAperture->IoBase;\r
  PrivateData->IoTranslation = ResAperture->IoTranslation;\r
\r
  //\r
  // The host bridge only supports 32bit addressing for memory\r
  // and standard IA32 16bit io\r
  //\r
  PrivateData->MemLimit = ResAperture->MemLimit;\r
  PrivateData->IoLimit  = ResAperture->IoLimit;\r
\r
  //\r
  // Bus Aperture for this Root Bridge (Possible Range)\r
  //\r
  PrivateData->BusBase  = ResAperture->BusBase;\r
  PrivateData->BusLimit = ResAperture->BusLimit;\r
\r
  //\r
  // Specific for this chipset\r
  //\r
  for (Index = TypeIo; Index < TypeMax; Index++) {\r
    PrivateData->ResAllocNode[Index].Type      = Index;\r
    PrivateData->ResAllocNode[Index].Base      = 0;\r
    PrivateData->ResAllocNode[Index].Length    = 0;\r
    PrivateData->ResAllocNode[Index].Status    = ResNone;\r
  }\r
\r
  PrivateData->RootBridgeAttrib = Attri;\r
\r
  PrivateData->Supports    = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \\r
                             EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \\r
                             EFI_PCI_ATTRIBUTE_VGA_MEMORY | \\r
                             EFI_PCI_ATTRIBUTE_VGA_IO_16  | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
  PrivateData->Attributes  = PrivateData->Supports;\r
\r
  Protocol->ParentHandle   = HostBridgeHandle;\r
\r
  Protocol->PollMem        = RootBridgeIoPollMem;\r
  Protocol->PollIo         = RootBridgeIoPollIo;\r
\r
  Protocol->Mem.Read       = RootBridgeIoMemRead;\r
  Protocol->Mem.Write      = RootBridgeIoMemWrite;\r
\r
  Protocol->Io.Read        = RootBridgeIoIoRead;\r
  Protocol->Io.Write       = RootBridgeIoIoWrite;\r
\r
  Protocol->CopyMem        = RootBridgeIoCopyMem;\r
\r
  Protocol->Pci.Read       = RootBridgeIoPciRead;\r
  Protocol->Pci.Write      = RootBridgeIoPciWrite;\r
\r
  Protocol->Map            = RootBridgeIoMap;\r
  Protocol->Unmap          = RootBridgeIoUnmap;\r
\r
  Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;\r
  Protocol->FreeBuffer     = RootBridgeIoFreeBuffer;\r
\r
  Protocol->Flush          = RootBridgeIoFlush;\r
\r
  Protocol->GetAttributes  = RootBridgeIoGetAttributes;\r
  Protocol->SetAttributes  = RootBridgeIoSetAttributes;\r
\r
  Protocol->Configuration  = RootBridgeIoConfiguration;\r
\r
  Protocol->SegmentNumber  = 0;\r
\r
  Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.\r
\r
  The I/O operations are carried out exactly as requested. The caller is responsible\r
  for satisfying any alignment and I/O width restrictions that a PI System on a\r
  platform might require. For example on some platforms, width requests of\r
  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r
  be handled by the driver.\r
\r
  @param[in] This           A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
  @param[in] OperationType  I/O operation type: IO/MMIO/PCI.\r
  @param[in] Width          Signifies the width of the I/O or Memory operation.\r
  @param[in] Address        The base address of the I/O operation.\r
  @param[in] Count          The number of I/O operations to perform. The number of\r
                            bytes moved is Width size * Count, starting at Address.\r
  @param[in] Buffer         For read operations, the destination buffer to store the results.\r
                            For write operations, the source buffer from which to write data.\r
\r
  @retval EFI_SUCCESS            The parameters for this request pass the checks.\r
  @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
  @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
  @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r
                                 and Count is not valid for this PI system.\r
\r
**/\r
EFI_STATUS\r
RootBridgeIoCheckParameter (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN OPERATION_TYPE                         OperationType,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                                 Address,\r
  IN UINTN                                  Count,\r
  IN VOID                                   *Buffer\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE                     *PrivateData;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  *PciRbAddr;\r
  UINT32                                       Stride;\r
  UINT64                                       Base;\r
  UINT64                                       Limit;\r
\r
  //\r
  // Check to see if Buffer is NULL\r
  //\r
  if (Buffer == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Check to see if Width is in the valid range\r
  //\r
  if ((UINT32)Width >= EfiPciWidthMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // For FIFO type, the target address won't increase during the access,\r
  // so treat Count as 1\r
  //\r
  if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {\r
    Count = 1;\r
  }\r
\r
  //\r
  // Check to see if Width is in the valid range for I/O Port operations\r
  //\r
  Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
  if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {\r
    ASSERT (FALSE);\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Check to see if Address is aligned\r
  //\r
  Stride = mInStride[Width];\r
  if ((Address & (UINT64)(Stride - 1)) != 0) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
\r
  //\r
  // Check to see if any address associated with this transfer exceeds the maximum\r
  // allowed address.  The maximum address implied by the parameters passed in is\r
  // Address + Size * Count.  If the following condition is met, then the transfer\r
  // is not supported.\r
  //\r
  //    Address + Size * Count > Limit + 1\r
  //\r
  // Since Limit can be the maximum integer value supported by the CPU and Count\r
  // can also be the maximum integer value supported by the CPU, this range\r
  // check must be adjusted to avoid all oveflow conditions.\r
  //\r
  if (OperationType == IoOperation) {\r
    Base = PrivateData->IoBase;\r
    Limit = PrivateData->IoLimit;\r
  } else if (OperationType == MemOperation) {\r
    Base = PrivateData->MemBase;\r
    Limit = PrivateData->MemLimit;\r
  } else {\r
    PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
    if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
\r
    if (PciRbAddr->ExtendedRegister != 0) {\r
      Address = PciRbAddr->ExtendedRegister;\r
    } else {\r
      Address = PciRbAddr->Register;\r
    }\r
    Base = 0;\r
    Limit = MAX_PCI_REG_ADDRESS;\r
  }\r
\r
  if (Limit < Address) {\r
      return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (Address < Base) {\r
      return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Base <= Address <= Limit\r
  //\r
  if (Address == 0 && Limit == MAX_UINT64) {\r
    //\r
    // 2^64 bytes are valid to transfer. With Stride == 1, that's simply\r
    // impossible to reach in Count; with Stride in {2, 4, 8}, we can divide\r
    // both 2^64 and Stride with 2.\r
    //\r
    if (Stride > 1 && Count > DivU64x32 (BIT63, Stride / 2)) {\r
      return EFI_UNSUPPORTED;\r
    }\r
  } else {\r
    //\r
    // (Limit - Address) does not wrap, and it is smaller than MAX_UINT64.\r
    //\r
    if (Count > DivU64x32 (Limit - Address + 1, Stride)) {\r
      return EFI_UNSUPPORTED;\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Internal help function for read and write memory space.\r
\r
   @param[in]   This          A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Write         Switch value for Read or Write.\r
   @param[in]   Width         Signifies the width of the memory operations.\r
   @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
   @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                              moved is Width size * Count, starting at Address.\r
   @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
                              write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
RootBridgeIoMemRW (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     BOOLEAN                                Write,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  )\r
{\r
  EFI_STATUS                             Status;\r
  UINT8                                  InStride;\r
  UINT8                                  OutStride;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  OperationWidth;\r
  UINT8                                  *Uint8Buffer;\r
\r
  Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  InStride = mInStride[Width];\r
  OutStride = mOutStride[Width];\r
  OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
    if (Write) {\r
      switch (OperationWidth) {\r
        case EfiPciWidthUint8:\r
          MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
          break;\r
        case EfiPciWidthUint16:\r
          MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
          break;\r
        case EfiPciWidthUint32:\r
          MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
          break;\r
        case EfiPciWidthUint64:\r
          MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
          break;\r
        default:\r
          //\r
          // The RootBridgeIoCheckParameter call above will ensure that this\r
          // path is not taken.\r
          //\r
          ASSERT (FALSE);\r
          break;\r
      }\r
    } else {\r
      switch (OperationWidth) {\r
        case EfiPciWidthUint8:\r
          *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
          break;\r
        case EfiPciWidthUint16:\r
          *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
          break;\r
        case EfiPciWidthUint32:\r
          *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
          break;\r
        case EfiPciWidthUint64:\r
          *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
          break;\r
        default:\r
          //\r
          // The RootBridgeIoCheckParameter call above will ensure that this\r
          // path is not taken.\r
          //\r
          ASSERT (FALSE);\r
          break;\r
      }\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Internal help function for read and write IO space.\r
\r
   @param[in]   This          A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Write         Switch value for Read or Write.\r
   @param[in]   Width         Signifies the width of the memory operations.\r
   @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
   @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                              moved is Width size * Count, starting at Address.\r
   @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
                              write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
RootBridgeIoIoRW (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     BOOLEAN                                Write,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN OUT VOID                                   *Buffer\r
  )\r
{\r
  EFI_STATUS                             Status;\r
  PCI_ROOT_BRIDGE_INSTANCE               *PrivateData;\r
  UINT8                                  InStride;\r
  UINT8                                  OutStride;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  OperationWidth;\r
  UINT8                                  *Uint8Buffer;\r
\r
  Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
  //\r
  // The addition below is performed in UINT64 modular arithmetic, in\r
  // accordance with the definition of PcdPciIoTranslation in\r
  // "ArmPlatformPkg.dec". Meaning, the addition below may in fact *decrease*\r
  // Address, implementing a negative offset translation.\r
  //\r
  Address += PrivateData->IoTranslation;\r
\r
  InStride = mInStride[Width];\r
  OutStride = mOutStride[Width];\r
  OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
\r
  for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
    if (Write) {\r
      switch (OperationWidth) {\r
        case EfiPciWidthUint8:\r
          MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
          break;\r
        case EfiPciWidthUint16:\r
          MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));\r
          break;\r
        case EfiPciWidthUint32:\r
          MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
          break;\r
        default:\r
          //\r
          // The RootBridgeIoCheckParameter call above will ensure that this\r
          // path is not taken.\r
          //\r
          ASSERT (FALSE);\r
          break;\r
      }\r
    } else {\r
      switch (OperationWidth) {\r
        case EfiPciWidthUint8:\r
          *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
          break;\r
        case EfiPciWidthUint16:\r
          *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);\r
          break;\r
        case EfiPciWidthUint32:\r
          *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);\r
          break;\r
        default:\r
          //\r
          // The RootBridgeIoCheckParameter call above will ensure that this\r
          // path is not taken.\r
          //\r
          ASSERT (FALSE);\r
          break;\r
      }\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Internal help function for read and write PCI configuration space.\r
\r
   @param[in]   This          A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Write         Switch value for Read or Write.\r
   @param[in]   Width         Signifies the width of the memory operations.\r
   @param[in]   UserAddress   The address within the PCI configuration space for the PCI controller.\r
   @param[in]   Count         The number of PCI configuration operations to perform. Bytes\r
                              moved is Width size * Count, starting at Address.\r
   @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For\r
                              write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
RootBridgeIoPciRW (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN BOOLEAN                                Write,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                                 Address,\r
  IN UINTN                                  Count,\r
  IN OUT VOID                               *Buffer\r
  )\r
{\r
  EFI_STATUS                                   Status;\r
  UINT8                                        InStride;\r
  UINT8                                        OutStride;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        OperationWidth;\r
  UINT8                                        *Uint8Buffer;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS  *PciRbAddr;\r
  UINTN                                        PcieRegAddr;\r
\r
  Status = RootBridgeIoCheckParameter (This, PciOperation, Width, Address, Count, Buffer);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;\r
\r
  PcieRegAddr = (UINTN) PCI_LIB_ADDRESS (\r
                          PciRbAddr->Bus,\r
                          PciRbAddr->Device,\r
                          PciRbAddr->Function,\r
                          (PciRbAddr->ExtendedRegister != 0) ? \\r
                            PciRbAddr->ExtendedRegister :\r
                            PciRbAddr->Register\r
                          );\r
\r
  InStride = mInStride[Width];\r
  OutStride = mOutStride[Width];\r
  OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
  for (Uint8Buffer = Buffer; Count > 0; PcieRegAddr += InStride, Uint8Buffer += OutStride, Count--) {\r
    if (Write) {\r
      switch (OperationWidth) {\r
        case EfiPciWidthUint8:\r
          PciWrite8 (PcieRegAddr, *Uint8Buffer);\r
          break;\r
        case EfiPciWidthUint16:\r
          PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer));\r
          break;\r
        case EfiPciWidthUint32:\r
          PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer));\r
          break;\r
        default:\r
          //\r
          // The RootBridgeIoCheckParameter call above will ensure that this\r
          // path is not taken.\r
          //\r
          ASSERT (FALSE);\r
          break;\r
      }\r
    } else {\r
      switch (OperationWidth) {\r
        case EfiPciWidthUint8:\r
          *Uint8Buffer = PciRead8 (PcieRegAddr);\r
          break;\r
        case EfiPciWidthUint16:\r
          *((UINT16 *)Uint8Buffer) = PciRead16 (PcieRegAddr);\r
          break;\r
        case EfiPciWidthUint32:\r
          *((UINT32 *)Uint8Buffer) = PciRead32 (PcieRegAddr);\r
          break;\r
        default:\r
          //\r
          // The RootBridgeIoCheckParameter call above will ensure that this\r
          // path is not taken.\r
          //\r
          ASSERT (FALSE);\r
          break;\r
      }\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Polls an address in memory mapped I/O space until an exit condition is met, or\r
   a timeout occurs.\r
\r
   This function provides a standard way to poll a PCI memory location. A PCI memory read\r
   operation is performed at the PCI memory address specified by Address for the width specified\r
   by Width. The result of this PCI memory read operation is stored in Result. This PCI memory\r
   read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &\r
   Mask) is equal to Value.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operations.\r
   @param[in]   Address   The base address of the memory operations. The caller is\r
                          responsible for aligning Address if required.\r
   @param[in]   Mask      Mask used for the polling criteria. Bytes above Width in Mask\r
                          are ignored. The bits in the bytes below Width which are zero in\r
                          Mask are ignored when polling the memory address.\r
   @param[in]   Value     The comparison value used for the polling exit criteria.\r
   @param[in]   Delay     The number of 100 ns units to poll. Note that timer available may\r
                          be of poorer granularity.\r
   @param[out]  Result    Pointer to the last value read from the memory location.\r
\r
   @retval EFI_SUCCESS            The last data returned from the access matched the poll exit criteria.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid.\r
   @retval EFI_INVALID_PARAMETER  Result is NULL.\r
   @retval EFI_TIMEOUT            Delay expired before a match occurred.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollMem (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT64      NumberOfTicks;\r
  UINT32      Remainder;\r
\r
  if (Result == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((UINT32)Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // No matter what, always do a single poll.\r
  //\r
  Status = This->Mem.Read (This, Width, Address, 1, Result);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  if ((*Result & Mask) == Value) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (Delay == 0) {\r
    return EFI_SUCCESS;\r
\r
  } else {\r
\r
    //\r
    // Determine the proper # of metronome ticks to wait for polling the\r
    // location.  The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
    // The "+1" to account for the possibility of the first tick being short\r
    // because we started in the middle of a tick.\r
    //\r
    // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome\r
    // protocol definition is updated.\r
    //\r
    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);\r
    if (Remainder != 0) {\r
      NumberOfTicks += 1;\r
    }\r
    NumberOfTicks += 1;\r
\r
    while (NumberOfTicks != 0) {\r
\r
      mMetronome->WaitForTick (mMetronome, 1);\r
\r
      Status = This->Mem.Read (This, Width, Address, 1, Result);\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
\r
      if ((*Result & Mask) == Value) {\r
        return EFI_SUCCESS;\r
      }\r
\r
      NumberOfTicks -= 1;\r
    }\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
   Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is\r
   satisfied or after a defined duration.\r
\r
   This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is\r
   performed at the PCI I/O address specified by Address for the width specified by Width.\r
   The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is\r
   repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal\r
   to Value.\r
\r
   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in] Width     Signifies the width of the I/O operations.\r
   @param[in] Address   The base address of the I/O operations. The caller is responsible\r
                        for aligning Address if required.\r
   @param[in] Mask      Mask used for the polling criteria. Bytes above Width in Mask\r
                        are ignored. The bits in the bytes below Width which are zero in\r
                        Mask are ignored when polling the I/O address.\r
   @param[in] Value     The comparison value used for the polling exit criteria.\r
   @param[in] Delay     The number of 100 ns units to poll. Note that timer available may\r
                        be of poorer granularity.\r
   @param[out] Result   Pointer to the last value read from the memory location.\r
\r
   @retval EFI_SUCCESS            The last data returned from the access matched the poll exit criteria.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid.\r
   @retval EFI_INVALID_PARAMETER  Result is NULL.\r
   @retval EFI_TIMEOUT            Delay expired before a match occurred.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPollIo (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN  UINT64                                 Address,\r
  IN  UINT64                                 Mask,\r
  IN  UINT64                                 Value,\r
  IN  UINT64                                 Delay,\r
  OUT UINT64                                 *Result\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT64      NumberOfTicks;\r
  UINT32      Remainder;\r
\r
  //\r
  // No matter what, always do a single poll.\r
  //\r
\r
  if (Result == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if ((UINT32)Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = This->Io.Read (This, Width, Address, 1, Result);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
  if ((*Result & Mask) == Value) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  if (Delay == 0) {\r
    return EFI_SUCCESS;\r
\r
  } else {\r
\r
    //\r
    // Determine the proper # of metronome ticks to wait for polling the\r
    // location.  The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1\r
    // The "+1" to account for the possibility of the first tick being short\r
    // because we started in the middle of a tick.\r
    //\r
    NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);\r
    if (Remainder != 0) {\r
      NumberOfTicks += 1;\r
    }\r
    NumberOfTicks += 1;\r
\r
    while (NumberOfTicks != 0) {\r
\r
      mMetronome->WaitForTick (mMetronome, 1);\r
\r
      Status = This->Io.Read (This, Width, Address, 1, Result);\r
      if (EFI_ERROR (Status)) {\r
        return Status;\r
      }\r
\r
      if ((*Result & Mask) == Value) {\r
        return EFI_SUCCESS;\r
      }\r
\r
      NumberOfTicks -= 1;\r
    }\r
  }\r
  return EFI_TIMEOUT;\r
}\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
\r
   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
   registers in the PCI root bridge memory space.\r
   The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
   any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operation.\r
   @param[in]   Address   The base address of the memory operation. The caller is\r
                          responsible for aligning the Address if required.\r
   @param[in]   Count     The number of memory operations to perform. Bytes moved is\r
                          Width size * Count, starting at Address.\r
   @param[out]  Buffer    For read operations, the destination buffer to store the results. For\r
                          write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  OUT    VOID                                   *Buffer\r
  )\r
{\r
  return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.\r
\r
   The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller\r
   registers in the PCI root bridge memory space.\r
   The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
   any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operation.\r
   @param[in]   Address   The base address of the memory operation. The caller is\r
                          responsible for aligning the Address if required.\r
   @param[in]   Count     The number of memory operations to perform. Bytes moved is\r
                          Width size * Count, starting at Address.\r
   @param[in]   Buffer    For read operations, the destination buffer to store the results. For\r
                          write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMemWrite (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  IN     VOID                                   *Buffer\r
  )\r
{\r
  return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
\r
   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width       Signifies the width of the memory operations.\r
   @param[in]   Address     The base address of the I/O operation. The caller is responsible for\r
                            aligning the Address if required.\r
   @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                            size * Count, starting at Address.\r
   @param[out]  Buffer      For read operations, the destination buffer to store the results. For\r
                            write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER    Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoRead (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT64                                 Address,\r
  IN     UINTN                                  Count,\r
  OUT    VOID                                   *Buffer\r
  )\r
{\r
  return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.\r
\r
   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width       Signifies the width of the memory operations.\r
   @param[in]   Address     The base address of the I/O operation. The caller is responsible for\r
                            aligning the Address if required.\r
   @param[in]   Count       The number of I/O operations to perform. Bytes moved is Width\r
                            size * Count, starting at Address.\r
   @param[in]   Buffer       For read operations, the destination buffer to store the results. For\r
                            write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS              The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER    Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER    Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES     The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoIoWrite (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL         *This,\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH   Width,\r
  IN       UINT64                                  Address,\r
  IN       UINTN                                   Count,\r
  IN       VOID                                    *Buffer\r
  )\r
{\r
  return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
   Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI\r
   root bridge memory space.\r
\r
   The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory\r
   space to another region of PCI root bridge memory space. This is especially useful for video scroll\r
   operation on a memory mapped video buffer.\r
   The memory operations are carried out exactly as requested. The caller is responsible for satisfying\r
   any alignment and memory width restrictions that a PCI root bridge on a platform might require.\r
\r
   @param[in] This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.\r
   @param[in] Width       Signifies the width of the memory operations.\r
   @param[in] DestAddress The destination address of the memory operation. The caller is\r
                          responsible for aligning the DestAddress if required.\r
   @param[in] SrcAddress  The source address of the memory operation. The caller is\r
                          responsible for aligning the SrcAddress if required.\r
   @param[in] Count       The number of memory operations to perform. Bytes moved is\r
                          Width size * Count, starting at DestAddress and SrcAddress.\r
\r
   @retval  EFI_SUCCESS             The data was copied from one memory region to another memory region.\r
   @retval  EFI_INVALID_PARAMETER   Width is invalid for this PCI root bridge.\r
   @retval  EFI_OUT_OF_RESOURCES    The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoCopyMem (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL              *This,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH        Width,\r
  IN UINT64                                       DestAddress,\r
  IN UINT64                                       SrcAddress,\r
  IN UINTN                                        Count\r
  )\r
{\r
  EFI_STATUS  Status;\r
  BOOLEAN     Direction;\r
  UINTN       Stride;\r
  UINTN       Index;\r
  UINT64      Result;\r
\r
  if ((UINT32)Width > EfiPciWidthUint64) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  if (DestAddress == SrcAddress) {\r
    return EFI_SUCCESS;\r
  }\r
\r
  Stride = (UINTN)(1 << Width);\r
\r
  Direction = TRUE;\r
  if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {\r
    Direction   = FALSE;\r
    SrcAddress  = SrcAddress  + (Count-1) * Stride;\r
    DestAddress = DestAddress + (Count-1) * Stride;\r
  }\r
\r
  for (Index = 0;Index < Count;Index++) {\r
    Status = RootBridgeIoMemRead (\r
               This,\r
               Width,\r
               SrcAddress,\r
               1,\r
               &Result\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    Status = RootBridgeIoMemWrite (\r
               This,\r
               Width,\r
               DestAddress,\r
               1,\r
               &Result\r
               );\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
    if (Direction) {\r
      SrcAddress  += Stride;\r
      DestAddress += Stride;\r
    } else {\r
      SrcAddress  -= Stride;\r
      DestAddress -= Stride;\r
    }\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
\r
   The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
   registers for a PCI controller.\r
   The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
   any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
   require.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operations.\r
   @param[in]   Address   The address within the PCI configuration space for the PCI controller.\r
   @param[in]   Count     The number of PCI configuration operations to perform. Bytes\r
                          moved is Width size * Count, starting at Address.\r
   @param[out]  Buffer    For read operations, the destination buffer to store the results. For\r
                          write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciRead (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN       UINT64                                 Address,\r
  IN       UINTN                                  Count,\r
  OUT      VOID                                   *Buffer\r
  )\r
{\r
  return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
   Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.\r
\r
   The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration\r
   registers for a PCI controller.\r
   The PCI Configuration operations are carried out exactly as requested. The caller is responsible for\r
   any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might\r
   require.\r
\r
   @param[in]   This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]   Width     Signifies the width of the memory operations.\r
   @param[in]   Address   The address within the PCI configuration space for the PCI controller.\r
   @param[in]   Count     The number of PCI configuration operations to perform. Bytes\r
                          moved is Width size * Count, starting at Address.\r
   @param[in]   Buffer    For read operations, the destination buffer to store the results. For\r
                          write operations, the source buffer to write data from.\r
\r
   @retval EFI_SUCCESS            The data was read from or written to the PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PCI root bridge.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoPciWrite (\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN       EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN       UINT64                                 Address,\r
  IN       UINTN                                  Count,\r
  IN       VOID                                   *Buffer\r
  )\r
{\r
  return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer);\r
}\r
\r
/**\r
   Provides the PCI controller-specific addresses required to access system memory from a\r
   DMA bus master.\r
\r
   The Map() function provides the PCI controller specific addresses needed to access system\r
   memory. This function is used to map system memory for PCI bus master DMA accesses.\r
\r
   @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]       Operation       Indicates if the bus master is going to read or write to system memory.\r
   @param[in]       HostAddress     The system memory address to map to the PCI controller.\r
   @param[in, out]  NumberOfBytes   On input the number of bytes to map. On output the number of bytes that were mapped.\r
   @param[out]      DeviceAddress   The resulting map address for the bus master PCI controller to use\r
                                    to access the system memory's HostAddress.\r
   @param[out]      Mapping         The value to pass to Unmap() when the bus master DMA operation is complete.\r
\r
   @retval EFI_SUCCESS            The range was mapped for the returned NumberOfBytes.\r
   @retval EFI_INVALID_PARAMETER  Operation is invalid.\r
   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.\r
   @retval EFI_INVALID_PARAMETER  NumberOfBytes is NULL.\r
   @retval EFI_INVALID_PARAMETER  DeviceAddress is NULL.\r
   @retval EFI_INVALID_PARAMETER  Mapping is NULL.\r
   @retval EFI_UNSUPPORTED        The HostAddress cannot be mapped as a common buffer.\r
   @retval EFI_DEVICE_ERROR       The system hardware could not map the requested address.\r
   @retval EFI_OUT_OF_RESOURCES   The request could not be completed due to a lack of resources.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoMap (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL            *This,\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                                       *HostAddress,\r
  IN OUT UINTN                                      *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS                       *DeviceAddress,\r
  OUT    VOID                                       **Mapping\r
  )\r
{\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  PhysicalAddress;\r
  MAP_INFO              *MapInfo;\r
\r
  if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Initialize the return values to their defaults\r
  //\r
  *Mapping = NULL;\r
\r
  //\r
  // Make sure that Operation is valid\r
  //\r
  if ((UINT32)Operation >= EfiPciOperationMaximum) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Most PCAT like chipsets can not handle performing DMA above 4GB.\r
  // If any part of the DMA transfer being mapped is above 4GB, then\r
  // map the DMA transfer to a buffer below 4GB.\r
  //\r
  PhysicalAddress = (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress;\r
  if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) {\r
\r
    //\r
    // Common Buffer operations can not be remapped.  If the common buffer\r
    // if above 4GB, then it is not possible to generate a mapping, so return\r
    // an error.\r
    //\r
    if (Operation == EfiPciOperationBusMasterCommonBuffer || Operation == EfiPciOperationBusMasterCommonBuffer64) {\r
      return EFI_UNSUPPORTED;\r
    }\r
\r
    //\r
    // Allocate a MAP_INFO structure to remember the mapping when Unmap() is\r
    // called later.\r
    //\r
    Status = gBS->AllocatePool (\r
                    EfiBootServicesData,\r
                    sizeof(MAP_INFO),\r
                    (VOID **)&MapInfo\r
                    );\r
    if (EFI_ERROR (Status)) {\r
      *NumberOfBytes = 0;\r
      return Status;\r
    }\r
\r
    //\r
    // Return a pointer to the MAP_INFO structure in Mapping\r
    //\r
    *Mapping = MapInfo;\r
\r
    //\r
    // Initialize the MAP_INFO structure\r
    //\r
    MapInfo->Operation         = Operation;\r
    MapInfo->NumberOfBytes     = *NumberOfBytes;\r
    MapInfo->NumberOfPages     = EFI_SIZE_TO_PAGES(*NumberOfBytes);\r
    MapInfo->HostAddress       = PhysicalAddress;\r
    MapInfo->MappedHostAddress = 0x00000000ffffffff;\r
\r
    //\r
    // Allocate a buffer below 4GB to map the transfer to.\r
    //\r
    Status = gBS->AllocatePages (\r
                    AllocateMaxAddress,\r
                    EfiBootServicesData,\r
                    MapInfo->NumberOfPages,\r
                    &MapInfo->MappedHostAddress\r
                    );\r
    if (EFI_ERROR (Status)) {\r
      gBS->FreePool (MapInfo);\r
      *NumberOfBytes = 0;\r
      return Status;\r
    }\r
\r
    //\r
    // If this is a read operation from the Bus Master's point of view,\r
    // then copy the contents of the real buffer into the mapped buffer\r
    // so the Bus Master can read the contents of the real buffer.\r
    //\r
    if (Operation == EfiPciOperationBusMasterRead || Operation == EfiPciOperationBusMasterRead64) {\r
      CopyMem (\r
        (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
        (VOID *)(UINTN)MapInfo->HostAddress,\r
        MapInfo->NumberOfBytes\r
        );\r
    }\r
\r
    //\r
    // The DeviceAddress is the address of the maped buffer below 4GB\r
    //\r
    *DeviceAddress = MapInfo->MappedHostAddress;\r
  } else {\r
    //\r
    // The transfer is below 4GB, so the DeviceAddress is simply the HostAddress\r
    //\r
    *DeviceAddress = PhysicalAddress;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Completes the Map() operation and releases any corresponding resources.\r
\r
   The Unmap() function completes the Map() operation and releases any corresponding resources.\r
   If the operation was an EfiPciOperationBusMasterWrite or\r
   EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.\r
   Any resources used for the mapping are freed.\r
\r
   @param[in] This      A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in] Mapping   The mapping value returned from Map().\r
\r
   @retval EFI_SUCCESS            The range was unmapped.\r
   @retval EFI_INVALID_PARAMETER  Mapping is not a value that was returned by Map().\r
   @retval EFI_DEVICE_ERROR       The data was not committed to the target system memory.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoUnmap (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN VOID                             *Mapping\r
  )\r
{\r
  MAP_INFO    *MapInfo;\r
\r
  //\r
  // See if the Map() operation associated with this Unmap() required a mapping buffer.\r
  // If a mapping buffer was not required, then this function simply returns EFI_SUCCESS.\r
  //\r
  if (Mapping != NULL) {\r
    //\r
    // Get the MAP_INFO structure from Mapping\r
    //\r
    MapInfo = (MAP_INFO *)Mapping;\r
\r
    //\r
    // If this is a write operation from the Bus Master's point of view,\r
    // then copy the contents of the mapped buffer into the real buffer\r
    // so the processor can read the contents of the real buffer.\r
    //\r
    if (MapInfo->Operation == EfiPciOperationBusMasterWrite || MapInfo->Operation == EfiPciOperationBusMasterWrite64) {\r
      CopyMem (\r
        (VOID *)(UINTN)MapInfo->HostAddress,\r
        (VOID *)(UINTN)MapInfo->MappedHostAddress,\r
        MapInfo->NumberOfBytes\r
        );\r
    }\r
\r
    //\r
    // Free the mapped buffer and the MAP_INFO structure.\r
    //\r
    gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages);\r
    gBS->FreePool (Mapping);\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or\r
   EfiPciOperationBusMasterCommonBuffer64 mapping.\r
\r
   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param Type        This parameter is not used and must be ignored.\r
   @param MemoryType  The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.\r
   @param Pages       The number of pages to allocate.\r
   @param HostAddress A pointer to store the base system memory address of the allocated range.\r
   @param Attributes  The requested bit mask of attributes for the allocated range. Only\r
                      the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,\r
                      and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.\r
\r
   @retval EFI_SUCCESS            The requested memory pages were allocated.\r
   @retval EFI_INVALID_PARAMETER  MemoryType is invalid.\r
   @retval EFI_INVALID_PARAMETER  HostAddress is NULL.\r
   @retval EFI_UNSUPPORTED        Attributes is unsupported. The only legal attribute bits are\r
                                  MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.\r
   @retval EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoAllocateBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  EFI_ALLOCATE_TYPE                Type,\r
  IN  EFI_MEMORY_TYPE                  MemoryType,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             **HostAddress,\r
  IN  UINT64                           Attributes\r
  )\r
{\r
  EFI_STATUS            Status;\r
  EFI_PHYSICAL_ADDRESS  PhysicalAddress;\r
\r
  //\r
  // Validate Attributes\r
  //\r
  if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != 0) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Check for invalid inputs\r
  //\r
  if (HostAddress == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData\r
  //\r
  if (MemoryType != EfiBootServicesData && MemoryType != EfiRuntimeServicesData) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Limit allocations to memory below 4GB\r
  //\r
  PhysicalAddress = (EFI_PHYSICAL_ADDRESS)(0xffffffff);\r
\r
  Status = gBS->AllocatePages (AllocateMaxAddress, MemoryType, Pages, &PhysicalAddress);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  *HostAddress = (VOID *)(UINTN)PhysicalAddress;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Frees memory that was allocated with AllocateBuffer().\r
\r
   The FreeBuffer() function frees memory that was allocated with AllocateBuffer().\r
\r
   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param Pages       The number of pages to free.\r
   @param HostAddress The base system memory address of the allocated range.\r
\r
   @retval EFI_SUCCESS            The requested memory pages were freed.\r
   @retval EFI_INVALID_PARAMETER  The memory range specified by HostAddress and Pages\r
                                  was not allocated with AllocateBuffer().\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFreeBuffer (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN  UINTN                            Pages,\r
  OUT VOID                             *HostAddress\r
  )\r
{\r
  return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages);\r
}\r
\r
/**\r
   Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
\r
   The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system\r
   memory. Posted write transactions are generated by PCI bus masters when they perform write\r
   transactions to target addresses in system memory.\r
   This function does not flush posted write transactions from any PCI bridges. A PCI controller\r
   specific action must be taken to guarantee that the posted write transactions have been flushed from\r
   the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with\r
   a PCI read transaction from the PCI controller prior to calling Flush().\r
\r
   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
\r
   @retval EFI_SUCCESS        The PCI posted write transactions were flushed from the PCI host\r
                              bridge to system memory.\r
   @retval EFI_DEVICE_ERROR   The PCI posted write transactions were not flushed from the PCI\r
                              host bridge due to a hardware error.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoFlush (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *This\r
  )\r
{\r
  //\r
  // not supported yet\r
  //\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the\r
   attributes that a PCI root bridge is currently using.\r
\r
   The GetAttributes() function returns the mask of attributes that this PCI root bridge supports\r
   and the mask of attributes that the PCI root bridge is currently using.\r
\r
   @param This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param Supported   A pointer to the mask of attributes that this PCI root bridge\r
                      supports setting with SetAttributes().\r
   @param Attributes  A pointer to the mask of attributes that this PCI root bridge is\r
                      currently using.\r
\r
   @retval  EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI root\r
                                  bridge supports is returned in Supports. If Attributes is\r
                                  not NULL, then the attributes that the PCI root bridge is currently\r
                                  using is returned in Attributes.\r
   @retval  EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoGetAttributes (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  OUT UINT64                           *Supported,\r
  OUT UINT64                           *Attributes\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE *PrivateData;\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
  if (Attributes == NULL && Supported == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  //\r
  // Set the return value for Supported and Attributes\r
  //\r
  if (Supported != NULL) {\r
    *Supported  = PrivateData->Supports;\r
  }\r
\r
  if (Attributes != NULL) {\r
    *Attributes = PrivateData->Attributes;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Sets attributes for a resource range on a PCI root bridge.\r
\r
   The SetAttributes() function sets the attributes specified in Attributes for the PCI root\r
   bridge on the resource range specified by ResourceBase and ResourceLength. Since the\r
   granularity of setting these attributes may vary from resource type to resource type, and from\r
   platform to platform, the actual resource range and the one passed in by the caller may differ. As a\r
   result, this function may set the attributes specified by Attributes on a larger resource range\r
   than the caller requested. The actual range is returned in ResourceBase and\r
   ResourceLength. The caller is responsible for verifying that the actual range for which the\r
   attributes were set is acceptable.\r
\r
   @param[in]       This            A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[in]       Attributes      The mask of attributes to set. If the attribute bit\r
                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, or\r
                                    MEMORY_DISABLE is set, then the resource range is specified by\r
                                    ResourceBase and ResourceLength. If\r
                                    MEMORY_WRITE_COMBINE, MEMORY_CACHED, and\r
                                    MEMORY_DISABLE are not set, then ResourceBase and\r
                                    ResourceLength are ignored, and may be NULL.\r
   @param[in, out]  ResourceBase    A pointer to the base address of the resource range to be modified\r
                                    by the attributes specified by Attributes.\r
   @param[in, out]  ResourceLength  A pointer to the length of the resource range to be modified by the\r
                                    attributes specified by Attributes.\r
\r
   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.\r
   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
   @retval  EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoSetAttributes (\r
  IN     EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *This,\r
  IN     UINT64                           Attributes,\r
  IN OUT UINT64                           *ResourceBase,\r
  IN OUT UINT64                           *ResourceLength\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE            *PrivateData;\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);\r
\r
  if (Attributes != 0) {\r
    if ((Attributes & (~(PrivateData->Supports))) != 0) {\r
      return EFI_UNSUPPORTED;\r
    }\r
  }\r
\r
  //\r
  // This is a generic driver for a PC-AT class system.  It does not have any\r
  // chipset specific knowlegde, so none of the attributes can be set or\r
  // cleared.  Any attempt to set attribute that are already set will succeed,\r
  // and any attempt to set an attribute that is not supported will fail.\r
  //\r
  if (Attributes & (~PrivateData->Attributes)) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
   Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0\r
   resource descriptors.\r
\r
   There are only two resource descriptor types from the ACPI Specification that may be used to\r
   describe the current resources allocated to a PCI root bridge. These are the QWORD Address\r
   Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The\r
   QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic\r
   or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD\r
   Address Space Descriptors followed by an End Tag.\r
\r
   @param[in]   This        A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r
   @param[out]  Resources   A pointer to the ACPI 2.0 resource descriptors that describe the\r
                            current configuration of this PCI root bridge. The storage for the\r
                            ACPI 2.0 resource descriptors is allocated by this function. The\r
                            caller must treat the return buffer as read-only data, and the buffer\r
                            must not be freed by the caller.\r
\r
   @retval  EFI_SUCCESS     The current configuration of this PCI root bridge was returned in Resources.\r
   @retval  EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.\r
   @retval  EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
RootBridgeIoConfiguration (\r
  IN  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL     *This,\r
  OUT VOID                                **Resources\r
  )\r
{\r
  PCI_ROOT_BRIDGE_INSTANCE              *PrivateData;\r
  UINTN                                 Index;\r
\r
  PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);\r
\r
  for (Index = 0; Index < TypeMax; Index++) {\r
    if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {\r
      Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;\r
      Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;\r
      Configuration.SpaceDesp[Index].AddrLen      = PrivateData->ResAllocNode[Index].Length;\r
    }\r
  }\r
\r
  *Resources = &Configuration;\r
  return EFI_SUCCESS;\r
}\r
\r