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1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
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4 | \r |
| a1594be9 |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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6 | \r |
| 7 | **/\r |
| 8 | \r |
| 9 | #include <PiPei.h>\r |
| 10 | #include <Library/IoLib.h>\r |
| 11 | #include <Library/DebugLib.h>\r |
| 12 | #include <Omap3530/Omap3530.h>\r |
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13 | #include <BeagleBoard.h>\r |
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14 | \r |
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15 | #define NUM_PINS_SHARED 232\r |
| 16 | #define NUM_PINS_ABC 6\r |
| 17 | #define NUM_PINS_XM 12\r |
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18 | \r |
| efe5f1a2 |
19 | PAD_CONFIGURATION PadConfigurationTableShared[] = {\r |
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20 | //Pin, MuxMode, PullConfig, InputEnable\r |
| 21 | { SDRC_D0, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 22 | { SDRC_D1, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 23 | { SDRC_D2, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 24 | { SDRC_D3, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 25 | { SDRC_D4, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 26 | { SDRC_D5, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 27 | { SDRC_D6, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 28 | { SDRC_D7, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 29 | { SDRC_D8, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 30 | { SDRC_D9, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 31 | { SDRC_D10, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 32 | { SDRC_D11, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 33 | { SDRC_D12, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 34 | { SDRC_D13, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 35 | { SDRC_D14, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 36 | { SDRC_D15, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 37 | { SDRC_D16, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 38 | { SDRC_D17, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 39 | { SDRC_D18, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 40 | { SDRC_D19, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 41 | { SDRC_D20, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 42 | { SDRC_D21, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 43 | { SDRC_D22, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 44 | { SDRC_D23, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 45 | { SDRC_D24, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 46 | { SDRC_D25, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 47 | { SDRC_D26, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 48 | { SDRC_D27, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 49 | { SDRC_D28, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 50 | { SDRC_D29, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 51 | { SDRC_D30, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 52 | { SDRC_D31, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 53 | { SDRC_CLK, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 54 | { SDRC_DQS0, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 55 | { SDRC_CKE0, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 56 | { SDRC_CKE1, MUXMODE7, PULL_DISABLED, INPUT },\r |
| 57 | { SDRC_DQS1, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 58 | { SDRC_DQS2, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 59 | { SDRC_DQS3, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 60 | { GPMC_A1, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 61 | { GPMC_A2, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 62 | { GPMC_A3, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 63 | { GPMC_A4, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 64 | { GPMC_A5, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 65 | { GPMC_A6, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 66 | { GPMC_A7, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 67 | { GPMC_A8, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 68 | { GPMC_A9, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 69 | { GPMC_A10, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 70 | { GPMC_D0, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 71 | { GPMC_D1, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 72 | { GPMC_D2, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 73 | { GPMC_D3, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 74 | { GPMC_D4, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 75 | { GPMC_D5, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 76 | { GPMC_D6, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 77 | { GPMC_D7, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 78 | { GPMC_D8, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 79 | { GPMC_D9, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 80 | { GPMC_D10, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 81 | { GPMC_D11, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 82 | { GPMC_D12, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 83 | { GPMC_D13, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 84 | { GPMC_D14, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 85 | { GPMC_D15, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 86 | { GPMC_NCS0, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 87 | { GPMC_NCS1, MUXMODE0, PULL_UP_SELECTED, OUTPUT },\r |
| 88 | { GPMC_NCS2, MUXMODE0, PULL_UP_SELECTED, OUTPUT },\r |
| 89 | { GPMC_NCS3, MUXMODE0, PULL_UP_SELECTED, OUTPUT },\r |
| 90 | { GPMC_NCS4, MUXMODE0, PULL_UP_SELECTED, OUTPUT },\r |
| 91 | { GPMC_NCS5, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 92 | { GPMC_NCS6, MUXMODE1, PULL_DISABLED, INPUT },\r |
| 93 | { GPMC_NCS7, MUXMODE1, PULL_UP_SELECTED, INPUT },\r |
| 94 | { GPMC_CLK, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 95 | { GPMC_NADV_ALE, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 96 | { GPMC_NOE, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 97 | { GPMC_NWE, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 98 | { GPMC_NBE0_CLE, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 99 | { GPMC_NBE1, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 100 | { GPMC_NWP, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 101 | { GPMC_WAIT0, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 102 | { GPMC_WAIT1, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 103 | { GPMC_WAIT2, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 104 | { GPMC_WAIT3, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 105 | { DSS_PCLK, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 106 | { DSS_HSYNC, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 107 | { DSS_PSYNC, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 108 | { DSS_ACBIAS, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 109 | { DSS_DATA0, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 110 | { DSS_DATA1, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 111 | { DSS_DATA2, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 112 | { DSS_DATA3, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 113 | { DSS_DATA4, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 114 | { DSS_DATA5, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 115 | { DSS_DATA6, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 116 | { DSS_DATA7, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 117 | { DSS_DATA8, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 118 | { DSS_DATA9, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 119 | { DSS_DATA10, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 120 | { DSS_DATA11, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 121 | { DSS_DATA12, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 122 | { DSS_DATA13, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 123 | { DSS_DATA14, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 124 | { DSS_DATA15, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 125 | { DSS_DATA16, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 126 | { DSS_DATA17, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
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127 | { CAM_HS, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 128 | { CAM_VS, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 129 | { CAM_XCLKA, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 130 | { CAM_PCLK, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 131 | { CAM_FLD, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 132 | { CAM_D0, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 133 | { CAM_D1, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 134 | { CAM_D2, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 135 | { CAM_D3, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 136 | { CAM_D4, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 137 | { CAM_D5, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 138 | { CAM_D6, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 139 | { CAM_D7, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 140 | { CAM_D8, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 141 | { CAM_D9, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 142 | { CAM_D10, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 143 | { CAM_D11, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 144 | { CAM_XCLKB, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 145 | { CAM_WEN, MUXMODE4, PULL_DISABLED, INPUT },\r |
| 146 | { CAM_STROBE, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 147 | { CSI2_DX0, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 148 | { CSI2_DY0, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 149 | { CSI2_DX1, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 150 | { CSI2_DY1, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 151 | { MCBSP2_FSX, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 152 | { MCBSP2_CLKX, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 153 | { MCBSP2_DR, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 154 | { MCBSP2_DX, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 155 | { MMC1_CLK, MUXMODE0, PULL_UP_SELECTED, OUTPUT },\r |
| 156 | { MMC1_CMD, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 157 | { MMC1_DAT0, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 158 | { MMC1_DAT1, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 159 | { MMC1_DAT2, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 160 | { MMC1_DAT3, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 161 | { MMC1_DAT4, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 162 | { MMC1_DAT5, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 163 | { MMC1_DAT6, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 164 | { MMC1_DAT7, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 165 | { MMC2_CLK, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 166 | { MMC2_CMD, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 167 | { MMC2_DAT0, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 168 | { MMC2_DAT1, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 169 | { MMC2_DAT2, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 170 | { MMC2_DAT3, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 171 | { MMC2_DAT4, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 172 | { MMC2_DAT5, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 173 | { MMC2_DAT6, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 174 | { MMC2_DAT7, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 175 | { MCBSP3_DX, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 176 | { MCBSP3_DR, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 177 | { MCBSP3_CLKX, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 178 | { MCBSP3_FSX, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 179 | { UART2_CTS, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 180 | { UART2_RTS, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 181 | { UART2_TX, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 182 | { UART2_RX, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 183 | { UART1_TX, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 184 | { UART1_RTS, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 185 | { UART1_CTS, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 186 | { UART1_RX, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 187 | { MCBSP4_CLKX, MUXMODE1, PULL_DISABLED, INPUT },\r |
| 188 | { MCBSP4_DR, MUXMODE1, PULL_DISABLED, INPUT },\r |
| 189 | { MCBSP4_DX, MUXMODE1, PULL_DISABLED, INPUT },\r |
| 190 | { MCBSP4_FSX, MUXMODE1, PULL_DISABLED, INPUT },\r |
| 191 | { MCBSP1_CLKR, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 192 | { MCBSP1_FSR, MUXMODE4, PULL_UP_SELECTED, OUTPUT },\r |
| 193 | { MCBSP1_DX, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 194 | { MCBSP1_DR, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 195 | { MCBSP1_CLKS, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 196 | { MCBSP1_FSX, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 197 | { MCBSP1_CLKX, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 198 | { UART3_CTS_RCTX,MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 199 | { UART3_RTS_SD, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 200 | { UART3_RX_IRRX, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 201 | { UART3_TX_IRTX, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 202 | { HSUSB0_CLK, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 203 | { HSUSB0_STP, MUXMODE0, PULL_UP_SELECTED, OUTPUT },\r |
| 204 | { HSUSB0_DIR, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 205 | { HSUSB0_NXT, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 206 | { HSUSB0_DATA0, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 207 | { HSUSB0_DATA1, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 208 | { HSUSB0_DATA2, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 209 | { HSUSB0_DATA3, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 210 | { HSUSB0_DATA4, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 211 | { HSUSB0_DATA5, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 212 | { HSUSB0_DATA6, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 213 | { HSUSB0_DATA7, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 214 | { I2C1_SCL, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 215 | { I2C1_SDA, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 216 | { I2C2_SCL, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 217 | { I2C2_SDA, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 218 | { I2C3_SCL, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 219 | { I2C3_SDA, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| efe5f1a2 |
220 | { HDQ_SIO, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 7f21c4a2 |
221 | { MCSPI1_CLK, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 222 | { MCSPI1_SIMO, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 223 | { MCSPI1_SOMI, MUXMODE0, PULL_DISABLED, INPUT },\r |
| 224 | { MCSPI1_CS0, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 225 | { MCSPI1_CS1, MUXMODE0, PULL_UP_SELECTED, OUTPUT },\r |
| 226 | { MCSPI1_CS2, MUXMODE4, PULL_DISABLED, OUTPUT },\r |
| 227 | { MCSPI1_CS3, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 228 | { MCSPI2_CLK, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 229 | { MCSPI2_SIMO, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 230 | { MCSPI2_SOMI, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 231 | { MCSPI2_CS0, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 232 | { MCSPI2_CS1, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 233 | { SYS_NIRQ, MUXMODE0, PULL_UP_SELECTED, INPUT },\r |
| 234 | { SYS_CLKOUT2, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 235 | { ETK_CLK, MUXMODE3, PULL_UP_SELECTED, OUTPUT },\r |
| 236 | { ETK_CTL, MUXMODE3, PULL_UP_SELECTED, OUTPUT },\r |
| 237 | { ETK_D0, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 238 | { ETK_D1, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 239 | { ETK_D2, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 240 | { ETK_D3, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 241 | { ETK_D4, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 242 | { ETK_D5, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 243 | { ETK_D6, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 244 | { ETK_D7, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 245 | { ETK_D8, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 246 | { ETK_D9, MUXMODE4, PULL_UP_SELECTED, INPUT },\r |
| 247 | { ETK_D10, MUXMODE3, PULL_UP_SELECTED, OUTPUT },\r |
| 248 | { ETK_D11, MUXMODE3, PULL_UP_SELECTED, OUTPUT },\r |
| 249 | { ETK_D12, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 250 | { ETK_D13, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 251 | { ETK_D14, MUXMODE3, PULL_UP_SELECTED, INPUT },\r |
| 252 | { ETK_D15, MUXMODE3, PULL_UP_SELECTED, INPUT }\r |
| 253 | };\r |
| 254 | \r |
| efe5f1a2 |
255 | PAD_CONFIGURATION PadConfigurationTableAbc[] = {\r |
| 256 | { DSS_DATA18, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 257 | { DSS_DATA19, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 258 | { DSS_DATA20, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 259 | { DSS_DATA21, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 260 | { DSS_DATA22, MUXMODE0, PULL_DISABLED, OUTPUT },\r |
| 261 | { DSS_DATA23, MUXMODE0, PULL_DISABLED, OUTPUT }\r |
| 262 | };\r |
| 263 | \r |
| 264 | PAD_CONFIGURATION PadConfigurationTableXm[] = {\r |
| 265 | { DSS_DATA18, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 266 | { DSS_DATA19, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 267 | { DSS_DATA20, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 268 | { DSS_DATA21, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 269 | { DSS_DATA22, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 270 | { DSS_DATA23, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 271 | { SYS_BOOT0, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 272 | { SYS_BOOT1, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 273 | { SYS_BOOT3, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 274 | { SYS_BOOT4, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 275 | { SYS_BOOT5, MUXMODE3, PULL_DISABLED, OUTPUT },\r |
| 276 | { SYS_BOOT6, MUXMODE3, PULL_DISABLED, OUTPUT }\r |
| 277 | };\r |
| 278 | \r |
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279 | VOID\r |
| 280 | PadConfiguration (\r |
| efe5f1a2 |
281 | BEAGLEBOARD_REVISION Revision\r |
| 7f21c4a2 |
282 | )\r |
| 283 | {\r |
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284 | UINTN Index;\r |
| 285 | UINT16 PadConfiguration;\r |
| 286 | PAD_CONFIGURATION *BoardConfiguration;\r |
| 287 | UINTN NumPinsToConfigure;\r |
| 288 | \r |
| 289 | for (Index = 0; Index < NUM_PINS_SHARED; Index++) {\r |
| 290 | // Set up Pad configuration for particular pin.\r |
| 291 | PadConfiguration = (PadConfigurationTableShared[Index].MuxMode << MUXMODE_OFFSET);\r |
| 292 | PadConfiguration |= (PadConfigurationTableShared[Index].PullConfig << PULL_CONFIG_OFFSET);\r |
| 293 | PadConfiguration |= (PadConfigurationTableShared[Index].InputEnable << INPUTENABLE_OFFSET);\r |
| 294 | \r |
| 295 | // Configure the pin with specific Pad configuration.\r |
| 296 | MmioWrite16(PadConfigurationTableShared[Index].Pin, PadConfiguration);\r |
| 297 | }\r |
| 298 | \r |
| 299 | if (Revision == REVISION_XM) {\r |
| 300 | BoardConfiguration = PadConfigurationTableXm;\r |
| 301 | NumPinsToConfigure = NUM_PINS_XM;\r |
| 302 | } else {\r |
| 303 | BoardConfiguration = PadConfigurationTableAbc;\r |
| 304 | NumPinsToConfigure = NUM_PINS_ABC;\r |
| 305 | }\r |
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306 | \r |
| 307 | for (Index = 0; Index < NumPinsToConfigure; Index++) {\r |
| 308 | //Set up Pad configuration for particular pin.\r |
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309 | PadConfiguration = (BoardConfiguration[Index].MuxMode << MUXMODE_OFFSET);\r |
| 310 | PadConfiguration |= (BoardConfiguration[Index].PullConfig << PULL_CONFIG_OFFSET);\r |
| 311 | PadConfiguration |= (BoardConfiguration[Index].InputEnable << INPUTENABLE_OFFSET);\r |
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312 | \r |
| 313 | //Configure the pin with specific Pad configuration.\r |
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314 | MmioWrite16(BoardConfiguration[Index].Pin, PadConfiguration);\r |
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315 | }\r |
| 316 | }\r |
projects / mirror_edk2.git / blame