projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ef2b01e A |
1 | #------------------------------------------------------------------------------ \r |
| 2 | #\r | |
| 3 | # Copyright (c) 2008-2009 Apple Inc. All rights reserved.\r | |
| 4 | #\r | |
| 5 | # All rights reserved. This program and the accompanying materials\r | |
| 6 | # are licensed and made available under the terms and conditions of the BSD License\r | |
| 7 | # which accompanies this distribution. The full text of the license may be found at\r | |
| 8 | # http://opensource.org/licenses/bsd-license.php\r | |
| 9 | #\r | |
| 10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 12 | #\r | |
| 13 | #------------------------------------------------------------------------------\r | |
| 14 | \r | |
| 15 | #include <AsmMacroIoLib.h>\r | |
| 16 | #include <Library/PcdLib.h>\r | |
| 17 | \r | |
| 18 | .text\r | |
| 19 | .align 3\r | |
| 20 | \r | |
| 21 | .globl ASM_PFX(CEntryPoint)\r | |
| 22 | .globl ASM_PFX(_ModuleEntryPoint)\r | |
| 23 | \r | |
| 24 | ASM_PFX(_ModuleEntryPoint):\r | |
| 25 | \r | |
| 26 | //Disable L2 cache\r | |
| 27 | mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register\r | |
| 28 | bic r0, r0, #0x00000002 // disable L2 cache\r | |
| 29 | mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register\r | |
| 30 | \r | |
| 31 | //Enable Strict alignment checking & Instruction cache\r | |
| 32 | mrc p15, 0, r0, c1, c0, 0\r | |
| 33 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */\r | |
| 34 | bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */\r | |
| 35 | orr r0, r0, #0x00000002 /* set bit 1 (A) Align */\r | |
| 36 | orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */\r | |
| 37 | mcr p15, 0, r0, c1, c0, 0\r | |
| 97e9818a | 38 | \r |
| 2ef2b01e | 39 | // Set CPU vectors to start of DRAM\r |
| bff4e9ea | 40 | LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r |
| 2ef2b01e | 41 | mcr p15, 0, r0, c12, c0, 0\r |
| 4951b248 | 42 | isb // Sync changes to control registers\r |
| 43 | \r | |
| bff4e9ea | 44 | // Fill vector table with branchs to current pc (jmp $)\r |
| 45 | ldr r1, ShouldNeverGetHere\r | |
| 46 | movs r2, #0\r | |
| 47 | FillVectors:\r | |
| 48 | str r1, [r0, r2]\r | |
| 49 | adds r2, r2, #4\r | |
| 50 | cmp r2, #32\r | |
| 51 | bne FillVectors\r | |
| 52 | \r | |
| 53 | /* before we call C code, lets setup the stack pointer in internal RAM */\r | |
| 2ef2b01e A |
54 | stack_pointer_setup:\r |
| 55 | \r | |
| 56 | //\r | |
| 57 | // Set stack based on PCD values. Need to do it this way to make C code work \r | |
| 58 | // when it runs from FLASH. \r | |
| 59 | // \r | |
| 60 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */\r | |
| 61 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */\r | |
| 62 | add r4, r2, r3\r | |
| 63 | \r | |
| 2ef2b01e A |
64 | //Enter SVC mode and set up SVC stack pointer\r |
| 65 | mov r0,#0x13|0x80|0x40\r | |
| 66 | msr CPSR_c,r0\r | |
| 2ef2b01e A |
67 | mov r13,r4\r |
| 68 | \r | |
| 69 | // Call C entry point\r | |
| 753816a3 | 70 | LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) /* memory size arg1 */\r |
| 71 | LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) /* memory size arg0 */\r | |
| 97e9818a | 72 | blx ASM_PFX(CEntryPoint) /* Assume C code is thumb */\r |
| 2ef2b01e A |
73 | \r |
| 74 | ShouldNeverGetHere:\r | |
| 75 | /* _CEntryPoint should never return */\r | |
| 76 | b ShouldNeverGetHere\r | |
| 2ef2b01e | 77 | \r |