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CorebootModulePkg: Remove unused PCI non-enumeration drivers
[mirror_edk2.git] / CorebootPayloadPkg / Library / PciHostBridgeLib / PciHostBridgeSupport.c
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69787a9d
MM		 1/** @file\r
2 Scan the entire PCI bus for root bridges to support coreboot UEFI payload.\r
3\r
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
5\r
6 This program and the accompanying materials are licensed and made available\r
7 under the terms and conditions of the BSD License which accompanies this\r
8 distribution. The full text of the license may be found at\r
9 http://opensource.org/licenses/bsd-license.php.\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
12 WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14**/\r
15\r
16#include <PiDxe.h>\r
17#include <IndustryStandard/Pci.h>\r
18#include <Protocol/PciHostBridgeResourceAllocation.h>\r
19#include <Protocol/PciRootBridgeIo.h>\r
20#include <Library/BaseMemoryLib.h>\r
21#include <Library/DebugLib.h>\r
22#include <Library/MemoryAllocationLib.h>\r
23#include <Library/PciHostBridgeLib.h>\r
24#include <Library/PciLib.h>\r
25#include "PciHostBridge.h"\r
26\r
27/**\r
28 Adjust the collected PCI resource.\r
29\r
30 @param[in] Io IO aperture.\r
31\r
32 @param[in] Mem MMIO aperture.\r
33\r
34 @param[in] MemAbove4G MMIO aperture above 4G.\r
35\r
36 @param[in] PMem Prefetchable MMIO aperture.\r
37\r
38 @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
39**/\r
40VOID\r
41AdjustRootBridgeResource (\r
42 IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
43 IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
44 IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
45 IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
46 IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
47)\r
48{\r
49 UINT64 Mask;\r
50\r
51 //\r
52 // For now try to downgrade everything into MEM32 since\r
53 // - coreboot does not assign resource above 4GB\r
54 // - coreboot might allocate interleaved MEM32 and PMEM32 resource\r
55 // in some cases\r
56 //\r
57 if (PMem->Base < Mem->Base) {\r
58 Mem->Base = PMem->Base;\r
59 }\r
60\r
61 if (PMem->Limit > Mem->Limit) {\r
62 Mem->Limit = PMem->Limit;\r
63 }\r
64\r
65 PMem->Base = MAX_UINT64;\r
66 PMem->Limit = 0;\r
67\r
68 if (MemAbove4G->Base < 0x100000000ULL) {\r
69 if (MemAbove4G->Base < Mem->Base) {\r
70 Mem->Base = MemAbove4G->Base;\r
71 }\r
72 if (MemAbove4G->Limit > Mem->Limit) {\r
73 Mem->Limit = MemAbove4G->Limit;\r
74 }\r
75 MemAbove4G->Base = MAX_UINT64;\r
76 MemAbove4G->Limit = 0;\r
77 }\r
78\r
79 if (PMemAbove4G->Base < 0x100000000ULL) {\r
80 if (PMemAbove4G->Base < Mem->Base) {\r
81 Mem->Base = PMemAbove4G->Base;\r
82 }\r
83 if (PMemAbove4G->Limit > Mem->Limit) {\r
84 Mem->Limit = PMemAbove4G->Limit;\r
85 }\r
86 PMemAbove4G->Base = MAX_UINT64;\r
87 PMemAbove4G->Limit = 0;\r
88 }\r
89\r
90 //\r
91 // Align IO resource at 4K boundary\r
92 //\r
93 Mask = 0xFFFULL;\r
94 Io->Limit = (Io->Limit + Mask) & ~Mask;\r
95 if (Io->Base != MAX_UINT64) {\r
96 Io->Base &= ~Mask;\r
97 }\r
98\r
99 //\r
100 // Align MEM resource at 1MB boundary\r
101 //\r
102 Mask = 0xFFFFFULL;\r
103 Mem->Limit = (Mem->Limit + Mask) & ~Mask;\r
104 if (Mem->Base != MAX_UINT64) {\r
105 Mem->Base &= ~Mask;\r
106 }\r
107}\r
108\r
109/**\r
110 Probe a bar is existed or not.\r
111\r
112 @param[in] Address PCI address for the BAR.\r
113 @param[out] OriginalValue The original bar value returned.\r
114 @param[out] Value The probed bar value returned.\r
115**/\r
116STATIC\r
117VOID\r
118PcatPciRootBridgeBarExisted (\r
119 IN UINT64 Address,\r
120 OUT UINT32 *OriginalValue,\r
121 OUT UINT32 *Value\r
122)\r
123{\r
124 UINTN PciAddress;\r
125\r
126 PciAddress = (UINTN)Address;\r
127\r
128 //\r
129 // Preserve the original value\r
130 //\r
131 *OriginalValue = PciRead32 (PciAddress);\r
132\r
133 //\r
134 // Disable timer interrupt while the BAR is probed\r
135 //\r
136 DisableInterrupts ();\r
137\r
138 PciWrite32 (PciAddress, 0xFFFFFFFF);\r
139 *Value = PciRead32 (PciAddress);\r
140 PciWrite32 (PciAddress, *OriginalValue);\r
141\r
142 //\r
143 // Enable interrupt\r
144 //\r
145 EnableInterrupts ();\r
146}\r
147\r
148/**\r
149 Parse PCI bar and collect the assigned PCI resouce information.\r
150\r
151 @param[in] Command Supported attributes.\r
152\r
153 @param[in] Bus PCI bus number.\r
154\r
155 @param[in] Device PCI device number.\r
156\r
157 @param[in] Function PCI function number.\r
158\r
159 @param[in] BarOffsetBase PCI bar start offset.\r
160\r
161 @param[in] BarOffsetEnd PCI bar end offset.\r
162\r
163 @param[in] Io IO aperture.\r
164\r
165 @param[in] Mem MMIO aperture.\r
166\r
167 @param[in] MemAbove4G MMIO aperture above 4G.\r
168\r
169 @param[in] PMem Prefetchable MMIO aperture.\r
170\r
171 @param[in] PMemAbove4G Prefetchable MMIO aperture above 4G.\r
172**/\r
173STATIC\r
174VOID\r
175PcatPciRootBridgeParseBars (\r
176 IN UINT16 Command,\r
177 IN UINTN Bus,\r
178 IN UINTN Device,\r
179 IN UINTN Function,\r
180 IN UINTN BarOffsetBase,\r
181 IN UINTN BarOffsetEnd,\r
182 IN PCI_ROOT_BRIDGE_APERTURE *Io,\r
183 IN PCI_ROOT_BRIDGE_APERTURE *Mem,\r
184 IN PCI_ROOT_BRIDGE_APERTURE *MemAbove4G,\r
185 IN PCI_ROOT_BRIDGE_APERTURE *PMem,\r
186 IN PCI_ROOT_BRIDGE_APERTURE *PMemAbove4G\r
187\r
188)\r
189{\r
190 UINT32 OriginalValue;\r
191 UINT32 Value;\r
192 UINT32 OriginalUpperValue;\r
193 UINT32 UpperValue;\r
194 UINT64 Mask;\r
195 UINTN Offset;\r
196 UINT64 Base;\r
197 UINT64 Length;\r
198 UINT64 Limit;\r
199 PCI_ROOT_BRIDGE_APERTURE *MemAperture;\r
200\r
201 for (Offset = BarOffsetBase; Offset < BarOffsetEnd; Offset += sizeof (UINT32)) {\r
202 PcatPciRootBridgeBarExisted (\r
203 PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
204 &OriginalValue, &Value\r
205 );\r
206 if (Value == 0) {\r
207 continue;\r
208 }\r
209 if ((Value & BIT0) == BIT0) {\r
210 //\r
211 // IO Bar\r
212 //\r
213 if (Command & EFI_PCI_COMMAND_IO_SPACE) {\r
214 Mask = 0xfffffffc;\r
215 Base = OriginalValue & Mask;\r
216 Length = ((~(Value & Mask)) & Mask) + 0x04;\r
217 if (!(Value & 0xFFFF0000)) {\r
218 Length &= 0x0000FFFF;\r
219 }\r
220 Limit = Base + Length - 1;\r
221\r
222 if ((Base > 0) && (Base < Limit)) {\r
223 if (Io->Base > Base) {\r
224 Io->Base = Base;\r
225 }\r
226 if (Io->Limit < Limit) {\r
227 Io->Limit = Limit;\r
228 }\r
229 }\r
230 }\r
231 } else {\r
232 //\r
233 // Mem Bar\r
234 //\r
235 if (Command & EFI_PCI_COMMAND_MEMORY_SPACE) {\r
236\r
237 Mask = 0xfffffff0;\r
238 Base = OriginalValue & Mask;\r
239 Length = Value & Mask;\r
240\r
241 if ((Value & (BIT1 | BIT2)) == 0) {\r
242 //\r
243 // 32bit\r
244 //\r
245 Length = ((~Length) + 1) & 0xffffffff;\r
246\r
247 if ((Value & BIT3) == BIT3) {\r
248 MemAperture = PMem;\r
249 } else {\r
250 MemAperture = Mem;\r
251 }\r
252 } else {\r
253 //\r
254 // 64bit\r
255 //\r
256 Offset += 4;\r
257 PcatPciRootBridgeBarExisted (\r
258 PCI_LIB_ADDRESS (Bus, Device, Function, Offset),\r
259 &OriginalUpperValue,\r
260 &UpperValue\r
261 );\r
262\r
263 Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);\r
264 Length = Length | LShiftU64 ((UINT64) UpperValue, 32);\r
265 Length = (~Length) + 1;\r
266\r
267 if ((Value & BIT3) == BIT3) {\r
268 MemAperture = PMemAbove4G;\r
269 } else {\r
270 MemAperture = MemAbove4G;\r
271 }\r
272 }\r
273\r
274 Limit = Base + Length - 1;\r
275 if ((Base > 0) && (Base < Limit)) {\r
276 if (MemAperture->Base > Base) {\r
277 MemAperture->Base = Base;\r
278 }\r
279 if (MemAperture->Limit < Limit) {\r
280 MemAperture->Limit = Limit;\r
281 }\r
282 }\r
283 }\r
284 }\r
285 }\r
286}\r
287\r
288/**\r
289 Scan for all root bridges in platform.\r
290\r
291 @param[out] NumberOfRootBridges Number of root bridges detected\r
292\r
293 @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.\r
294**/\r
295PCI_ROOT_BRIDGE *\r
296ScanForRootBridges (\r
297 OUT UINTN *NumberOfRootBridges\r
298)\r
299{\r
300 UINTN PrimaryBus;\r
301 UINTN SubBus;\r
302 UINT8 Device;\r
303 UINT8 Function;\r
304 UINTN NumberOfDevices;\r
305 UINTN Address;\r
306 PCI_TYPE01 Pci;\r
307 UINT64 Attributes;\r
308 UINT64 Base;\r
309 UINT64 Limit;\r
310 UINT64 Value;\r
311 PCI_ROOT_BRIDGE_APERTURE Io, Mem, MemAbove4G, PMem, PMemAbove4G, *MemAperture;\r
312 PCI_ROOT_BRIDGE *RootBridges;\r
313 UINTN BarOffsetEnd;\r
314\r
315\r
316 *NumberOfRootBridges = 0;\r
317 RootBridges = NULL;\r
318\r
319 //\r
320 // After scanning all the PCI devices on the PCI root bridge's primary bus,\r
321 // update the Primary Bus Number for the next PCI root bridge to be this PCI\r
322 // root bridge's subordinate bus number + 1.\r
323 //\r
324 for (PrimaryBus = 0; PrimaryBus <= PCI_MAX_BUS; PrimaryBus = SubBus + 1) {\r
325 SubBus = PrimaryBus;\r
326 Attributes = 0;\r
327 Io.Base = Mem.Base = MemAbove4G.Base = PMem.Base = PMemAbove4G.Base = MAX_UINT64;\r
328 Io.Limit = Mem.Limit = MemAbove4G.Limit = PMem.Limit = PMemAbove4G.Limit = 0;\r
329 //\r
330 // Scan all the PCI devices on the primary bus of the PCI root bridge\r
331 //\r
332 for (Device = 0, NumberOfDevices = 0; Device <= PCI_MAX_DEVICE; Device++) {\r
333\r
334 for (Function = 0; Function <= PCI_MAX_FUNC; Function++) {\r
335\r
336 //\r
337 // Compute the PCI configuration address of the PCI device to probe\r
338 //\r
339 Address = PCI_LIB_ADDRESS (PrimaryBus, Device, Function, 0);\r
340\r
341 //\r
342 // Read the Vendor ID from the PCI Configuration Header\r
343 //\r
344 if (PciRead16 (Address) == MAX_UINT16) {\r
345 if (Function == 0) {\r
346 //\r
347 // If the PCI Configuration Read fails, or a PCI device does not\r
348 // exist, then skip this entire PCI device\r
349 //\r
350 break;\r
351 } else {\r
352 //\r
353 // If PCI function != 0, VendorId == 0xFFFF, we continue to search\r
354 // PCI function.\r
355 //\r
356 continue;\r
357 }\r
358 }\r
359\r
360 //\r
361 // Read the entire PCI Configuration Header\r
362 //\r
363 PciReadBuffer (Address, sizeof (Pci), &Pci);\r
364\r
365 //\r
366 // Increment the number of PCI device found on the primary bus of the\r
367 // PCI root bridge\r
368 //\r
369 NumberOfDevices++;\r
370\r
371 //\r
372 // Look for devices with the VGA Palette Snoop enabled in the COMMAND\r
373 // register of the PCI Config Header\r
374 //\r
375 if ((Pci.Hdr.Command & EFI_PCI_COMMAND_VGA_PALETTE_SNOOP) != 0) {\r
376 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
377 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
378 }\r
379\r
380 BarOffsetEnd = 0;\r
381\r
382 //\r
383 // PCI-PCI Bridge\r
384 //\r
385 if (IS_PCI_BRIDGE (&Pci)) {\r
386 //\r
387 // Get the Bus range that the PPB is decoding\r
388 //\r
389 if (Pci.Bridge.SubordinateBus > SubBus) {\r
390 //\r
391 // If the suborinate bus number of the PCI-PCI bridge is greater\r
392 // than the PCI root bridge's current subordinate bus number,\r
393 // then update the PCI root bridge's subordinate bus number\r
394 //\r
395 SubBus = Pci.Bridge.SubordinateBus;\r
396 }\r
397\r
398 //\r
399 // Get the I/O range that the PPB is decoding\r
400 //\r
401 Value = Pci.Bridge.IoBase & 0x0f;\r
402 Base = ((UINT32) Pci.Bridge.IoBase & 0xf0) << 8;\r
403 Limit = (((UINT32) Pci.Bridge.IoLimit & 0xf0) << 8) | 0x0fff;\r
404 if (Value == BIT0) {\r
405 Base |= ((UINT32) Pci.Bridge.IoBaseUpper16 << 16);\r
406 Limit |= ((UINT32) Pci.Bridge.IoLimitUpper16 << 16);\r
407 }\r
408 if ((Base > 0) && (Base < Limit)) {\r
409 if (Io.Base > Base) {\r
410 Io.Base = Base;\r
411 }\r
412 if (Io.Limit < Limit) {\r
413 Io.Limit = Limit;\r
414 }\r
415 }\r
416\r
417 //\r
418 // Get the Memory range that the PPB is decoding\r
419 //\r
420 Base = ((UINT32) Pci.Bridge.MemoryBase & 0xfff0) << 16;\r
421 Limit = (((UINT32) Pci.Bridge.MemoryLimit & 0xfff0) << 16) | 0xfffff;\r
422 if ((Base > 0) && (Base < Limit)) {\r
423 if (Mem.Base > Base) {\r
424 Mem.Base = Base;\r
425 }\r
426 if (Mem.Limit < Limit) {\r
427 Mem.Limit = Limit;\r
428 }\r
429 }\r
430\r
431 //\r
432 // Get the Prefetchable Memory range that the PPB is decoding\r
433 //\r
434 Value = Pci.Bridge.PrefetchableMemoryBase & 0x0f;\r
435 Base = ((UINT32) Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;\r
436 Limit = (((UINT32) Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)\r
437 << 16) | 0xfffff;\r
438 MemAperture = &PMem;\r
439 if (Value == BIT0) {\r
440 Base |= LShiftU64 (Pci.Bridge.PrefetchableBaseUpper32, 32);\r
441 Limit |= LShiftU64 (Pci.Bridge.PrefetchableLimitUpper32, 32);\r
442 MemAperture = &PMemAbove4G;\r
443 }\r
444 if ((Base > 0) && (Base < Limit)) {\r
445 if (MemAperture->Base > Base) {\r
446 MemAperture->Base = Base;\r
447 }\r
448 if (MemAperture->Limit < Limit) {\r
449 MemAperture->Limit = Limit;\r
450 }\r
451 }\r
452\r
453 //\r
454 // Look at the PPB Configuration for legacy decoding attributes\r
455 //\r
456 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_ISA)\r
457 == EFI_PCI_BRIDGE_CONTROL_ISA) {\r
458 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
459 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
460 Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
461 }\r
462 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA)\r
463 == EFI_PCI_BRIDGE_CONTROL_VGA) {\r
464 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
465 Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
466 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
467 if ((Pci.Bridge.BridgeControl & EFI_PCI_BRIDGE_CONTROL_VGA_16)\r
468 != 0) {\r
469 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
470 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
471 }\r
472 }\r
473\r
474 BarOffsetEnd = OFFSET_OF (PCI_TYPE01, Bridge.Bar[2]);\r
475 } else {\r
476 //\r
477 // Parse the BARs of the PCI device to get what I/O Ranges, Memory\r
478 // Ranges, and Prefetchable Memory Ranges the device is decoding\r
479 //\r
480 if ((Pci.Hdr.HeaderType & HEADER_LAYOUT_CODE) == HEADER_TYPE_DEVICE) {\r
481 BarOffsetEnd = OFFSET_OF (PCI_TYPE00, Device.Bar[6]);\r
482 }\r
483 }\r
484\r
485 PcatPciRootBridgeParseBars (\r
486 Pci.Hdr.Command,\r
487 PrimaryBus,\r
488 Device,\r
489 Function,\r
490 OFFSET_OF (PCI_TYPE00, Device.Bar),\r
491 BarOffsetEnd,\r
492 &Io,\r
493 &Mem, &MemAbove4G,\r
494 &PMem, &PMemAbove4G\r
495 );\r
496\r
497 //\r
498 // See if the PCI device is an IDE controller\r
499 //\r
500 if (IS_CLASS2 (&Pci, PCI_CLASS_MASS_STORAGE,\r
501 PCI_CLASS_MASS_STORAGE_IDE)) {\r
502 if (Pci.Hdr.ClassCode[0] & 0x80) {\r
503 Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
504 Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
505 }\r
506 if (Pci.Hdr.ClassCode[0] & 0x01) {\r
507 Attributes |= EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO;\r
508 }\r
509 if (Pci.Hdr.ClassCode[0] & 0x04) {\r
510 Attributes |= EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO;\r
511 }\r
512 }\r
513\r
514 //\r
515 // See if the PCI device is a legacy VGA controller or\r
516 // a standard VGA controller\r
517 //\r
518 if (IS_CLASS2 (&Pci, PCI_CLASS_OLD, PCI_CLASS_OLD_VGA) ||\r
519 IS_CLASS2 (&Pci, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_VGA)\r
520 ) {\r
521 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO;\r
522 Attributes |= EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16;\r
523 Attributes |= EFI_PCI_ATTRIBUTE_VGA_MEMORY;\r
524 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO;\r
525 Attributes |= EFI_PCI_ATTRIBUTE_VGA_IO_16;\r
526 }\r
527\r
528 //\r
529 // See if the PCI Device is a PCI - ISA or PCI - EISA\r
530 // or ISA_POSITIVIE_DECODE Bridge device\r
531 //\r
532 if (Pci.Hdr.ClassCode[2] == PCI_CLASS_BRIDGE) {\r
533 if (Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA ||\r
534 Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_EISA ||\r
535 Pci.Hdr.ClassCode[1] == PCI_CLASS_BRIDGE_ISA_PDECODE) {\r
536 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO;\r
537 Attributes |= EFI_PCI_ATTRIBUTE_ISA_IO_16;\r
538 Attributes |= EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO;\r
539 }\r
540 }\r
541\r
542 //\r
543 // If this device is not a multi function device, then skip the rest\r
544 // of this PCI device\r
545 //\r
546 if (Function == 0 && !IS_PCI_MULTI_FUNC (&Pci)) {\r
547 break;\r
548 }\r
549 }\r
550 }\r
551\r
552 //\r
553 // If at least one PCI device was found on the primary bus of this PCI\r
554 // root bridge, then the PCI root bridge exists.\r
555 //\r
556 if (NumberOfDevices > 0) {\r
557 RootBridges = ReallocatePool (\r
558 (*NumberOfRootBridges) * sizeof (PCI_ROOT_BRIDGE),\r
559 (*NumberOfRootBridges + 1) * sizeof (PCI_ROOT_BRIDGE),\r
560 RootBridges\r
561 );\r
562 ASSERT (RootBridges != NULL);\r
563\r
564 AdjustRootBridgeResource (&Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G);\r
565\r
566 InitRootBridge (\r
567 Attributes, Attributes, 0,\r
568 (UINT8) PrimaryBus, (UINT8) SubBus,\r
569 &Io, &Mem, &MemAbove4G, &PMem, &PMemAbove4G,\r
570 &RootBridges[*NumberOfRootBridges]\r
571 );\r
572 RootBridges[*NumberOfRootBridges].ResourceAssigned = TRUE;\r
573 //\r
574 // Increment the index for the next PCI Root Bridge\r
575 //\r
576 (*NumberOfRootBridges)++;\r
577 }\r
578 }\r
579\r
580 return RootBridges;\r
581}\r
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