projects / mirror_edk2.git / blame
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|---|---|---|
| c69dd9df | 1 | TITLE CpuInterrupt.asm: \r |
| 2 | ;------------------------------------------------------------------------------\r | |
| 3 | ;*\r | |
| b1f700a8 HT |
4 | ;* Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r |
| 5 | ;* This program and the accompanying materials \r | |
| c69dd9df | 6 | ;* are licensed and made available under the terms and conditions of the BSD License \r |
| 7 | ;* which accompanies this distribution. The full text of the license may be found at \r | |
| 8 | ;* http://opensource.org/licenses/bsd-license.php \r | |
| 9 | ;* \r | |
| 10 | ;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 11 | ;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 12 | ;* \r | |
| 13 | ;* CpuInterrupt.asm\r | |
| 14 | ;* \r | |
| 15 | ;* Abstract:\r | |
| 16 | ;*\r | |
| 17 | ;------------------------------------------------------------------------------\r | |
| 18 | \r | |
| 19 | .686p\r | |
| 20 | .model flat, C\r | |
| 21 | \r | |
| 22 | PUBLIC SystemTimerHandler\r | |
| 23 | PUBLIC SystemExceptionHandler\r | |
| 24 | EXTERNDEF mExceptionCodeSize:DWORD\r | |
| 25 | \r | |
| 26 | .code\r | |
| 27 | .stack\r | |
| 28 | .MMX\r | |
| 29 | .XMM\r | |
| 30 | \r | |
| 31 | EXTERN TimerHandler: NEAR\r | |
| 32 | EXTERN ExceptionHandler: NEAR\r | |
| 33 | EXTERN mTimerVector: DWORD\r | |
| 34 | \r | |
| 35 | mExceptionCodeSize DD 9\r | |
| 36 | \r | |
| 37 | InitDescriptor PROC C\r | |
| 38 | lea eax, [GDT_BASE] ; EAX=PHYSICAL address of gdt\r | |
| 39 | mov dword ptr [gdtr + 2],eax ; Put address of gdt into the gdtr\r | |
| 40 | lgdt fword ptr [gdtr]\r | |
| 41 | lea eax, [IDT_BASE] ; EAX=PHYSICAL address of idt\r | |
| 42 | mov dword ptr [idtr + 2],eax ; Put address of idt into the idtr\r | |
| 43 | lidt fword ptr [idtr]\r | |
| 44 | ret\r | |
| 45 | InitDescriptor ENDP\r | |
| 46 | \r | |
| 47 | ; VOID\r | |
| 48 | ; InstallInterruptHandler (\r | |
| 49 | ; UINTN Vector,\r | |
| 50 | ; VOID (*Handler)(VOID)\r | |
| 51 | ; )\r | |
| 52 | InstallInterruptHandler PROC C \\r | |
| 53 | Vector:DWORD, \\r | |
| 54 | Handler:DWORD\r | |
| 55 | \r | |
| 56 | push edi\r | |
| 57 | pushfd ; save eflags\r | |
| 58 | cli ; turn off interrupts\r | |
| 59 | sub esp, 6 ; open some space on the stack\r | |
| 60 | mov edi, esp\r | |
| 61 | sidt es:[edi] ; get fword address of IDT\r | |
| 62 | mov edi, es:[edi+2] ; move offset of IDT into EDI\r | |
| 63 | add esp, 6 ; correct stack\r | |
| 64 | mov eax, Vector ; Get vector number\r | |
| 65 | shl eax, 3 ; multiply by 8 to get offset\r | |
| 66 | add edi, eax ; add to IDT base to get entry\r | |
| 67 | mov eax, Handler ; load new address into IDT entry\r | |
| 68 | mov word ptr es:[edi], ax ; write bits 15..0 of offset\r | |
| 69 | shr eax, 16 ; use ax to copy 31..16 to descriptors\r | |
| 70 | mov word ptr es:[edi+6], ax ; write bits 31..16 of offset\r | |
| 71 | popfd ; restore flags (possible enabling interrupts)\r | |
| 72 | pop edi\r | |
| 73 | ret\r | |
| 74 | \r | |
| 75 | InstallInterruptHandler ENDP\r | |
| 76 | \r | |
| 77 | JmpCommonIdtEntry macro\r | |
| 78 | ; jmp commonIdtEntry - this must be hand coded to keep the assembler from\r | |
| 79 | ; using a 8 bit reletive jump when the entries are\r | |
| 80 | ; within 255 bytes of the common entry. This must\r | |
| 81 | ; be done to maintain the consistency of the size\r | |
| 82 | ; of entry points...\r | |
| 83 | db 0e9h ; jmp 16 bit reletive \r | |
| 84 | dd commonIdtEntry - $ - 4 ; offset to jump to\r | |
| 85 | endm\r | |
| 86 | \r | |
| 87 | align 02h\r | |
| 88 | SystemExceptionHandler PROC\r | |
| 89 | INT0:\r | |
| 90 | push 0h ; push error code place holder on the stack\r | |
| 91 | push 0h\r | |
| 92 | JmpCommonIdtEntry\r | |
| 93 | ; db 0e9h ; jmp 16 bit reletive \r | |
| 94 | ; dd commonIdtEntry - $ - 4 ; offset to jump to\r | |
| 95 | \r | |
| 96 | INT1:\r | |
| 97 | push 0h ; push error code place holder on the stack\r | |
| 98 | push 1h\r | |
| 99 | JmpCommonIdtEntry\r | |
| 100 | \r | |
| 101 | INT2:\r | |
| 102 | push 0h ; push error code place holder on the stack\r | |
| 103 | push 2h\r | |
| 104 | JmpCommonIdtEntry\r | |
| 105 | \r | |
| 106 | INT3:\r | |
| 107 | push 0h ; push error code place holder on the stack\r | |
| 108 | push 3h\r | |
| 109 | JmpCommonIdtEntry\r | |
| 110 | \r | |
| 111 | INT4:\r | |
| 112 | push 0h ; push error code place holder on the stack\r | |
| 113 | push 4h\r | |
| 114 | JmpCommonIdtEntry\r | |
| 115 | \r | |
| 116 | INT5:\r | |
| 117 | push 0h ; push error code place holder on the stack\r | |
| 118 | push 5h\r | |
| 119 | JmpCommonIdtEntry\r | |
| 120 | \r | |
| 121 | INT6:\r | |
| 122 | push 0h ; push error code place holder on the stack\r | |
| 123 | push 6h\r | |
| 124 | JmpCommonIdtEntry\r | |
| 125 | \r | |
| 126 | INT7:\r | |
| 127 | push 0h ; push error code place holder on the stack\r | |
| 128 | push 7h\r | |
| 129 | JmpCommonIdtEntry\r | |
| 130 | \r | |
| 131 | INT8:\r | |
| 132 | ; Double fault causes an error code to be pushed so no phony push necessary\r | |
| 133 | nop\r | |
| 134 | nop\r | |
| 135 | push 8h\r | |
| 136 | JmpCommonIdtEntry\r | |
| 137 | \r | |
| 138 | INT9:\r | |
| 139 | push 0h ; push error code place holder on the stack\r | |
| 140 | push 9h\r | |
| 141 | JmpCommonIdtEntry\r | |
| 142 | \r | |
| 143 | INT10:\r | |
| 144 | ; Invalid TSS causes an error code to be pushed so no phony push necessary\r | |
| 145 | nop\r | |
| 146 | nop\r | |
| 147 | push 10\r | |
| 148 | JmpCommonIdtEntry\r | |
| 149 | \r | |
| 150 | INT11:\r | |
| 151 | ; Segment Not Present causes an error code to be pushed so no phony push necessary\r | |
| 152 | nop\r | |
| 153 | nop\r | |
| 154 | push 11\r | |
| 155 | JmpCommonIdtEntry\r | |
| 156 | \r | |
| 157 | INT12:\r | |
| 158 | ; Stack fault causes an error code to be pushed so no phony push necessary\r | |
| 159 | nop\r | |
| 160 | nop\r | |
| 161 | push 12\r | |
| 162 | JmpCommonIdtEntry\r | |
| 163 | \r | |
| 164 | INT13:\r | |
| 165 | ; GP fault causes an error code to be pushed so no phony push necessary\r | |
| 166 | nop\r | |
| 167 | nop\r | |
| 168 | push 13\r | |
| 169 | JmpCommonIdtEntry\r | |
| 170 | \r | |
| 171 | INT14:\r | |
| 172 | ; Page fault causes an error code to be pushed so no phony push necessary\r | |
| 173 | nop\r | |
| 174 | nop\r | |
| 175 | push 14\r | |
| 176 | JmpCommonIdtEntry\r | |
| 177 | \r | |
| 178 | INT15:\r | |
| 179 | push 0h ; push error code place holder on the stack\r | |
| 180 | push 15\r | |
| 181 | JmpCommonIdtEntry\r | |
| 182 | \r | |
| 183 | INT16:\r | |
| 184 | push 0h ; push error code place holder on the stack\r | |
| 185 | push 16\r | |
| 186 | JmpCommonIdtEntry\r | |
| 187 | \r | |
| 188 | INT17:\r | |
| 189 | ; Alignment check causes an error code to be pushed so no phony push necessary\r | |
| 190 | nop\r | |
| 191 | nop\r | |
| 192 | push 17\r | |
| 193 | JmpCommonIdtEntry\r | |
| 194 | \r | |
| 195 | INT18:\r | |
| 196 | push 0h ; push error code place holder on the stack\r | |
| 197 | push 18\r | |
| 198 | JmpCommonIdtEntry\r | |
| 199 | \r | |
| 200 | INT19:\r | |
| 201 | push 0h ; push error code place holder on the stack\r | |
| 202 | push 19\r | |
| 203 | JmpCommonIdtEntry\r | |
| 204 | \r | |
| 205 | INTUnknown:\r | |
| 206 | REPEAT (32 - 20)\r | |
| 207 | push 0h ; push error code place holder on the stack\r | |
| 208 | ; push xxh ; push vector number\r | |
| 209 | db 06ah\r | |
| 210 | db ( $ - INTUnknown - 3 ) / 9 + 20 ; vector number\r | |
| 211 | JmpCommonIdtEntry\r | |
| 212 | ENDM\r | |
| 213 | SystemExceptionHandler ENDP\r | |
| 214 | \r | |
| 215 | SystemTimerHandler PROC\r | |
| 216 | push 0\r | |
| 217 | push mTimerVector\r | |
| 218 | JmpCommonIdtEntry\r | |
| 219 | SystemTimerHandler ENDP\r | |
| 220 | \r | |
| 221 | commonIdtEntry:\r | |
| 222 | ; +---------------------+\r | |
| 223 | ; + EFlags +\r | |
| 224 | ; +---------------------+\r | |
| 225 | ; + CS +\r | |
| 226 | ; +---------------------+\r | |
| 227 | ; + EIP +\r | |
| 228 | ; +---------------------+\r | |
| 229 | ; + Error Code +\r | |
| 230 | ; +---------------------+\r | |
| 231 | ; + Vector Number +\r | |
| 232 | ; +---------------------+\r | |
| 233 | ; + EBP +\r | |
| 234 | ; +---------------------+ <-- EBP\r | |
| 235 | \r | |
| 236 | cli\r | |
| 237 | push ebp\r | |
| 238 | mov ebp, esp\r | |
| 239 | \r | |
| 240 | ;\r | |
| 241 | ; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32\r | |
| 242 | ; is 16-byte aligned\r | |
| 243 | ;\r | |
| 244 | and esp, 0fffffff0h\r | |
| 245 | sub esp, 12\r | |
| 246 | \r | |
| 247 | ;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r | |
| 248 | push eax\r | |
| 249 | push ecx\r | |
| 250 | push edx\r | |
| 251 | push ebx\r | |
| 252 | lea ecx, [ebp + 6 * 4]\r | |
| 253 | push ecx ; ESP\r | |
| 254 | push dword ptr [ebp] ; EBP\r | |
| 255 | push esi\r | |
| 256 | push edi\r | |
| 257 | \r | |
| 258 | ;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r | |
| 259 | mov eax, ss\r | |
| 260 | push eax\r | |
| 261 | movzx eax, word ptr [ebp + 4 * 4]\r | |
| 262 | push eax\r | |
| 263 | mov eax, ds\r | |
| 264 | push eax\r | |
| 265 | mov eax, es\r | |
| 266 | push eax\r | |
| 267 | mov eax, fs\r | |
| 268 | push eax\r | |
| 269 | mov eax, gs\r | |
| 270 | push eax\r | |
| 271 | \r | |
| 272 | ;; UINT32 Eip;\r | |
| 273 | push dword ptr [ebp + 3 * 4]\r | |
| 274 | \r | |
| 275 | ;; UINT32 Gdtr[2], Idtr[2];\r | |
| 276 | sub esp, 8\r | |
| 277 | sidt fword ptr [esp]\r | |
| 278 | sub esp, 8\r | |
| 279 | sgdt fword ptr [esp]\r | |
| 280 | \r | |
| 281 | ;; UINT32 Ldtr, Tr;\r | |
| 282 | xor eax, eax\r | |
| 283 | str ax\r | |
| 284 | push eax\r | |
| 285 | sldt ax\r | |
| 286 | push eax\r | |
| 287 | \r | |
| 288 | ;; UINT32 EFlags;\r | |
| 289 | push dword ptr [ebp + 5 * 4]\r | |
| 290 | \r | |
| 291 | ;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r | |
| 292 | mov eax, cr4\r | |
| 293 | or eax, 208h\r | |
| 294 | mov cr4, eax\r | |
| 295 | push eax\r | |
| 296 | mov eax, cr3\r | |
| 297 | push eax\r | |
| 298 | mov eax, cr2\r | |
| 299 | push eax\r | |
| 300 | xor eax, eax\r | |
| 301 | push eax\r | |
| 302 | mov eax, cr0\r | |
| 303 | push eax\r | |
| 304 | \r | |
| 305 | ;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r | |
| 306 | mov eax, dr7\r | |
| 307 | push eax\r | |
| 308 | ;; clear Dr7 while executing debugger itself\r | |
| 309 | xor eax, eax\r | |
| 310 | mov dr7, eax\r | |
| 311 | \r | |
| 312 | mov eax, dr6\r | |
| 313 | push eax\r | |
| 314 | ;; insure all status bits in dr6 are clear...\r | |
| 315 | xor eax, eax\r | |
| 316 | mov dr6, eax\r | |
| 317 | \r | |
| 318 | mov eax, dr3\r | |
| 319 | push eax\r | |
| 320 | mov eax, dr2\r | |
| 321 | push eax\r | |
| 322 | mov eax, dr1\r | |
| 323 | push eax\r | |
| 324 | mov eax, dr0\r | |
| 325 | push eax\r | |
| 326 | \r | |
| 327 | ;; FX_SAVE_STATE_IA32 FxSaveState;\r | |
| 328 | sub esp, 512\r | |
| 329 | mov edi, esp\r | |
| 330 | db 0fh, 0aeh, 00000111y ;fxsave [edi]\r | |
| 331 | \r | |
| 332 | ;; UINT32 ExceptionData;\r | |
| 333 | push dword ptr [ebp + 2 * 4]\r | |
| 334 | \r | |
| 335 | ;; Prepare parameter and call\r | |
| 336 | mov edx, esp\r | |
| 337 | push edx\r | |
| 338 | mov eax, dword ptr [ebp + 1 * 4]\r | |
| 339 | push eax\r | |
| 340 | cmp eax, 32\r | |
| 341 | jb CallException\r | |
| 342 | call TimerHandler\r | |
| 343 | jmp ExceptionDone\r | |
| 344 | CallException:\r | |
| 345 | call ExceptionHandler\r | |
| 346 | ExceptionDone:\r | |
| 347 | add esp, 8\r | |
| 348 | \r | |
| 349 | cli\r | |
| 350 | ;; UINT32 ExceptionData;\r | |
| 351 | add esp, 4\r | |
| 352 | \r | |
| 353 | ;; FX_SAVE_STATE_IA32 FxSaveState;\r | |
| 354 | mov esi, esp\r | |
| 355 | db 0fh, 0aeh, 00001110y ; fxrstor [esi]\r | |
| 356 | add esp, 512\r | |
| 357 | \r | |
| 358 | ;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r | |
| 359 | pop eax\r | |
| 360 | mov dr0, eax\r | |
| 361 | pop eax\r | |
| 362 | mov dr1, eax\r | |
| 363 | pop eax\r | |
| 364 | mov dr2, eax\r | |
| 365 | pop eax\r | |
| 366 | mov dr3, eax\r | |
| 367 | ;; skip restore of dr6. We cleared dr6 during the context save.\r | |
| 368 | add esp, 4\r | |
| 369 | pop eax\r | |
| 370 | mov dr7, eax\r | |
| 371 | \r | |
| 372 | ;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r | |
| 373 | pop eax\r | |
| 374 | mov cr0, eax\r | |
| 375 | add esp, 4 ; not for Cr1\r | |
| 376 | pop eax\r | |
| 377 | mov cr2, eax\r | |
| 378 | pop eax\r | |
| 379 | mov cr3, eax\r | |
| 380 | pop eax\r | |
| 381 | mov cr4, eax\r | |
| 382 | \r | |
| 383 | ;; UINT32 EFlags;\r | |
| 384 | pop dword ptr [ebp + 5 * 4]\r | |
| 385 | \r | |
| 386 | ;; UINT32 Ldtr, Tr;\r | |
| 387 | ;; UINT32 Gdtr[2], Idtr[2];\r | |
| 388 | ;; Best not let anyone mess with these particular registers...\r | |
| 389 | add esp, 24\r | |
| 390 | \r | |
| 391 | ;; UINT32 Eip;\r | |
| 392 | pop dword ptr [ebp + 3 * 4]\r | |
| 393 | \r | |
| 394 | ;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r | |
| 395 | ;; NOTE - modified segment registers could hang the debugger... We\r | |
| 396 | ;; could attempt to insulate ourselves against this possibility,\r | |
| 397 | ;; but that poses risks as well.\r | |
| 398 | ;;\r | |
| 399 | pop gs\r | |
| 400 | pop fs\r | |
| 401 | pop es\r | |
| 402 | pop ds\r | |
| 403 | pop dword ptr [ebp + 4 * 4]\r | |
| 404 | pop ss\r | |
| 405 | \r | |
| 406 | ;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r | |
| 407 | pop edi\r | |
| 408 | pop esi\r | |
| 409 | add esp, 4 ; not for ebp\r | |
| 410 | add esp, 4 ; not for esp\r | |
| 411 | pop ebx\r | |
| 412 | pop edx\r | |
| 413 | pop ecx\r | |
| 414 | pop eax\r | |
| 415 | \r | |
| 416 | mov esp, ebp\r | |
| 417 | pop ebp\r | |
| 418 | add esp, 8\r | |
| 419 | iretd\r | |
| 420 | \r | |
| 421 | \r | |
| 422 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r | |
| 423 | ; data\r | |
| 424 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r | |
| 425 | \r | |
| 426 | align 02h\r | |
| 427 | \r | |
| 428 | gdtr dw GDT_END - GDT_BASE - 1 ; GDT limit\r | |
| 429 | dd 0 ; (GDT base gets set above)\r | |
| 430 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r | |
| 431 | ; global descriptor table (GDT)\r | |
| 432 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r | |
| 433 | \r | |
| 434 | align 02h\r | |
| 435 | \r | |
| 436 | public GDT_BASE\r | |
| 437 | GDT_BASE:\r | |
| 438 | ; null descriptor\r | |
| 439 | NULL_SEL equ $-GDT_BASE\r | |
| 440 | dw 0 ; limit 15:0\r | |
| 441 | dw 0 ; base 15:0\r | |
| 442 | db 0 ; base 23:16\r | |
| 443 | db 0 ; type\r | |
| 444 | db 0 ; limit 19:16, flags\r | |
| 445 | db 0 ; base 31:24\r | |
| 446 | \r | |
| 447 | ; linear data segment descriptor\r | |
| 448 | LINEAR_SEL equ $-GDT_BASE\r | |
| 449 | dw 0FFFFh ; limit 0xFFFFF\r | |
| 450 | dw 0 ; base 0\r | |
| 451 | db 0\r | |
| 452 | db 092h ; present, ring 0, data, expand-up, writable\r | |
| 453 | db 0CFh ; page-granular, 32-bit\r | |
| 454 | db 0\r | |
| 455 | \r | |
| 456 | ; linear code segment descriptor\r | |
| 457 | LINEAR_CODE_SEL equ $-GDT_BASE\r | |
| 458 | dw 0FFFFh ; limit 0xFFFFF\r | |
| 459 | dw 0 ; base 0\r | |
| 460 | db 0\r | |
| 461 | db 09Ah ; present, ring 0, data, expand-up, writable\r | |
| 462 | db 0CFh ; page-granular, 32-bit\r | |
| 463 | db 0\r | |
| 464 | \r | |
| 465 | ; system data segment descriptor\r | |
| 466 | SYS_DATA_SEL equ $-GDT_BASE\r | |
| 467 | dw 0FFFFh ; limit 0xFFFFF\r | |
| 468 | dw 0 ; base 0\r | |
| 469 | db 0\r | |
| 470 | db 092h ; present, ring 0, data, expand-up, writable\r | |
| 471 | db 0CFh ; page-granular, 32-bit\r | |
| 472 | db 0\r | |
| 473 | \r | |
| 474 | ; system code segment descriptor\r | |
| 475 | SYS_CODE_SEL equ $-GDT_BASE\r | |
| 476 | dw 0FFFFh ; limit 0xFFFFF\r | |
| 477 | dw 0 ; base 0\r | |
| 478 | db 0\r | |
| 479 | db 09Ah ; present, ring 0, data, expand-up, writable\r | |
| 480 | db 0CFh ; page-granular, 32-bit\r | |
| 481 | db 0\r | |
| 482 | \r | |
| 483 | ; spare segment descriptor\r | |
| 484 | SPARE3_SEL equ $-GDT_BASE\r | |
| 485 | dw 0 ; limit 0xFFFFF\r | |
| 486 | dw 0 ; base 0\r | |
| 487 | db 0\r | |
| 488 | db 0 ; present, ring 0, data, expand-up, writable\r | |
| 489 | db 0 ; page-granular, 32-bit\r | |
| 490 | db 0\r | |
| 491 | \r | |
| 492 | ; spare segment descriptor\r | |
| 493 | SPARE4_SEL equ $-GDT_BASE\r | |
| 494 | dw 0 ; limit 0xFFFFF\r | |
| 495 | dw 0 ; base 0\r | |
| 496 | db 0\r | |
| 497 | db 0 ; present, ring 0, data, expand-up, writable\r | |
| 498 | db 0 ; page-granular, 32-bit\r | |
| 499 | db 0\r | |
| 500 | \r | |
| 501 | ; spare segment descriptor\r | |
| 502 | SPARE5_SEL equ $-GDT_BASE\r | |
| 503 | dw 0 ; limit 0xFFFFF\r | |
| 504 | dw 0 ; base 0\r | |
| 505 | db 0\r | |
| 506 | db 0 ; present, ring 0, data, expand-up, writable\r | |
| 507 | db 0 ; page-granular, 32-bit\r | |
| 508 | db 0\r | |
| 509 | \r | |
| 510 | GDT_END:\r | |
| 511 | \r | |
| 512 | align 02h\r | |
| 513 | \r | |
| 514 | \r | |
| 515 | \r | |
| 516 | idtr dw IDT_END - IDT_BASE - 1 ; IDT limit\r | |
| 517 | dd 0 ; (IDT base gets set above)\r | |
| 518 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r | |
| 519 | ; interrupt descriptor table (IDT)\r | |
| 520 | ;\r | |
| 521 | ; Note: The hardware IRQ's specified in this table are the normal PC/AT IRQ\r | |
| 522 | ; mappings. This implementation only uses the system timer and all other\r | |
| 523 | ; IRQs will remain masked. The descriptors for vectors 33+ are provided\r | |
| 524 | ; for convenience.\r | |
| 525 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r | |
| 526 | \r | |
| 527 | ;idt_tag db "IDT",0 \r | |
| 528 | align 02h\r | |
| 529 | \r | |
| 530 | public IDT_BASE\r | |
| 531 | IDT_BASE:\r | |
| 532 | ; divide by zero (INT 0)\r | |
| 533 | DIV_ZERO_SEL equ $-IDT_BASE\r | |
| 534 | dw 0 ; offset 15:0\r | |
| 535 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 536 | db 0 ; 0 for interrupt gate\r | |
| 537 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 538 | dw 0 ; offset 31:16\r | |
| 539 | \r | |
| 540 | ; debug exception (INT 1)\r | |
| 541 | DEBUG_EXCEPT_SEL equ $-IDT_BASE\r | |
| 542 | dw 0 ; offset 15:0\r | |
| 543 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 544 | db 0 ; 0 for interrupt gate\r | |
| 545 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 546 | dw 0 ; offset 31:16\r | |
| 547 | \r | |
| 548 | ; NMI (INT 2)\r | |
| 549 | NMI_SEL equ $-IDT_BASE\r | |
| 550 | dw 0 ; offset 15:0\r | |
| 551 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 552 | db 0 ; 0 for interrupt gate\r | |
| 553 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 554 | dw 0 ; offset 31:16\r | |
| 555 | \r | |
| 556 | ; soft breakpoint (INT 3)\r | |
| 557 | BREAKPOINT_SEL equ $-IDT_BASE\r | |
| 558 | dw 0 ; offset 15:0\r | |
| 559 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 560 | db 0 ; 0 for interrupt gate\r | |
| 561 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 562 | dw 0 ; offset 31:16\r | |
| 563 | \r | |
| 564 | ; overflow (INT 4)\r | |
| 565 | OVERFLOW_SEL equ $-IDT_BASE\r | |
| 566 | dw 0 ; offset 15:0\r | |
| 567 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 568 | db 0 ; 0 for interrupt gate\r | |
| 569 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 570 | dw 0 ; offset 31:16\r | |
| 571 | \r | |
| 572 | ; bounds check (INT 5)\r | |
| 573 | BOUNDS_CHECK_SEL equ $-IDT_BASE\r | |
| 574 | dw 0 ; offset 15:0\r | |
| 575 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 576 | db 0 ; 0 for interrupt gate\r | |
| 577 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 578 | dw 0 ; offset 31:16\r | |
| 579 | \r | |
| 580 | ; invalid opcode (INT 6)\r | |
| 581 | INVALID_OPCODE_SEL equ $-IDT_BASE\r | |
| 582 | dw 0 ; offset 15:0\r | |
| 583 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 584 | db 0 ; 0 for interrupt gate\r | |
| 585 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 586 | dw 0 ; offset 31:16\r | |
| 587 | \r | |
| 588 | ; device not available (INT 7)\r | |
| 589 | DEV_NOT_AVAIL_SEL equ $-IDT_BASE\r | |
| 590 | dw 0 ; offset 15:0\r | |
| 591 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 592 | db 0 ; 0 for interrupt gate\r | |
| 593 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 594 | dw 0 ; offset 31:16\r | |
| 595 | \r | |
| 596 | ; double fault (INT 8)\r | |
| 597 | DOUBLE_FAULT_SEL equ $-IDT_BASE\r | |
| 598 | dw 0 ; offset 15:0\r | |
| 599 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 600 | db 0 ; 0 for interrupt gate\r | |
| 601 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 602 | dw 0 ; offset 31:16\r | |
| 603 | \r | |
| 604 | ; Coprocessor segment overrun - reserved (INT 9)\r | |
| 605 | RSVD_INTR_SEL1 equ $-IDT_BASE\r | |
| 606 | dw 0 ; offset 15:0\r | |
| 607 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 608 | db 0 ; 0 for interrupt gate\r | |
| 609 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 610 | dw 0 ; offset 31:16\r | |
| 611 | \r | |
| 612 | ; invalid TSS (INT 0ah)\r | |
| 613 | INVALID_TSS_SEL equ $-IDT_BASE\r | |
| 614 | dw 0 ; offset 15:0\r | |
| 615 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 616 | db 0 ; 0 for interrupt gate\r | |
| 617 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 618 | dw 0 ; offset 31:16\r | |
| 619 | \r | |
| 620 | ; segment not present (INT 0bh)\r | |
| 621 | SEG_NOT_PRESENT_SEL equ $-IDT_BASE\r | |
| 622 | dw 0 ; offset 15:0\r | |
| 623 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 624 | db 0 ; 0 for interrupt gate\r | |
| 625 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 626 | dw 0 ; offset 31:16\r | |
| 627 | \r | |
| 628 | ; stack fault (INT 0ch)\r | |
| 629 | STACK_FAULT_SEL equ $-IDT_BASE\r | |
| 630 | dw 0 ; offset 15:0\r | |
| 631 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 632 | db 0 ; 0 for interrupt gate\r | |
| 633 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 634 | dw 0 ; offset 31:16\r | |
| 635 | \r | |
| 636 | ; general protection (INT 0dh)\r | |
| 637 | GP_FAULT_SEL equ $-IDT_BASE\r | |
| 638 | dw 0 ; offset 15:0\r | |
| 639 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 640 | db 0 ; 0 for interrupt gate\r | |
| 641 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 642 | dw 0 ; offset 31:16\r | |
| 643 | \r | |
| 644 | ; page fault (INT 0eh)\r | |
| 645 | PAGE_FAULT_SEL equ $-IDT_BASE\r | |
| 646 | dw 0 ; offset 15:0\r | |
| 647 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 648 | db 0 ; 0 for interrupt gate\r | |
| 649 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 650 | dw 0 ; offset 31:16\r | |
| 651 | \r | |
| 652 | ; Intel reserved - do not use (INT 0fh)\r | |
| 653 | RSVD_INTR_SEL2 equ $-IDT_BASE\r | |
| 654 | dw 0 ; offset 15:0\r | |
| 655 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 656 | db 0 ; 0 for interrupt gate\r | |
| 657 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 658 | dw 0 ; offset 31:16\r | |
| 659 | \r | |
| 660 | ; floating point error (INT 10h)\r | |
| 661 | FLT_POINT_ERR_SEL equ $-IDT_BASE\r | |
| 662 | dw 0 ; offset 15:0\r | |
| 663 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 664 | db 0 ; 0 for interrupt gate\r | |
| 665 | db 0eh OR 80h ; type = 386 interrupt gate, present\r | |
| 666 | dw 0 ; offset 31:16\r | |
| 667 | \r | |
| 668 | ; alignment check (INT 11h)\r | |
| 669 | ALIGNMENT_CHECK_SEL equ $-IDT_BASE\r | |
| 670 | dw 0 ; offset 15:0\r | |
| 671 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 672 | db 0 ; 0 for interrupt gate\r | |
| 673 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 674 | dw 0 ; offset 31:16\r | |
| 675 | \r | |
| 676 | ; machine check (INT 12h)\r | |
| 677 | MACHINE_CHECK_SEL equ $-IDT_BASE\r | |
| 678 | dw 0 ; offset 15:0\r | |
| 679 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 680 | db 0 ; 0 for interrupt gate\r | |
| 681 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 682 | dw 0 ; offset 31:16\r | |
| 683 | \r | |
| 684 | ; SIMD floating-point exception (INT 13h)\r | |
| 685 | SIMD_EXCEPTION_SEL equ $-IDT_BASE\r | |
| 686 | dw 0 ; offset 15:0\r | |
| 687 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 688 | db 0 ; 0 for interrupt gate\r | |
| 689 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 690 | dw 0 ; offset 31:16\r | |
| 691 | \r | |
| 692 | REPEAT (32 - 20)\r | |
| 693 | dw 0 ; offset 15:0\r | |
| 694 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 695 | db 0 ; 0 for interrupt gate\r | |
| 696 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 697 | dw 0 ; offset 31:16\r | |
| 698 | ENDM\r | |
| 699 | \r | |
| 700 | ; 72 unspecified descriptors\r | |
| 701 | db (72 * 8) dup(0)\r | |
| 702 | \r | |
| 703 | ; IRQ 0 (System timer) - (INT 68h)\r | |
| 704 | IRQ0_SEL equ $-IDT_BASE\r | |
| 705 | dw 0 ; offset 15:0\r | |
| 706 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 707 | db 0 ; 0 for interrupt gate\r | |
| 708 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 709 | dw 0 ; offset 31:16\r | |
| 710 | \r | |
| 711 | ; IRQ 1 (8042 Keyboard controller) - (INT 69h)\r | |
| 712 | IRQ1_SEL equ $-IDT_BASE\r | |
| 713 | dw 0 ; offset 15:0\r | |
| 714 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 715 | db 0 ; 0 for interrupt gate\r | |
| 716 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 717 | dw 0 ; offset 31:16\r | |
| 718 | \r | |
| 719 | ; Reserved - IRQ 2 redirect (IRQ 2) - DO NOT USE!!! - (INT 6ah)\r | |
| 720 | IRQ2_SEL equ $-IDT_BASE\r | |
| 721 | dw 0 ; offset 15:0\r | |
| 722 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 723 | db 0 ; 0 for interrupt gate\r | |
| 724 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 725 | dw 0 ; offset 31:16\r | |
| 726 | \r | |
| 727 | ; IRQ 3 (COM 2) - (INT 6bh)\r | |
| 728 | IRQ3_SEL equ $-IDT_BASE\r | |
| 729 | dw 0 ; offset 15:0\r | |
| 730 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 731 | db 0 ; 0 for interrupt gate\r | |
| 732 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 733 | dw 0 ; offset 31:16\r | |
| 734 | \r | |
| 735 | ; IRQ 4 (COM 1) - (INT 6ch)\r | |
| 736 | IRQ4_SEL equ $-IDT_BASE\r | |
| 737 | dw 0 ; offset 15:0\r | |
| 738 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 739 | db 0 ; 0 for interrupt gate\r | |
| 740 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 741 | dw 0 ; offset 31:16\r | |
| 742 | \r | |
| 743 | ; IRQ 5 (LPT 2) - (INT 6dh)\r | |
| 744 | IRQ5_SEL equ $-IDT_BASE\r | |
| 745 | dw 0 ; offset 15:0\r | |
| 746 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 747 | db 0 ; 0 for interrupt gate\r | |
| 748 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 749 | dw 0 ; offset 31:16\r | |
| 750 | \r | |
| 751 | ; IRQ 6 (Floppy controller) - (INT 6eh)\r | |
| 752 | IRQ6_SEL equ $-IDT_BASE\r | |
| 753 | dw 0 ; offset 15:0\r | |
| 754 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 755 | db 0 ; 0 for interrupt gate\r | |
| 756 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 757 | dw 0 ; offset 31:16\r | |
| 758 | \r | |
| 759 | ; IRQ 7 (LPT 1) - (INT 6fh)\r | |
| 760 | IRQ7_SEL equ $-IDT_BASE\r | |
| 761 | dw 0 ; offset 15:0\r | |
| 762 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 763 | db 0 ; 0 for interrupt gate\r | |
| 764 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 765 | dw 0 ; offset 31:16\r | |
| 766 | \r | |
| 767 | ; IRQ 8 (RTC Alarm) - (INT 70h)\r | |
| 768 | IRQ8_SEL equ $-IDT_BASE\r | |
| 769 | dw 0 ; offset 15:0\r | |
| 770 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 771 | db 0 ; 0 for interrupt gate\r | |
| 772 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 773 | dw 0 ; offset 31:16\r | |
| 774 | \r | |
| 775 | ; IRQ 9 - (INT 71h)\r | |
| 776 | IRQ9_SEL equ $-IDT_BASE\r | |
| 777 | dw 0 ; offset 15:0\r | |
| 778 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 779 | db 0 ; 0 for interrupt gate\r | |
| 780 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 781 | dw 0 ; offset 31:16\r | |
| 782 | \r | |
| 783 | ; IRQ 10 - (INT 72h)\r | |
| 784 | IRQ10_SEL equ $-IDT_BASE\r | |
| 785 | dw 0 ; offset 15:0\r | |
| 786 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 787 | db 0 ; 0 for interrupt gate\r | |
| 788 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 789 | dw 0 ; offset 31:16\r | |
| 790 | \r | |
| 791 | ; IRQ 11 - (INT 73h)\r | |
| 792 | IRQ11_SEL equ $-IDT_BASE\r | |
| 793 | dw 0 ; offset 15:0\r | |
| 794 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 795 | db 0 ; 0 for interrupt gate\r | |
| 796 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 797 | dw 0 ; offset 31:16\r | |
| 798 | \r | |
| 799 | ; IRQ 12 (PS/2 mouse) - (INT 74h)\r | |
| 800 | IRQ12_SEL equ $-IDT_BASE\r | |
| 801 | dw 0 ; offset 15:0\r | |
| 802 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 803 | db 0 ; 0 for interrupt gate\r | |
| 804 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 805 | dw 0 ; offset 31:16\r | |
| 806 | \r | |
| 807 | ; IRQ 13 (Floating point error) - (INT 75h)\r | |
| 808 | IRQ13_SEL equ $-IDT_BASE\r | |
| 809 | dw 0 ; offset 15:0\r | |
| 810 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 811 | db 0 ; 0 for interrupt gate\r | |
| 812 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 813 | dw 0 ; offset 31:16\r | |
| 814 | \r | |
| 815 | ; IRQ 14 (Secondary IDE) - (INT 76h)\r | |
| 816 | IRQ14_SEL equ $-IDT_BASE\r | |
| 817 | dw 0 ; offset 15:0\r | |
| 818 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 819 | db 0 ; 0 for interrupt gate\r | |
| 820 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 821 | dw 0 ; offset 31:16\r | |
| 822 | \r | |
| 823 | ; IRQ 15 (Primary IDE) - (INT 77h)\r | |
| 824 | IRQ15_SEL equ $-IDT_BASE\r | |
| 825 | dw 0 ; offset 15:0\r | |
| 826 | dw SYS_CODE_SEL ; selector 15:0\r | |
| 827 | db 0 ; 0 for interrupt gate\r | |
| 828 | db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r | |
| 829 | dw 0 ; offset 31:16\r | |
| 830 | \r | |
| 831 | db (1 * 8) dup(0)\r | |
| 832 | \r | |
| 833 | IDT_END:\r | |
| 834 | \r | |
| 835 | END\r |