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c69dd9df 1 TITLE CpuInterrupt.asm: \r
2;------------------------------------------------------------------------------\r
3;*\r
4;* Copyright 2006, Intel Corporation \r
5;* All rights reserved. This program and the accompanying materials \r
6;* are licensed and made available under the terms and conditions of the BSD License \r
7;* which accompanies this distribution. The full text of the license may be found at \r
8;* http://opensource.org/licenses/bsd-license.php \r
9;* \r
10;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12;* \r
13;* CpuInterrupt.asm\r
14;* \r
15;* Abstract:\r
16;*\r
17;------------------------------------------------------------------------------\r
18\r
19EXTERNDEF mExceptionCodeSize:DWORD\r
20\r
21.code\r
22\r
23EXTERN TimerHandler: FAR\r
24EXTERN ExceptionHandler: NEAR\r
25EXTERN mTimerVector: QWORD\r
26\r
27mExceptionCodeSize DD 9\r
28\r
29InitDescriptor PROC\r
30 lea rax, [GDT_BASE] ; RAX=PHYSICAL address of gdt\r
31 mov qword ptr [gdtr + 2], rax ; Put address of gdt into the gdtr\r
32 lgdt fword ptr [gdtr]\r
33 mov rax, 18h\r
34 mov gs, rax\r
35 mov fs, rax\r
36 lea rax, [IDT_BASE] ; RAX=PHYSICAL address of idt\r
37 mov qword ptr [idtr + 2], rax ; Put address of idt into the idtr\r
38 lidt fword ptr [idtr]\r
39 ret\r
40InitDescriptor ENDP\r
41\r
42; VOID\r
43; InstallInterruptHandler (\r
44; UINTN Vector, // rcx\r
45; void (*Handler)(void) // rdx\r
46; )\r
47InstallInterruptHandler PROC \r
48 push rbx\r
49 pushfq ; save eflags\r
50 cli ; turn off interrupts\r
51 sub rsp, 10h ; open some space on the stack\r
52 mov rbx, rsp\r
53 sidt [rbx] ; get fword address of IDT\r
54 mov rbx, [rbx+2] ; move offset of IDT into RBX\r
55 add rsp, 10h ; correct stack\r
56 mov rax, rcx ; Get vector number\r
57 shl rax, 4 ; multiply by 16 to get offset\r
58 add rbx, rax ; add to IDT base to get entry\r
59 mov rax, rdx ; load new address into IDT entry\r
60 mov word ptr [rbx], ax ; write bits 15..0 of offset\r
61 shr rax, 16 ; use ax to copy 31..16 to descriptors\r
62 mov word ptr [rbx+6], ax ; write bits 31..16 of offset\r
63 shr rax, 16 ; use eax to copy 63..32 to descriptors\r
64 mov dword ptr [rbx+8], eax ; write bits 63..32 of offset\r
65 popfq ; restore flags (possible enabling interrupts)\r
66 pop rbx\r
67 ret\r
68\r
69InstallInterruptHandler ENDP\r
70\r
71JmpCommonIdtEntry macro\r
72 ; jmp commonIdtEntry - this must be hand coded to keep the assembler from\r
73 ; using a 8 bit reletive jump when the entries are\r
74 ; within 255 bytes of the common entry. This must\r
75 ; be done to maintain the consistency of the size\r
76 ; of entry points...\r
77 db 0e9h ; jmp 16 bit reletive \r
78 dd commonIdtEntry - $ - 4 ; offset to jump to\r
79endm\r
80\r
81 align 02h\r
82SystemExceptionHandler PROC\r
83INT0:\r
84 push 0h ; push error code place holder on the stack\r
85 push 0h\r
86 JmpCommonIdtEntry\r
87; db 0e9h ; jmp 16 bit reletive \r
88; dd commonIdtEntry - $ - 4 ; offset to jump to\r
89 \r
90INT1:\r
91 push 0h ; push error code place holder on the stack\r
92 push 1h\r
93 JmpCommonIdtEntry\r
94 \r
95INT2:\r
96 push 0h ; push error code place holder on the stack\r
97 push 2h\r
98 JmpCommonIdtEntry\r
99 \r
100INT3:\r
101 push 0h ; push error code place holder on the stack\r
102 push 3h\r
103 JmpCommonIdtEntry\r
104 \r
105INT4:\r
106 push 0h ; push error code place holder on the stack\r
107 push 4h\r
108 JmpCommonIdtEntry\r
109 \r
110INT5:\r
111 push 0h ; push error code place holder on the stack\r
112 push 5h\r
113 JmpCommonIdtEntry\r
114 \r
115INT6:\r
116 push 0h ; push error code place holder on the stack\r
117 push 6h\r
118 JmpCommonIdtEntry\r
119 \r
120INT7:\r
121 push 0h ; push error code place holder on the stack\r
122 push 7h\r
123 JmpCommonIdtEntry\r
124 \r
125INT8:\r
126; Double fault causes an error code to be pushed so no phony push necessary\r
127 nop\r
128 nop\r
129 push 8h\r
130 JmpCommonIdtEntry\r
131 \r
132INT9:\r
133 push 0h ; push error code place holder on the stack\r
134 push 9h\r
135 JmpCommonIdtEntry\r
136 \r
137INT10:\r
138; Invalid TSS causes an error code to be pushed so no phony push necessary\r
139 nop\r
140 nop\r
141 push 10\r
142 JmpCommonIdtEntry\r
143 \r
144INT11:\r
145; Segment Not Present causes an error code to be pushed so no phony push necessary\r
146 nop\r
147 nop\r
148 push 11\r
149 JmpCommonIdtEntry\r
150 \r
151INT12:\r
152; Stack fault causes an error code to be pushed so no phony push necessary\r
153 nop\r
154 nop\r
155 push 12\r
156 JmpCommonIdtEntry\r
157 \r
158INT13:\r
159; GP fault causes an error code to be pushed so no phony push necessary\r
160 nop\r
161 nop\r
162 push 13\r
163 JmpCommonIdtEntry\r
164 \r
165INT14:\r
166; Page fault causes an error code to be pushed so no phony push necessary\r
167 nop\r
168 nop\r
169 push 14\r
170 JmpCommonIdtEntry\r
171 \r
172INT15:\r
173 push 0h ; push error code place holder on the stack\r
174 push 15\r
175 JmpCommonIdtEntry\r
176 \r
177INT16:\r
178 push 0h ; push error code place holder on the stack\r
179 push 16\r
180 JmpCommonIdtEntry\r
181 \r
182INT17:\r
183; Alignment check causes an error code to be pushed so no phony push necessary\r
184 nop\r
185 nop\r
186 push 17\r
187 JmpCommonIdtEntry\r
188 \r
189INT18:\r
190 push 0h ; push error code place holder on the stack\r
191 push 18\r
192 JmpCommonIdtEntry\r
193 \r
194INT19:\r
195 push 0h ; push error code place holder on the stack\r
196 push 19\r
197 JmpCommonIdtEntry\r
198\r
199INTUnknown:\r
200REPEAT (32 - 20)\r
201 push 0h ; push error code place holder on the stack\r
202; push xxh ; push vector number\r
203 db 06ah\r
204 db ( $ - INTUnknown - 3 ) / 9 + 20 ; vector number\r
205 JmpCommonIdtEntry\r
206ENDM\r
207SystemExceptionHandler ENDP\r
208\r
209SystemTimerHandler PROC\r
210 push 0\r
211 push mTimerVector\r
212 JmpCommonIdtEntry\r
213SystemTimerHandler ENDP\r
214\r
215commonIdtEntry:\r
216; +---------------------+ <-- 16-byte aligned ensured by processor\r
217; + Old SS +\r
218; +---------------------+\r
219; + Old RSP +\r
220; +---------------------+\r
221; + RFlags +\r
222; +---------------------+\r
223; + CS +\r
224; +---------------------+\r
225; + RIP +\r
226; +---------------------+\r
227; + Error Code +\r
228; +---------------------+\r
229; + Vector Number +\r
230; +---------------------+\r
231; + RBP +\r
232; +---------------------+ <-- RBP, 16-byte aligned\r
233\r
234 cli\r
235 push rbp\r
236 mov rbp, rsp\r
237\r
238 ;\r
239 ; Since here the stack pointer is 16-byte aligned, so\r
240 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64\r
241 ; is 16-byte aligned\r
242 ; \r
243\r
244;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
245;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
246 push r15\r
247 push r14\r
248 push r13\r
249 push r12\r
250 push r11\r
251 push r10\r
252 push r9\r
253 push r8\r
254 push rax\r
255 push rcx\r
256 push rdx\r
257 push rbx\r
258 push qword ptr [rbp + 6 * 8] ; RSP\r
259 push qword ptr [rbp] ; RBP\r
260 push rsi\r
261 push rdi\r
262\r
263;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero\r
264 movzx rax, word ptr [rbp + 7 * 8]\r
265 push rax ; for ss\r
266 movzx rax, word ptr [rbp + 4 * 8]\r
267 push rax ; for cs\r
268 mov rax, ds\r
269 push rax\r
270 mov rax, es\r
271 push rax\r
272 mov rax, fs\r
273 push rax\r
274 mov rax, gs\r
275 push rax\r
276\r
277;; UINT64 Rip;\r
278 push qword ptr [rbp + 3 * 8]\r
279\r
280;; UINT64 Gdtr[2], Idtr[2];\r
281 sub rsp, 16\r
282 sidt fword ptr [rsp]\r
283 sub rsp, 16\r
284 sgdt fword ptr [rsp]\r
285\r
286;; UINT64 Ldtr, Tr;\r
287 xor rax, rax\r
288 str ax\r
289 push rax\r
290 sldt ax\r
291 push rax\r
292\r
293;; UINT64 RFlags;\r
294 push qword ptr [rbp + 5 * 8]\r
295\r
296;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
297 mov rax, cr8\r
298 push rax\r
299 mov rax, cr4\r
300 or rax, 208h\r
301 mov cr4, rax\r
302 push rax\r
303 mov rax, cr3\r
304 push rax\r
305 mov rax, cr2\r
306 push rax\r
307 xor rax, rax\r
308 push rax\r
309 mov rax, cr0\r
310 push rax\r
311\r
312;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
313 mov rax, dr7\r
314 push rax\r
315;; clear Dr7 while executing debugger itself\r
316 xor rax, rax\r
317 mov dr7, rax\r
318\r
319 mov rax, dr6\r
320 push rax\r
321;; insure all status bits in dr6 are clear...\r
322 xor rax, rax\r
323 mov dr6, rax\r
324\r
325 mov rax, dr3\r
326 push rax\r
327 mov rax, dr2\r
328 push rax\r
329 mov rax, dr1\r
330 push rax\r
331 mov rax, dr0\r
332 push rax\r
333\r
334;; FX_SAVE_STATE_X64 FxSaveState;\r
335\r
336 sub rsp, 512\r
337 mov rdi, rsp\r
338 db 0fh, 0aeh, 00000111y ;fxsave [rdi]\r
339\r
340;; UINT32 ExceptionData;\r
341 push qword ptr [rbp + 2 * 8]\r
342\r
343;; call into exception handler\r
344;; Prepare parameter and call\r
345 mov rcx, qword ptr [rbp + 1 * 8]\r
346 mov rdx, rsp\r
347 ;\r
348 ; Per X64 calling convention, allocate maximum parameter stack space\r
349 ; and make sure RSP is 16-byte aligned\r
350 ;\r
351 sub rsp, 4 * 8 + 8\r
352 cmp rcx, 32\r
353 jb CallException\r
354 call TimerHandler\r
355 jmp ExceptionDone\r
356CallException:\r
357 call ExceptionHandler\r
358ExceptionDone:\r
359 add rsp, 4 * 8 + 8\r
360\r
361 cli\r
362;; UINT64 ExceptionData;\r
363 add rsp, 8\r
364\r
365;; FX_SAVE_STATE_X64 FxSaveState;\r
366\r
367 mov rsi, rsp\r
368 db 0fh, 0aeh, 00001110y ; fxrstor [rsi]\r
369 add rsp, 512\r
370\r
371;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
372 pop rax\r
373 mov dr0, rax\r
374 pop rax\r
375 mov dr1, rax\r
376 pop rax\r
377 mov dr2, rax\r
378 pop rax\r
379 mov dr3, rax\r
380;; skip restore of dr6. We cleared dr6 during the context save.\r
381 add rsp, 8\r
382 pop rax\r
383 mov dr7, rax\r
384\r
385;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;\r
386 pop rax\r
387 mov cr0, rax\r
388 add rsp, 8 ; not for Cr1\r
389 pop rax\r
390 mov cr2, rax\r
391 pop rax\r
392 mov cr3, rax\r
393 pop rax\r
394 mov cr4, rax\r
395 pop rax\r
396 mov cr8, rax\r
397\r
398;; UINT64 RFlags;\r
399 pop qword ptr [rbp + 5 * 8]\r
400\r
401;; UINT64 Ldtr, Tr;\r
402;; UINT64 Gdtr[2], Idtr[2];\r
403;; Best not let anyone mess with these particular registers...\r
404 add rsp, 48\r
405\r
406;; UINT64 Rip;\r
407 pop qword ptr [rbp + 3 * 8]\r
408\r
409;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;\r
410 pop rax\r
411 ; mov gs, rax ; not for gs\r
412 pop rax\r
413 ; mov fs, rax ; not for fs\r
414 ; (X64 will not use fs and gs, so we do not restore it)\r
415 pop rax\r
416 mov es, rax\r
417 pop rax\r
418 mov ds, rax\r
419 pop qword ptr [rbp + 4 * 8] ; for cs\r
420 pop qword ptr [rbp + 7 * 8] ; for ss\r
421\r
422;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;\r
423;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;\r
424 pop rdi\r
425 pop rsi\r
426 add rsp, 8 ; not for rbp\r
427 pop qword ptr [rbp + 6 * 8] ; for rsp\r
428 pop rbx\r
429 pop rdx\r
430 pop rcx\r
431 pop rax\r
432 pop r8\r
433 pop r9\r
434 pop r10\r
435 pop r11\r
436 pop r12\r
437 pop r13\r
438 pop r14\r
439 pop r15\r
440\r
441 mov rsp, rbp\r
442 pop rbp\r
443 add rsp, 16\r
444 iretq\r
445\r
446;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
447; data\r
448;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
449\r
450 align 010h\r
451\r
452gdtr dw GDT_END - GDT_BASE - 1 ; GDT limit\r
453 dq 0 ; (GDT base gets set above)\r
454;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
455; global descriptor table (GDT)\r
456;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
457\r
458 align 010h\r
459\r
460public GDT_BASE\r
461GDT_BASE:\r
462; null descriptor\r
463NULL_SEL equ $-GDT_BASE ; Selector [0x0]\r
464 dw 0 ; limit 15:0\r
465 dw 0 ; base 15:0\r
466 db 0 ; base 23:16\r
467 db 0 ; type\r
468 db 0 ; limit 19:16, flags\r
469 db 0 ; base 31:24\r
470\r
471; linear data segment descriptor\r
472LINEAR_SEL equ $-GDT_BASE ; Selector [0x8]\r
473 dw 0FFFFh ; limit 0xFFFFF\r
474 dw 0 ; base 0\r
475 db 0\r
476 db 092h ; present, ring 0, data, expand-up, writable\r
477 db 0CFh ; page-granular, 32-bit\r
478 db 0\r
479\r
480; linear code segment descriptor\r
481LINEAR_CODE_SEL equ $-GDT_BASE ; Selector [0x10]\r
482 dw 0FFFFh ; limit 0xFFFFF\r
483 dw 0 ; base 0\r
484 db 0\r
485 db 09Ah ; present, ring 0, data, expand-up, writable\r
486 db 0CFh ; page-granular, 32-bit\r
487 db 0\r
488\r
489; system data segment descriptor\r
490SYS_DATA_SEL equ $-GDT_BASE ; Selector [0x18]\r
491 dw 0FFFFh ; limit 0xFFFFF\r
492 dw 0 ; base 0\r
493 db 0\r
494 db 092h ; present, ring 0, data, expand-up, writable\r
495 db 0CFh ; page-granular, 32-bit\r
496 db 0\r
497\r
498; system code segment descriptor\r
499SYS_CODE_SEL equ $-GDT_BASE ; Selector [0x20]\r
500 dw 0FFFFh ; limit 0xFFFFF\r
501 dw 0 ; base 0\r
502 db 0\r
503 db 09Ah ; present, ring 0, data, expand-up, writable\r
504 db 0CFh ; page-granular, 32-bit\r
505 db 0\r
506\r
507; spare segment descriptor\r
508SPARE3_SEL equ $-GDT_BASE ; Selector [0x28]\r
509 dw 0 ; limit 0xFFFFF\r
510 dw 0 ; base 0\r
511 db 0\r
512 db 0 ; present, ring 0, data, expand-up, writable\r
513 db 0 ; page-granular, 32-bit\r
514 db 0\r
515\r
516;\r
517; system data segment descriptor\r
518;\r
519SYS_DATA64_SEL equ $-GDT_BASE ; Selector [0x30]\r
520 dw 0FFFFh ; limit 0xFFFFF\r
521 dw 0 ; base 0\r
522 db 0\r
523 db 092h ; P | DPL [1..2] | 1 | 1 | C | R | A\r
524 db 0CFh ; G | D | L | AVL | Segment [19..16]\r
525 db 0\r
526\r
527;\r
528; system code segment descriptor\r
529;\r
530SYS_CODE64_SEL equ $-GDT_BASE ; Selector [0x38]\r
531 dw 0FFFFh ; limit 0xFFFFF\r
532 dw 0 ; base 0\r
533 db 0\r
534 db 09Ah ; P | DPL [1..2] | 1 | 1 | C | R | A\r
535 db 0AFh ; G | D | L | AVL | Segment [19..16]\r
536 db 0\r
537\r
538; spare segment descriptor\r
539SPARE4_SEL equ $-GDT_BASE ; Selector [0x40]\r
540 dw 0 ; limit 0xFFFFF\r
541 dw 0 ; base 0\r
542 db 0\r
543 db 0 ; present, ring 0, data, expand-up, writable\r
544 db 0 ; page-granular, 32-bit\r
545 db 0\r
546\r
547GDT_END:\r
548\r
549 align 02h\r
550\r
551\r
552\r
553idtr dw IDT_END - IDT_BASE - 1 ; IDT limit\r
554 dq 0 ; (IDT base gets set above)\r
555\r
556;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
557; interrupt descriptor table (IDT)\r
558;\r
559; Note: The hardware IRQ's specified in this table are the normal PC/AT IRQ\r
560; mappings. This implementation only uses the system timer and all other\r
561; IRQs will remain masked. The descriptors for vectors 33+ are provided\r
562; for convenience.\r
563;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;\r
564\r
565;idt_tag db "IDT",0 \r
566 align 02h\r
567\r
568public IDT_BASE\r
569IDT_BASE:\r
570; divide by zero (INT 0)\r
571DIV_ZERO_SEL equ $-IDT_BASE\r
572 dw 0 ; offset 15:0\r
573 dw SYS_CODE64_SEL ; selector 15:0\r
574 db 0 ; 0 for interrupt gate\r
575 db 0eh OR 80h ; type = 386 interrupt gate, present\r
576 dw 0 ; offset 31:16\r
577 dd 0 ; offset 63:32\r
578 dd 0 ; 0 for reserved\r
579\r
580; debug exception (INT 1)\r
581DEBUG_EXCEPT_SEL equ $-IDT_BASE\r
582 dw 0 ; offset 15:0\r
583 dw SYS_CODE64_SEL ; selector 15:0\r
584 db 0 ; 0 for interrupt gate\r
585 db 0eh OR 80h ; type = 386 interrupt gate, present\r
586 dw 0 ; offset 31:16\r
587 dd 0 ; offset 63:32\r
588 dd 0 ; 0 for reserved\r
589\r
590; NMI (INT 2)\r
591NMI_SEL equ $-IDT_BASE\r
592 dw 0 ; offset 15:0\r
593 dw SYS_CODE64_SEL ; selector 15:0\r
594 db 0 ; 0 for interrupt gate\r
595 db 0eh OR 80h ; type = 386 interrupt gate, present\r
596 dw 0 ; offset 31:16\r
597 dd 0 ; offset 63:32\r
598 dd 0 ; 0 for reserved\r
599\r
600; soft breakpoint (INT 3)\r
601BREAKPOINT_SEL equ $-IDT_BASE\r
602 dw 0 ; offset 15:0\r
603 dw SYS_CODE64_SEL ; selector 15:0\r
604 db 0 ; 0 for interrupt gate\r
605 db 0eh OR 80h ; type = 386 interrupt gate, present\r
606 dw 0 ; offset 31:16\r
607 dd 0 ; offset 63:32\r
608 dd 0 ; 0 for reserved\r
609\r
610; overflow (INT 4)\r
611OVERFLOW_SEL equ $-IDT_BASE\r
612 dw 0 ; offset 15:0\r
613 dw SYS_CODE64_SEL ; selector 15:0\r
614 db 0 ; 0 for interrupt gate\r
615 db 0eh OR 80h ; type = 386 interrupt gate, present\r
616 dw 0 ; offset 31:16\r
617 dd 0 ; offset 63:32\r
618 dd 0 ; 0 for reserved\r
619\r
620; bounds check (INT 5)\r
621BOUNDS_CHECK_SEL equ $-IDT_BASE\r
622 dw 0 ; offset 15:0\r
623 dw SYS_CODE64_SEL ; selector 15:0\r
624 db 0 ; 0 for interrupt gate\r
625 db 0eh OR 80h ; type = 386 interrupt gate, present\r
626 dw 0 ; offset 31:16\r
627 dd 0 ; offset 63:32\r
628 dd 0 ; 0 for reserved\r
629\r
630; invalid opcode (INT 6)\r
631INVALID_OPCODE_SEL equ $-IDT_BASE\r
632 dw 0 ; offset 15:0\r
633 dw SYS_CODE64_SEL ; selector 15:0\r
634 db 0 ; 0 for interrupt gate\r
635 db 0eh OR 80h ; type = 386 interrupt gate, present\r
636 dw 0 ; offset 31:16\r
637 dd 0 ; offset 63:32\r
638 dd 0 ; 0 for reserved\r
639\r
640; device not available (INT 7)\r
641DEV_NOT_AVAIL_SEL equ $-IDT_BASE\r
642 dw 0 ; offset 15:0\r
643 dw SYS_CODE64_SEL ; selector 15:0\r
644 db 0 ; 0 for interrupt gate\r
645 db 0eh OR 80h ; type = 386 interrupt gate, present\r
646 dw 0 ; offset 31:16\r
647 dd 0 ; offset 63:32\r
648 dd 0 ; 0 for reserved\r
649\r
650; double fault (INT 8)\r
651DOUBLE_FAULT_SEL equ $-IDT_BASE\r
652 dw 0 ; offset 15:0\r
653 dw SYS_CODE64_SEL ; selector 15:0\r
654 db 0 ; 0 for interrupt gate\r
655 db 0eh OR 80h ; type = 386 interrupt gate, present\r
656 dw 0 ; offset 31:16\r
657 dd 0 ; offset 63:32\r
658 dd 0 ; 0 for reserved\r
659\r
660; Coprocessor segment overrun - reserved (INT 9)\r
661RSVD_INTR_SEL1 equ $-IDT_BASE\r
662 dw 0 ; offset 15:0\r
663 dw SYS_CODE64_SEL ; selector 15:0\r
664 db 0 ; 0 for interrupt gate\r
665 db 0eh OR 80h ; type = 386 interrupt gate, present\r
666 dw 0 ; offset 31:16\r
667 dd 0 ; offset 63:32\r
668 dd 0 ; 0 for reserved\r
669\r
670; invalid TSS (INT 0ah)\r
671INVALID_TSS_SEL equ $-IDT_BASE\r
672 dw 0 ; offset 15:0\r
673 dw SYS_CODE64_SEL ; selector 15:0\r
674 db 0 ; 0 for interrupt gate\r
675 db 0eh OR 80h ; type = 386 interrupt gate, present\r
676 dw 0 ; offset 31:16\r
677 dd 0 ; offset 63:32\r
678 dd 0 ; 0 for reserved\r
679\r
680; segment not present (INT 0bh)\r
681SEG_NOT_PRESENT_SEL equ $-IDT_BASE\r
682 dw 0 ; offset 15:0\r
683 dw SYS_CODE64_SEL ; selector 15:0\r
684 db 0 ; 0 for interrupt gate\r
685 db 0eh OR 80h ; type = 386 interrupt gate, present\r
686 dw 0 ; offset 31:16\r
687 dd 0 ; offset 63:32\r
688 dd 0 ; 0 for reserved\r
689\r
690; stack fault (INT 0ch)\r
691STACK_FAULT_SEL equ $-IDT_BASE\r
692 dw 0 ; offset 15:0\r
693 dw SYS_CODE64_SEL ; selector 15:0\r
694 db 0 ; 0 for interrupt gate\r
695 db 0eh OR 80h ; type = 386 interrupt gate, present\r
696 dw 0 ; offset 31:16\r
697 dd 0 ; offset 63:32\r
698 dd 0 ; 0 for reserved\r
699\r
700; general protection (INT 0dh)\r
701GP_FAULT_SEL equ $-IDT_BASE\r
702 dw 0 ; offset 15:0\r
703 dw SYS_CODE64_SEL ; selector 15:0\r
704 db 0 ; 0 for interrupt gate\r
705 db 0eh OR 80h ; type = 386 interrupt gate, present\r
706 dw 0 ; offset 31:16\r
707 dd 0 ; offset 63:32\r
708 dd 0 ; 0 for reserved\r
709\r
710; page fault (INT 0eh)\r
711PAGE_FAULT_SEL equ $-IDT_BASE\r
712 dw 0 ; offset 15:0\r
713 dw SYS_CODE64_SEL ; selector 15:0\r
714 db 0 ; 0 for interrupt gate\r
715 db 0eh OR 80h ; type = 386 interrupt gate, present\r
716 dw 0 ; offset 31:16\r
717 dd 0 ; offset 63:32\r
718 dd 0 ; 0 for reserved\r
719\r
720; Intel reserved - do not use (INT 0fh)\r
721RSVD_INTR_SEL2 equ $-IDT_BASE\r
722 dw 0 ; offset 15:0\r
723 dw SYS_CODE64_SEL ; selector 15:0\r
724 db 0 ; 0 for interrupt gate\r
725 db 0eh OR 80h ; type = 386 interrupt gate, present\r
726 dw 0 ; offset 31:16\r
727 dd 0 ; offset 63:32\r
728 dd 0 ; 0 for reserved\r
729\r
730; floating point error (INT 10h)\r
731FLT_POINT_ERR_SEL equ $-IDT_BASE\r
732 dw 0 ; offset 15:0\r
733 dw SYS_CODE64_SEL ; selector 15:0\r
734 db 0 ; 0 for interrupt gate\r
735 db 0eh OR 80h ; type = 386 interrupt gate, present\r
736 dw 0 ; offset 31:16\r
737 dd 0 ; offset 63:32\r
738 dd 0 ; 0 for reserved\r
739\r
740; alignment check (INT 11h)\r
741ALIGNMENT_CHECK_SEL equ $-IDT_BASE\r
742 dw 0 ; offset 15:0\r
743 dw SYS_CODE64_SEL ; selector 15:0\r
744 db 0 ; 0 for interrupt gate\r
745 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
746 dw 0 ; offset 31:16\r
747 dd 0 ; offset 63:32\r
748 dd 0 ; 0 for reserved\r
749\r
750; machine check (INT 12h)\r
751MACHINE_CHECK_SEL equ $-IDT_BASE\r
752 dw 0 ; offset 15:0\r
753 dw SYS_CODE64_SEL ; selector 15:0\r
754 db 0 ; 0 for interrupt gate\r
755 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
756 dw 0 ; offset 31:16\r
757 dd 0 ; offset 63:32\r
758 dd 0 ; 0 for reserved\r
759\r
760; SIMD floating-point exception (INT 13h)\r
761SIMD_EXCEPTION_SEL equ $-IDT_BASE\r
762 dw 0 ; offset 15:0\r
763 dw SYS_CODE64_SEL ; selector 15:0\r
764 db 0 ; 0 for interrupt gate\r
765 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
766 dw 0 ; offset 31:16\r
767 dd 0 ; offset 63:32\r
768 dd 0 ; 0 for reserved\r
769\r
770REPEAT (32 - 20)\r
771 dw 0 ; offset 15:0\r
772 dw SYS_CODE64_SEL ; selector 15:0\r
773 db 0 ; 0 for interrupt gate\r
774 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
775 dw 0 ; offset 31:16\r
776 dd 0 ; offset 63:32\r
777 dd 0 ; 0 for reserved\r
778ENDM\r
779\r
780; 72 unspecified descriptors\r
781 db (72 * 16) dup(0)\r
782 \r
783; IRQ 0 (System timer) - (INT 68h)\r
784IRQ0_SEL equ $-IDT_BASE\r
785 dw 0 ; offset 15:0\r
786 dw SYS_CODE64_SEL ; selector 15:0\r
787 db 0 ; 0 for interrupt gate\r
788 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
789 dw 0 ; offset 31:16\r
790 dd 0 ; offset 63:32\r
791 dd 0 ; 0 for reserved\r
792\r
793; IRQ 1 (8042 Keyboard controller) - (INT 69h)\r
794IRQ1_SEL equ $-IDT_BASE\r
795 dw 0 ; offset 15:0\r
796 dw SYS_CODE64_SEL ; selector 15:0\r
797 db 0 ; 0 for interrupt gate\r
798 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
799 dw 0 ; offset 31:16\r
800 dd 0 ; offset 63:32\r
801 dd 0 ; 0 for reserved\r
802\r
803; Reserved - IRQ 2 redirect (IRQ 2) - DO NOT USE!!! - (INT 6ah)\r
804IRQ2_SEL equ $-IDT_BASE\r
805 dw 0 ; offset 15:0\r
806 dw SYS_CODE64_SEL ; selector 15:0\r
807 db 0 ; 0 for interrupt gate\r
808 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
809 dw 0 ; offset 31:16\r
810 dd 0 ; offset 63:32\r
811 dd 0 ; 0 for reserved\r
812\r
813; IRQ 3 (COM 2) - (INT 6bh)\r
814IRQ3_SEL equ $-IDT_BASE\r
815 dw 0 ; offset 15:0\r
816 dw SYS_CODE64_SEL ; selector 15:0\r
817 db 0 ; 0 for interrupt gate\r
818 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
819 dw 0 ; offset 31:16\r
820 dd 0 ; offset 63:32\r
821 dd 0 ; 0 for reserved\r
822\r
823; IRQ 4 (COM 1) - (INT 6ch)\r
824IRQ4_SEL equ $-IDT_BASE\r
825 dw 0 ; offset 15:0\r
826 dw SYS_CODE64_SEL ; selector 15:0\r
827 db 0 ; 0 for interrupt gate\r
828 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
829 dw 0 ; offset 31:16\r
830 dd 0 ; offset 63:32\r
831 dd 0 ; 0 for reserved\r
832\r
833; IRQ 5 (LPT 2) - (INT 6dh)\r
834IRQ5_SEL equ $-IDT_BASE\r
835 dw 0 ; offset 15:0\r
836 dw SYS_CODE64_SEL ; selector 15:0\r
837 db 0 ; 0 for interrupt gate\r
838 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
839 dw 0 ; offset 31:16\r
840 dd 0 ; offset 63:32\r
841 dd 0 ; 0 for reserved\r
842\r
843; IRQ 6 (Floppy controller) - (INT 6eh)\r
844IRQ6_SEL equ $-IDT_BASE\r
845 dw 0 ; offset 15:0\r
846 dw SYS_CODE64_SEL ; selector 15:0\r
847 db 0 ; 0 for interrupt gate\r
848 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
849 dw 0 ; offset 31:16\r
850 dd 0 ; offset 63:32\r
851 dd 0 ; 0 for reserved\r
852\r
853; IRQ 7 (LPT 1) - (INT 6fh)\r
854IRQ7_SEL equ $-IDT_BASE\r
855 dw 0 ; offset 15:0\r
856 dw SYS_CODE64_SEL ; selector 15:0\r
857 db 0 ; 0 for interrupt gate\r
858 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
859 dw 0 ; offset 31:16\r
860 dd 0 ; offset 63:32\r
861 dd 0 ; 0 for reserved\r
862\r
863; IRQ 8 (RTC Alarm) - (INT 70h)\r
864IRQ8_SEL equ $-IDT_BASE\r
865 dw 0 ; offset 15:0\r
866 dw SYS_CODE64_SEL ; selector 15:0\r
867 db 0 ; 0 for interrupt gate\r
868 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
869 dw 0 ; offset 31:16\r
870 dd 0 ; offset 63:32\r
871 dd 0 ; 0 for reserved\r
872\r
873; IRQ 9 - (INT 71h)\r
874IRQ9_SEL equ $-IDT_BASE\r
875 dw 0 ; offset 15:0\r
876 dw SYS_CODE64_SEL ; selector 15:0\r
877 db 0 ; 0 for interrupt gate\r
878 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
879 dw 0 ; offset 31:16\r
880 dd 0 ; offset 63:32\r
881 dd 0 ; 0 for reserved\r
882\r
883; IRQ 10 - (INT 72h)\r
884IRQ10_SEL equ $-IDT_BASE\r
885 dw 0 ; offset 15:0\r
886 dw SYS_CODE64_SEL ; selector 15:0\r
887 db 0 ; 0 for interrupt gate\r
888 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
889 dw 0 ; offset 31:16\r
890 dd 0 ; offset 63:32\r
891 dd 0 ; 0 for reserved\r
892\r
893; IRQ 11 - (INT 73h)\r
894IRQ11_SEL equ $-IDT_BASE\r
895 dw 0 ; offset 15:0\r
896 dw SYS_CODE64_SEL ; selector 15:0\r
897 db 0 ; 0 for interrupt gate\r
898 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
899 dw 0 ; offset 31:16\r
900 dd 0 ; offset 63:32\r
901 dd 0 ; 0 for reserved\r
902\r
903; IRQ 12 (PS/2 mouse) - (INT 74h)\r
904IRQ12_SEL equ $-IDT_BASE\r
905 dw 0 ; offset 15:0\r
906 dw SYS_CODE64_SEL ; selector 15:0\r
907 db 0 ; 0 for interrupt gate\r
908 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
909 dw 0 ; offset 31:16\r
910 dd 0 ; offset 63:32\r
911 dd 0 ; 0 for reserved\r
912\r
913; IRQ 13 (Floating point error) - (INT 75h)\r
914IRQ13_SEL equ $-IDT_BASE\r
915 dw 0 ; offset 15:0\r
916 dw SYS_CODE64_SEL ; selector 15:0\r
917 db 0 ; 0 for interrupt gate\r
918 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
919 dw 0 ; offset 31:16\r
920 dd 0 ; offset 63:32\r
921 dd 0 ; 0 for reserved\r
922\r
923; IRQ 14 (Secondary IDE) - (INT 76h)\r
924IRQ14_SEL equ $-IDT_BASE\r
925 dw 0 ; offset 15:0\r
926 dw SYS_CODE64_SEL ; selector 15:0\r
927 db 0 ; 0 for interrupt gate\r
928 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
929 dw 0 ; offset 31:16\r
930 dd 0 ; offset 63:32\r
931 dd 0 ; 0 for reserved\r
932\r
933; IRQ 15 (Primary IDE) - (INT 77h)\r
934IRQ15_SEL equ $-IDT_BASE\r
935 dw 0 ; offset 15:0\r
936 dw SYS_CODE64_SEL ; selector 15:0\r
937 db 0 ; 0 for interrupt gate\r
938 db 0eh OR 80h ; (10001110)type = 386 interrupt gate, present\r
939 dw 0 ; offset 31:16\r
940 dd 0 ; offset 63:32\r
941 dd 0 ; 0 for reserved\r
942\r
943 db (1 * 16) dup(0)\r
944\r
945IDT_END:\r
946\r
947 align 02h\r
948\r
949END\r
EFI Development Kit II mirror for PVE