[mirror_edk2.git] / DuetPkg / PciRootBridgeNoEnumerationDxe / PcatPciRootBridge.h

/*++\r
\r
Copyright (c) 2005 - 2006, Intel Corporation                                                         \r
All rights reserved. This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
  PcatPciRootBridge.h\r
\r
Abstract:\r
\r
  The driver for the host to pci bridge (root bridge).\r
\r
--*/\r
\r
#ifndef _PCAT_PCI_ROOT_BRIDGE_H_\r
#define _PCAT_PCI_ROOT_BRIDGE_H_\r
\r
#include <PiDxe.h>\r
#include <Protocol/PciRootBridgeIo.h>\r
#include <Protocol/DeviceIo.h>\r
#include <Protocol/CpuIo.h>\r
\r
#include <Library/UefiLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DevicePathLib.h>\r
#include <Library/HobLib.h>\r
\r
#include <Guid/PciOptionRomTable.h>\r
#include <Guid/HobList.h>\r
#include <Guid/PciExpressBaseAddress.h>\r
\r
#include <IndustryStandard/Acpi.h>\r
#include <IndustryStandard/Pci.h>\r
//\r
// Driver Instance Data Prototypes\r
//\r
#define PCAT_PCI_ROOT_BRIDGE_SIGNATURE  EFI_SIGNATURE_32('p', 'c', 'r', 'b')\r
\r
typedef struct {\r
  UINT32                            Signature;\r
  EFI_HANDLE                        Handle;\r
                                    \r
  EFI_DEVICE_PATH_PROTOCOL          *DevicePath;\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL   Io;\r
  EFI_CPU_IO_PROTOCOL               *CpuIo;\r
\r
  UINT32                            RootBridgeNumber;\r
  UINT32                            PrimaryBus;\r
  UINT32                            SubordinateBus;\r
                                     \r
  UINT64                            MemBase;     // Offsets host to bus memory addr.\r
  UINT64                            MemLimit;    // Max allowable memory access\r
                                    \r
  UINT64                            IoBase;      // Offsets host to bus io addr.\r
  UINT64                            IoLimit;     // Max allowable io access\r
                                    \r
  UINT64                            PciAddress;\r
  UINT64                            PciData;\r
                                    \r
  UINT64                            PhysicalMemoryBase;\r
  UINT64                            PhysicalIoBase;\r
                                     \r
  EFI_LOCK                          PciLock;\r
                                    \r
  UINT64                            Attributes;\r
                                    \r
  UINT64                            Mem32Base;\r
  UINT64                            Mem32Limit;\r
  UINT64                            Pmem32Base;\r
  UINT64                            Pmem32Limit;\r
  UINT64                            Mem64Base;\r
  UINT64                            Mem64Limit;\r
  UINT64                            Pmem64Base;\r
  UINT64                            Pmem64Limit;\r
\r
  UINT64                            PciExpressBaseAddress;\r
\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
\r
  LIST_ENTRY                    MapInfo;\r
} PCAT_PCI_ROOT_BRIDGE_INSTANCE;\r
\r
//\r
// Driver Instance Data Macros\r
//\r
#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r
  CR(a, PCAT_PCI_ROOT_BRIDGE_INSTANCE, Io, PCAT_PCI_ROOT_BRIDGE_SIGNATURE)\r
\r
//\r
// Private data types\r
//\r
typedef union {\r
  UINT8   volatile  *buf;\r
  UINT8   volatile  *ui8;\r
  UINT16  volatile  *ui16;\r
  UINT32  volatile  *ui32;\r
  UINT64  volatile  *ui64;\r
  UINTN   volatile  ui;\r
} PTR;\r
\r
typedef struct {\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION  Operation;\r
  UINTN                                      NumberOfBytes;\r
  UINTN                                      NumberOfPages;\r
  EFI_PHYSICAL_ADDRESS                       HostAddress;\r
  EFI_PHYSICAL_ADDRESS                       MappedHostAddress;\r
} MAP_INFO;\r
\r
typedef struct {\r
  LIST_ENTRY Link;\r
  MAP_INFO * Map;  \r
} MAP_INFO_INSTANCE;\r
\r
typedef\r
VOID\r
(*EFI_PCI_BUS_SCAN_CALLBACK) (\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev,\r
  UINT16                           MinBus,\r
  UINT16                           MaxBus,\r
  UINT16                           MinDevice,\r
  UINT16                           MaxDevice,\r
  UINT16                           MinFunc,\r
  UINT16                           MaxFunc,\r
  UINT16                           Bus,\r
  UINT16                           Device,\r
  UINT16                           Func,\r
  IN VOID                          *Context\r
  );\r
\r
typedef struct {\r
  UINT16                    *CommandRegisterBuffer;\r
  UINT32                    PpbMemoryWindow;     \r
} PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT;\r
\r
typedef struct {\r
  UINT8 Register;\r
  UINT8 Function;\r
  UINT8 Device;\r
  UINT8 Bus;\r
  UINT8 Reserved[4];\r
} DEFIO_PCI_ADDR;\r
\r
//\r
// Driver Protocol Constructor Prototypes\r
//\r
EFI_STATUS \r
ConstructConfiguration(\r
  IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE  *PrivateData\r
  );\r
\r
EFI_STATUS\r
PcatPciRootBridgeParseBars (\r
  IN PCAT_PCI_ROOT_BRIDGE_INSTANCE  *PrivateData,\r
  IN UINT16                         Command,\r
  IN UINTN                          Bus,\r
  IN UINTN                          Device,\r
  IN UINTN                          Function\r
  );\r
\r
EFI_STATUS\r
ScanPciRootBridgeForRoms(\r
  EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *IoDev\r
  );\r
\r
EFI_STATUS\r
PcatRootBridgeDevicePathConstructor (\r
  IN EFI_DEVICE_PATH_PROTOCOL  **Protocol,\r
  IN UINTN                     RootBridgeNumber,\r
  IN BOOLEAN                   IsPciExpress\r
  );\r
\r
EFI_STATUS\r
PcatRootBridgeIoConstructor (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL  *Protocol,\r
  IN UINTN                            SegmentNumber\r
  );\r
\r
EFI_STATUS\r
PcatRootBridgeIoGetIoPortMapping (\r
  OUT EFI_PHYSICAL_ADDRESS  *IoPortMapping,\r
  OUT EFI_PHYSICAL_ADDRESS  *MemoryPortMapping\r
  );\r
\r
EFI_STATUS\r
PcatRootBridgeIoPciRW (\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL        *This,\r
  IN BOOLEAN                                Write,\r
  IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH  Width,\r
  IN UINT64                                 UserAddress,\r
  IN UINTN                                  Count,\r
  IN OUT VOID                               *UserBuffer\r
  );\r
\r
UINT64\r
GetPciExpressBaseAddressForRootBridge (\r
  IN UINTN    HostBridgeNumber,\r
  IN UINTN    RootBridgeNumber\r
  );\r
\r
//\r
// Driver entry point prototype\r
//\r
EFI_STATUS\r
EFIAPI\r
InitializePcatPciRootBridge (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  );\r
\r
extern EFI_CPU_IO_PROTOCOL  *gCpuIo;\r
\r
#endif\r
Commit	Line	Data
c69dd9df	1	/*++\r
	2	\r
	3	Copyright (c) 2005 - 2006, Intel Corporation \r
	4	All rights reserved. This program and the accompanying materials \r
	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	PcatPciRootBridge.h\r
	14	\r
	15	Abstract:\r
	16	\r
	17	The driver for the host to pci bridge (root bridge).\r
	18	\r
	19	--*/\r
	20	\r
	21	#ifndef _PCAT_PCI_ROOT_BRIDGE_H_\r
	22	#define _PCAT_PCI_ROOT_BRIDGE_H_\r
	23	\r
	24	#include <PiDxe.h>\r
	25	#include <Protocol/PciRootBridgeIo.h>\r
	26	#include <Protocol/DeviceIo.h>\r
	27	#include <Protocol/CpuIo.h>\r
	28	\r
	29	#include <Library/UefiLib.h>\r
	30	#include <Library/BaseLib.h>\r
	31	#include <Library/MemoryAllocationLib.h>\r
	32	#include <Library/UefiBootServicesTableLib.h>\r
	33	#include <Library/DebugLib.h>\r
	34	#include <Library/BaseMemoryLib.h>\r
	35	#include <Library/DevicePathLib.h>\r
	36	#include <Library/HobLib.h>\r
	37	\r
	38	#include <Guid/PciOptionRomTable.h>\r
	39	#include <Guid/HobList.h>\r
	40	#include <Guid/PciExpressBaseAddress.h>\r
	41	\r
	42	#include <IndustryStandard/Acpi.h>\r
	43	#include <IndustryStandard/Pci.h>\r
	44	//\r
	45	// Driver Instance Data Prototypes\r
	46	//\r
	47	#define PCAT_PCI_ROOT_BRIDGE_SIGNATURE EFI_SIGNATURE_32('p', 'c', 'r', 'b')\r
	48	\r
	49	typedef struct {\r
	50	UINT32 Signature;\r
	51	EFI_HANDLE Handle;\r
	52	\r
	53	EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
	54	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;\r
	55	EFI_CPU_IO_PROTOCOL *CpuIo;\r
	56	\r
	57	UINT32 RootBridgeNumber;\r
	58	UINT32 PrimaryBus;\r
	59	UINT32 SubordinateBus;\r
	60	\r
	61	UINT64 MemBase; // Offsets host to bus memory addr.\r
	62	UINT64 MemLimit; // Max allowable memory access\r
	63	\r
	64	UINT64 IoBase; // Offsets host to bus io addr.\r
65	UINT64 IoLimit; // Max allowable io access\r
66	\r
67	UINT64 PciAddress;\r
68	UINT64 PciData;\r
69	\r
70	UINT64 PhysicalMemoryBase;\r
71	UINT64 PhysicalIoBase;\r
72	\r
73	EFI_LOCK PciLock;\r
74	\r
75	UINT64 Attributes;\r
76	\r
77	UINT64 Mem32Base;\r
78	UINT64 Mem32Limit;\r
79	UINT64 Pmem32Base;\r
80	UINT64 Pmem32Limit;\r
81	UINT64 Mem64Base;\r
82	UINT64 Mem64Limit;\r
83	UINT64 Pmem64Base;\r
84	UINT64 Pmem64Limit;\r
85	\r
86	UINT64 PciExpressBaseAddress;\r
87	\r
88	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
89	\r
90	LIST_ENTRY MapInfo;\r
91	} PCAT_PCI_ROOT_BRIDGE_INSTANCE;\r
92	\r
93	//\r
94	// Driver Instance Data Macros\r
95	//\r
96	#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \\r
97	CR(a, PCAT_PCI_ROOT_BRIDGE_INSTANCE, Io, PCAT_PCI_ROOT_BRIDGE_SIGNATURE)\r
98	\r
c69dd9df	99	//\r
	100	// Private data types\r
	101	//\r
	102	typedef union {\r
e1cdd2eb	103	UINT8 volatile *buf;\r
	104	UINT8 volatile *ui8;\r
	105	UINT16 volatile *ui16;\r
	106	UINT32 volatile *ui32;\r
	107	UINT64 volatile *ui64;\r
	108	UINTN volatile ui;\r
c69dd9df	109	} PTR;\r
	110	\r
	111	typedef struct {\r
	112	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;\r
	113	UINTN NumberOfBytes;\r
	114	UINTN NumberOfPages;\r
	115	EFI_PHYSICAL_ADDRESS HostAddress;\r
	116	EFI_PHYSICAL_ADDRESS MappedHostAddress;\r
	117	} MAP_INFO;\r
	118	\r
	119	typedef struct {\r
	120	LIST_ENTRY Link;\r
	121	MAP_INFO * Map; \r
	122	} MAP_INFO_INSTANCE;\r
	123	\r
	124	typedef\r
	125	VOID\r
	126	(*EFI_PCI_BUS_SCAN_CALLBACK) (\r
	127	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev,\r
	128	UINT16 MinBus,\r
	129	UINT16 MaxBus,\r
	130	UINT16 MinDevice,\r
	131	UINT16 MaxDevice,\r
	132	UINT16 MinFunc,\r
	133	UINT16 MaxFunc,\r
	134	UINT16 Bus,\r
	135	UINT16 Device,\r
	136	UINT16 Func,\r
	137	IN VOID *Context\r
	138	);\r
	139	\r
	140	typedef struct {\r
	141	UINT16 *CommandRegisterBuffer;\r
	142	UINT32 PpbMemoryWindow; \r
	143	} PCAT_PCI_ROOT_BRIDGE_SCAN_FOR_ROM_CONTEXT;\r
	144	\r
8ad48840	145	typedef struct {\r
	146	UINT8 Register;\r
	147	UINT8 Function;\r
	148	UINT8 Device;\r
	149	UINT8 Bus;\r
	150	UINT8 Reserved[4];\r
	151	} DEFIO_PCI_ADDR;\r
	152	\r
c69dd9df	153	//\r
	154	// Driver Protocol Constructor Prototypes\r
	155	//\r
	156	EFI_STATUS \r
	157	ConstructConfiguration(\r
	158	IN OUT PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData\r
	159	);\r
	160	\r
	161	EFI_STATUS\r
	162	PcatPciRootBridgeParseBars (\r
	163	IN PCAT_PCI_ROOT_BRIDGE_INSTANCE *PrivateData,\r
	164	IN UINT16 Command,\r
	165	IN UINTN Bus,\r
	166	IN UINTN Device,\r
	167	IN UINTN Function\r
	168	);\r
	169	\r
	170	EFI_STATUS\r
	171	ScanPciRootBridgeForRoms(\r
	172	EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *IoDev\r
	173	);\r
	174	\r
	175	EFI_STATUS\r
	176	PcatRootBridgeDevicePathConstructor (\r
	177	IN EFI_DEVICE_PATH_PROTOCOL **Protocol,\r
	178	IN UINTN RootBridgeNumber,\r
	179	IN BOOLEAN IsPciExpress\r
	180	);\r
	181	\r
	182	EFI_STATUS\r
	183	PcatRootBridgeIoConstructor (\r
	184	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,\r
	185	IN UINTN SegmentNumber\r
	186	);\r
	187	\r
	188	EFI_STATUS\r
	189	PcatRootBridgeIoGetIoPortMapping (\r
	190	OUT EFI_PHYSICAL_ADDRESS *IoPortMapping,\r
	191	OUT EFI_PHYSICAL_ADDRESS *MemoryPortMapping\r
	192	);\r
	193	\r
	194	EFI_STATUS\r
	195	PcatRootBridgeIoPciRW (\r
	196	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,\r
	197	IN BOOLEAN Write,\r
	198	IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r
	199	IN UINT64 UserAddress,\r
	200	IN UINTN Count,\r
	201	IN OUT VOID *UserBuffer\r
	202	);\r
	203	\r
	204	UINT64\r
	205	GetPciExpressBaseAddressForRootBridge (\r
	206	IN UINTN HostBridgeNumber,\r
	207	IN UINTN RootBridgeNumber\r
	208	);\r
	209	\r
	210	//\r
	211	// Driver entry point prototype\r
	212	//\r
	213	EFI_STATUS\r
	214	EFIAPI\r
	215	InitializePcatPciRootBridge (\r
	216	IN EFI_HANDLE ImageHandle,\r
217	IN EFI_SYSTEM_TABLE *SystemTable\r
218	);\r
219	\r
220	extern EFI_CPU_IO_PROTOCOL *gCpuIo;\r
221	\r
222	#endif\r