UefiCpuPkg CpuCommFeaturesLib: Fix GP fault issue about ProcTrace

[mirror_edk2.git] / DynamicTablesPkg / Include / ArmNameSpaceObjects.h

/** @file\r
\r
  Copyright (c) 2017 - 2019, ARM Limited. All rights reserved.\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Glossary:\r
    - Cm or CM   - Configuration Manager\r
    - Obj or OBJ - Object\r
    - Std or STD - Standard\r
**/\r
\r
#ifndef ARM_NAMESPACE_OBJECTS_H_\r
#define ARM_NAMESPACE_OBJECTS_H_\r
\r
#include <StandardNameSpaceObjects.h>\r
\r
#pragma pack(1)\r
\r
/** The EARM_OBJECT_ID enum describes the Object IDs\r
    in the ARM Namespace\r
*/\r
typedef enum ArmObjectID {\r
  EArmObjReserved,                    ///<  0 - Reserved\r
  EArmObjBootArchInfo,                ///<  1 - Boot Architecture Info\r
  EArmObjCpuInfo,                     ///<  2 - CPU Info\r
  EArmObjPowerManagementProfileInfo,  ///<  3 - Power Management Profile Info\r
  EArmObjGicCInfo,                    ///<  4 - GIC CPU Interface Info\r
  EArmObjGicDInfo,                    ///<  5 - GIC Distributor Info\r
  EArmObjGicMsiFrameInfo,             ///<  6 - GIC MSI Frame Info\r
  EArmObjGicRedistributorInfo,        ///<  7 - GIC Redistributor Info\r
  EArmObjGicItsInfo,                  ///<  8 - GIC ITS Info\r
  EArmObjSerialConsolePortInfo,       ///<  9 - Serial Console Port Info\r
  EArmObjSerialDebugPortInfo,         ///< 10 - Serial Debug Port Info\r
  EArmObjGenericTimerInfo,            ///< 11 - Generic Timer Info\r
  EArmObjPlatformGTBlockInfo,         ///< 12 - Platform GT Block Info\r
  EArmObjGTBlockTimerFrameInfo,       ///< 13 - Generic Timer Block Frame Info\r
  EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r
  EArmObjPciConfigSpaceInfo,          ///< 15 - PCI Configuration Space Info\r
  EArmObjHypervisorVendorIdentity,    ///< 16 - Hypervisor Vendor Id\r
  EArmObjFixedFeatureFlags,           ///< 17 - Fixed feature flags for FADT\r
  EArmObjItsGroup,                    ///< 18 - ITS Group\r
  EArmObjNamedComponent,              ///< 19 - Named Component\r
  EArmObjRootComplex,                 ///< 20 - Root Complex\r
  EArmObjSmmuV1SmmuV2,                ///< 21 - SMMUv1 or SMMUv2\r
  EArmObjSmmuV3,                      ///< 22 - SMMUv3\r
  EArmObjPmcg,                        ///< 23 - PMCG\r
  EArmObjGicItsIdentifierArray,       ///< 24 - GIC ITS Identifier Array\r
  EArmObjIdMappingArray,              ///< 25 - ID Mapping Array\r
  EArmObjSmmuInterruptArray,          ///< 26 - SMMU Interrupt Array\r
  EArmObjMax\r
} EARM_OBJECT_ID;\r
\r
/** A structure that describes the\r
    ARM Boot Architecture flags.\r
\r
    ID: EArmObjBootArchInfo\r
*/\r
typedef struct CmArmBootArchInfo {\r
  /** This is the ARM_BOOT_ARCH flags field of the FADT Table\r
      described in the ACPI Table Specification.\r
  */\r
  UINT32  BootArchFlags;\r
} CM_ARM_BOOT_ARCH_INFO;\r
\r
typedef struct CmArmCpuInfo {\r
  // Reserved for use when SMBIOS tables are implemented\r
} CM_ARM_CPU_INFO;\r
\r
/** A structure that describes the\r
    Power Management Profile Information for the Platform.\r
\r
    ID: EArmObjPowerManagementProfileInfo\r
*/\r
typedef struct CmArmPowerManagementProfileInfo {\r
  /** This is the Preferred_PM_Profile field of the FADT Table\r
      described in the ACPI Specification\r
  */\r
  UINT8  PowerManagementProfile;\r
} CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;\r
\r
/** A structure that describes the\r
    GIC CPU Interface for the Platform.\r
\r
    ID: EArmObjGicCInfo\r
*/\r
typedef struct CmArmGicCInfo {\r
  /// The GIC CPU Interface number.\r
  UINT32  CPUInterfaceNumber;\r
\r
  /** The ACPI Processor UID. This must match the\r
      _UID of the CPU Device object information described\r
      in the DSDT/SSDT for the CPU.\r
  */\r
  UINT32  AcpiProcessorUid;\r
\r
  /** The flags field as described by the GICC structure\r
      in the ACPI Specification.\r
  */\r
  UINT32  Flags;\r
\r
  /** The parking protocol version field as described by\r
    the GICC structure in the ACPI Specification.\r
  */\r
  UINT32  ParkingProtocolVersion;\r
\r
  /** The Performance Interrupt field as described by\r
      the GICC structure in the ACPI Specification.\r
  */\r
  UINT32  PerformanceInterruptGsiv;\r
\r
  /** The CPU Parked address field as described by\r
      the GICC structure in the ACPI Specification.\r
  */\r
  UINT64  ParkedAddress;\r
\r
  /** The base address for the GIC CPU Interface\r
      as described by the GICC structure in the\r
      ACPI Specification.\r
  */\r
  UINT64  PhysicalBaseAddress;\r
\r
  /** The base address for GICV interface\r
      as described by the GICC structure in the\r
      ACPI Specification.\r
  */\r
  UINT64  GICV;\r
\r
  /** The base address for GICH interface\r
      as described by the GICC structure in the\r
      ACPI Specification.\r
  */\r
  UINT64  GICH;\r
\r
  /** The GICV maintenance interrupt\r
      as described by the GICC structure in the\r
      ACPI Specification.\r
  */\r
  UINT32  VGICMaintenanceInterrupt;\r
\r
  /** The base address for GICR interface\r
      as described by the GICC structure in the\r
      ACPI Specification.\r
  */\r
  UINT64  GICRBaseAddress;\r
\r
  /** The MPIDR for the CPU\r
      as described by the GICC structure in the\r
      ACPI Specification.\r
  */\r
  UINT64  MPIDR;\r
\r
  /** The Processor Power Efficiency class\r
      as described by the GICC structure in the\r
      ACPI Specification.\r
  */\r
  UINT8   ProcessorPowerEfficiencyClass;\r
} CM_ARM_GICC_INFO;\r
\r
/** A structure that describes the\r
    GIC Distributor information for the Platform.\r
\r
    ID: EArmObjGicDInfo\r
*/\r
typedef struct CmArmGicDInfo {\r
  /// The Physical Base address for the GIC Distributor.\r
  UINT64  PhysicalBaseAddress;\r
\r
  /** The global system interrupt\r
      number where this GIC Distributor's\r
      interrupt inputs start.\r
  */\r
  UINT32  SystemVectorBase;\r
\r
  /** The GIC version as described\r
      by the GICD structure in the\r
      ACPI Specification.\r
  */\r
  UINT8   GicVersion;\r
} CM_ARM_GICD_INFO;\r
\r
/** A structure that describes the\r
    GIC MSI Frame information for the Platform.\r
\r
    ID: EArmObjGicMsiFrameInfo\r
*/\r
typedef struct CmArmGicMsiFrameInfo {\r
  /// The GIC MSI Frame ID\r
  UINT32  GicMsiFrameId;\r
\r
  /// The Physical base address for the MSI Frame\r
  UINT64  PhysicalBaseAddress;\r
\r
  /** The GIC MSI Frame flags\r
      as described by the GIC MSI frame\r
      structure in the ACPI Specification.\r
  */\r
  UINT32  Flags;\r
\r
  /// SPI Count used by this frame\r
  UINT16  SPICount;\r
\r
  /// SPI Base used by this frame\r
  UINT16  SPIBase;\r
} CM_ARM_GIC_MSI_FRAME_INFO;\r
\r
/** A structure that describes the\r
    GIC Redistributor information for the Platform.\r
\r
    ID: EArmObjGicRedistributorInfo\r
*/\r
typedef struct CmArmGicRedistInfo {\r
  /** The physical address of a page range\r
      containing all GIC Redistributors.\r
  */\r
  UINT64  DiscoveryRangeBaseAddress;\r
\r
  /// Length of the GIC Redistributor Discovery page range\r
  UINT32  DiscoveryRangeLength;\r
} CM_ARM_GIC_REDIST_INFO;\r
\r
/** A structure that describes the\r
    GIC Interrupt Translation Service information for the Platform.\r
\r
    ID: EArmObjGicItsInfo\r
*/\r
typedef struct CmArmGicItsInfo {\r
  /// The GIC ITS ID\r
  UINT32  GicItsId;\r
\r
  /// The physical address for the Interrupt Translation Service\r
  UINT64  PhysicalBaseAddress;\r
} CM_ARM_GIC_ITS_INFO;\r
\r
/** A structure that describes the\r
    Serial Port information for the Platform.\r
\r
    ID: EArmObjSerialConsolePortInfo or\r
        EArmObjSerialDebugPortInfo\r
*/\r
typedef struct CmArmSerialPortInfo {\r
  /// The physical base address for the serial port\r
  UINT64  BaseAddress;\r
\r
  /// The serial port interrupt\r
  UINT32  Interrupt;\r
\r
  /// The serial port baud rate\r
  UINT64  BaudRate;\r
\r
  /// The serial port clock\r
  UINT32  Clock;\r
\r
  /// Serial Port subtype\r
  UINT16  PortSubtype;\r
} CM_ARM_SERIAL_PORT_INFO;\r
\r
/** A structure that describes the\r
    Generic Timer information for the Platform.\r
\r
    ID: EArmObjGenericTimerInfo\r
*/\r
typedef struct CmArmGenericTimerInfo {\r
  /// The physical base address for the counter control frame\r
  UINT64  CounterControlBaseAddress;\r
\r
  /// The physical base address for the counter read frame\r
  UINT64  CounterReadBaseAddress;\r
\r
  /// The secure PL1 timer interrupt\r
  UINT32  SecurePL1TimerGSIV;\r
\r
  /// The secure PL1 timer flags\r
  UINT32  SecurePL1TimerFlags;\r
\r
  /// The non-secure PL1 timer interrupt\r
  UINT32  NonSecurePL1TimerGSIV;\r
\r
  /// The non-secure PL1 timer flags\r
  UINT32  NonSecurePL1TimerFlags;\r
\r
  /// The virtual timer interrupt\r
  UINT32  VirtualTimerGSIV;\r
\r
  /// The virtual timer flags\r
  UINT32  VirtualTimerFlags;\r
\r
  /// The non-secure PL2 timer interrupt\r
  UINT32  NonSecurePL2TimerGSIV;\r
\r
  /// The non-secure PL2 timer flags\r
  UINT32  NonSecurePL2TimerFlags;\r
} CM_ARM_GENERIC_TIMER_INFO;\r
\r
/** A structure that describes the\r
    Platform Generic Block Timer Frame information for the Platform.\r
\r
    ID: EArmObjGTBlockTimerFrameInfo\r
*/\r
typedef struct CmArmGTBlockTimerFrameInfo {\r
  /// The Generic Timer frame number\r
  UINT8   FrameNumber;\r
\r
  /// The physical base address for the CntBase block\r
  UINT64  PhysicalAddressCntBase;\r
\r
  /// The physical base address for the CntEL0Base block\r
  UINT64  PhysicalAddressCntEL0Base;\r
\r
  /// The physical timer interrupt\r
  UINT32  PhysicalTimerGSIV;\r
\r
  /** The physical timer flags as described by the GT Block\r
      Timer frame Structure in the ACPI Specification.\r
  */\r
  UINT32  PhysicalTimerFlags;\r
\r
  /// The virtual timer interrupt\r
  UINT32  VirtualTimerGSIV;\r
\r
  /** The virtual timer flags as described by the GT Block\r
      Timer frame Structure in the ACPI Specification.\r
  */\r
  UINT32  VirtualTimerFlags;\r
\r
  /** The common timer flags as described by the GT Block\r
      Timer frame Structure in the ACPI Specification.\r
  */\r
  UINT32  CommonFlags;\r
} CM_ARM_GTBLOCK_TIMER_FRAME_INFO;\r
\r
/** A structure that describes the\r
    Platform Generic Block Timer information for the Platform.\r
\r
    ID: EArmObjPlatformGTBlockInfo\r
*/\r
typedef struct CmArmGTBlockInfo {\r
  /// The physical base address for the GT Block Timer structure\r
  UINT64            GTBlockPhysicalAddress;\r
\r
  /// The number of timer frames implemented in the GT Block\r
  UINT32            GTBlockTimerFrameCount;\r
\r
  /// Reference token for the GT Block timer frame list\r
  CM_OBJECT_TOKEN   GTBlockTimerFrameToken;\r
} CM_ARM_GTBLOCK_INFO;\r
\r
/** A structure that describes the\r
    SBSA Generic Watchdog information for the Platform.\r
\r
    ID: EArmObjPlatformGenericWatchdogInfo\r
*/\r
typedef struct CmArmGenericWatchdogInfo {\r
  /// The physical base address of the SBSA Watchdog control frame\r
  UINT64  ControlFrameAddress;\r
\r
  /// The physical base address of the SBSA Watchdog refresh frame\r
  UINT64  RefreshFrameAddress;\r
\r
  /// The watchdog interrupt\r
  UINT32  TimerGSIV;\r
\r
  /** The flags for the watchdog as described by the SBSA watchdog\r
      structure in the ACPI specification.\r
  */\r
  UINT32  Flags;\r
} CM_ARM_GENERIC_WATCHDOG_INFO;\r
\r
/** A structure that describes the\r
    PCI Configuration Space information for the Platform.\r
\r
    ID: EArmObjPciConfigSpaceInfo\r
*/\r
typedef struct CmArmPciConfigSpaceInfo {\r
  /// The physical base address for the PCI segment\r
  UINT64  BaseAddress;\r
\r
  /// The PCI segment group number\r
  UINT16  PciSegmentGroupNumber;\r
\r
  /// The start bus number\r
  UINT8   StartBusNumber;\r
\r
  /// The end bus number\r
  UINT8   EndBusNumber;\r
} CM_ARM_PCI_CONFIG_SPACE_INFO;\r
\r
/** A structure that describes the\r
    Hypervisor Vendor ID information for the Platform.\r
\r
    ID: EArmObjHypervisorVendorIdentity\r
*/\r
typedef struct CmArmHypervisorVendorId {\r
  /// The hypervisor Vendor ID\r
  UINT64  HypervisorVendorId;\r
} CM_ARM_HYPERVISOR_VENDOR_ID;\r
\r
/** A structure that describes the\r
    Fixed feature flags for the Platform.\r
\r
    ID: EArmObjFixedFeatureFlags\r
*/\r
typedef struct CmArmFixedFeatureFlags {\r
  /// The Fixed feature flags\r
  UINT32  Flags;\r
} CM_ARM_FIXED_FEATURE_FLAGS;\r
\r
/** A structure that describes the\r
    ITS Group node for the Platform.\r
\r
    ID: EArmObjItsGroup\r
*/\r
typedef struct CmArmItsGroupNode {\r
  /// An unique token used to identify this object\r
  CM_OBJECT_TOKEN   Token;\r
  /// The number of ITS identifiers in the ITS node\r
  UINT32            ItsIdCount;\r
  /// Reference token for the ITS identifier array\r
  CM_OBJECT_TOKEN   ItsIdToken;\r
} CM_ARM_ITS_GROUP_NODE;\r
\r
/** A structure that describes the\r
    GIC ITS Identifiers for an ITS Group node.\r
\r
    ID: EArmObjGicItsIdentifierArray\r
*/\r
typedef struct CmArmGicItsIdentifier {\r
  /// The ITS Identifier\r
  UINT32  ItsId;\r
} CM_ARM_ITS_IDENTIFIER;\r
\r
/** A structure that describes the\r
    Named component node for the Platform.\r
\r
    ID: EArmObjNamedComponent\r
*/\r
typedef struct CmArmNamedComponentNode {\r
  /// An unique token used to identify this object\r
  CM_OBJECT_TOKEN   Token;\r
  /// Number of ID mappings\r
  UINT32            IdMappingCount;\r
  /// Reference token for the ID mapping array\r
  CM_OBJECT_TOKEN   IdMappingToken;\r
\r
  /// Flags for the named component\r
  UINT32            Flags;\r
\r
  /// Memory access properties : Cache coherent attributes\r
  UINT32            CacheCoherent;\r
  /// Memory access properties : Allocation hints\r
  UINT8             AllocationHints;\r
  /// Memory access properties : Memory access flags\r
  UINT8             MemoryAccessFlags;\r
\r
  /// Memory access properties : Address size limit\r
  UINT8             AddressSizeLimit;\r
  /** ASCII Null terminated string with the full path to\r
      the entry in the namespace for this object.\r
  */\r
  CHAR8*            ObjectName;\r
} CM_ARM_NAMED_COMPONENT_NODE;\r
\r
/** A structure that describes the\r
    Root complex node for the Platform.\r
\r
    ID: EArmObjRootComplex\r
*/\r
typedef struct CmArmRootComplexNode {\r
  /// An unique token used to identify this object\r
  CM_OBJECT_TOKEN   Token;\r
  /// Number of ID mappings\r
  UINT32            IdMappingCount;\r
  /// Reference token for the ID mapping array\r
  CM_OBJECT_TOKEN   IdMappingToken;\r
\r
  /// Memory access properties : Cache coherent attributes\r
  UINT32            CacheCoherent;\r
  /// Memory access properties : Allocation hints\r
  UINT8             AllocationHints;\r
  /// Memory access properties : Memory access flags\r
  UINT8             MemoryAccessFlags;\r
\r
  /// ATS attributes\r
  UINT32            AtsAttribute;\r
  /// PCI segment number\r
  UINT32            PciSegmentNumber;\r
  /// Memory address size limit\r
  UINT8             MemoryAddressSize;\r
} CM_ARM_ROOT_COMPLEX_NODE;\r
\r
/** A structure that describes the\r
    SMMUv1 or SMMUv2 node for the Platform.\r
\r
    ID: EArmObjSmmuV1SmmuV2\r
*/\r
typedef struct CmArmSmmuV1SmmuV2Node {\r
  /// An unique token used to identify this object\r
  CM_OBJECT_TOKEN   Token;\r
  /// Number of ID mappings\r
  UINT32            IdMappingCount;\r
  /// Reference token for the ID mapping array\r
  CM_OBJECT_TOKEN   IdMappingToken;\r
\r
  /// SMMU Base Address\r
  UINT64            BaseAddress;\r
  /// Length of the memory range covered by the SMMU\r
  UINT64            Span;\r
  /// SMMU Model\r
  UINT32            Model;\r
  /// SMMU flags\r
  UINT32            Flags;\r
\r
  /// Number of context interrupts\r
  UINT32            ContextInterruptCount;\r
  /// Reference token for the context interrupt array\r
  CM_OBJECT_TOKEN   ContextInterruptToken;\r
\r
  /// Number of PMU interrupts\r
  UINT32            PmuInterruptCount;\r
  /// Reference token for the PMU interrupt array\r
  CM_OBJECT_TOKEN   PmuInterruptToken;\r
\r
  /// GSIV of the SMMU_NSgIrpt interrupt\r
  UINT32            SMMU_NSgIrpt;\r
  /// SMMU_NSgIrpt interrupt flags\r
  UINT32            SMMU_NSgIrptFlags;\r
  /// GSIV of the SMMU_NSgCfgIrpt interrupt\r
  UINT32            SMMU_NSgCfgIrpt;\r
  /// SMMU_NSgCfgIrpt interrupt flags\r
  UINT32            SMMU_NSgCfgIrptFlags;\r
} CM_ARM_SMMUV1_SMMUV2_NODE;\r
\r
/** A structure that describes the\r
    SMMUv3 node for the Platform.\r
\r
    ID: EArmObjSmmuV3\r
*/\r
typedef struct CmArmSmmuV3Node {\r
  /// An unique token used to identify this object\r
  CM_OBJECT_TOKEN   Token;\r
  /// Number of ID mappings\r
  UINT32            IdMappingCount;\r
  /// Reference token for the ID mapping array\r
  CM_OBJECT_TOKEN   IdMappingToken;\r
\r
  /// SMMU Base Address\r
  UINT64    BaseAddress;\r
  /// SMMU flags\r
  UINT32            Flags;\r
  /// VATOS address\r
  UINT64            VatosAddress;\r
  /// Model\r
  UINT32            Model;\r
  /// GSIV of the Event interrupt if SPI based\r
  UINT32            EventInterrupt;\r
  /// PRI Interrupt if SPI based\r
  UINT32            PriInterrupt;\r
  /// GERR interrupt if GSIV based\r
  UINT32            GerrInterrupt;\r
  /// Sync interrupt if GSIV based\r
  UINT32            SyncInterrupt;\r
\r
  /// Proximity domain flag\r
  UINT32            ProximityDomain;\r
  /// Index into the array of ID mapping\r
  UINT32            DeviceIdMappingIndex;\r
} CM_ARM_SMMUV3_NODE;\r
\r
/** A structure that describes the\r
    PMCG node for the Platform.\r
\r
    ID: EArmObjPmcg\r
*/\r
typedef struct CmArmPmcgNode {\r
  /// An unique token used to identify this object\r
  CM_OBJECT_TOKEN   Token;\r
  /// Number of ID mappings\r
  UINT32            IdMappingCount;\r
  /// Reference token for the ID mapping array\r
  CM_OBJECT_TOKEN   IdMappingToken;\r
\r
  /// Base Address for performance monitor counter group\r
  UINT64            BaseAddress;\r
  /// GSIV for the Overflow interrupt\r
  UINT32            OverflowInterrupt;\r
  /// Page 1 Base address\r
  UINT64            Page1BaseAddress;\r
\r
  /// Reference token for the IORT node associated with this node\r
  CM_OBJECT_TOKEN   ReferenceToken;\r
} CM_ARM_PMCG_NODE;\r
\r
/** A structure that describes the\r
    ID Mappings for the Platform.\r
\r
    ID: EArmObjIdMappingArray\r
*/\r
typedef struct CmArmIdMapping {\r
  /// Input base\r
  UINT32           InputBase;\r
  /// Number of input IDs\r
  UINT32           NumIds;\r
  /// Output Base\r
  UINT32           OutputBase;\r
  /// Reference token for the output node\r
  CM_OBJECT_TOKEN  OutputReferenceToken;\r
  /// Flags\r
  UINT32    Flags;\r
} CM_ARM_ID_MAPPING;\r
\r
/** A structure that describes the\r
    SMMU interrupts for the Platform.\r
\r
    ID: EArmObjSmmuInterruptArray\r
*/\r
typedef struct CmArmSmmuInterrupt {\r
  /// Interrupt number\r
  UINT32    Interrupt;\r
\r
  /// Flags\r
  UINT32    Flags;\r
} CM_ARM_SMMU_INTERRUPT;\r
\r
#pragma pack()\r
\r
#endif // ARM_NAMESPACE_OBJECTS_H_\r