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26147c77 SM |
1 | /** @file\r |
2 | \r | |
de200b7e | 3 | Copyright (c) 2017 - 2022, Arm Limited. All rights reserved.<BR>\r |
26147c77 | 4 | \r |
9cd9bdc6 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
26147c77 SM |
6 | \r |
7 | @par Glossary:\r | |
8 | - Cm or CM - Configuration Manager\r | |
9 | - Obj or OBJ - Object\r | |
10 | - Std or STD - Standard\r | |
11 | **/\r | |
12 | \r | |
13 | #ifndef ARM_NAMESPACE_OBJECTS_H_\r | |
14 | #define ARM_NAMESPACE_OBJECTS_H_\r | |
15 | \r | |
16 | #include <StandardNameSpaceObjects.h>\r | |
17 | \r | |
18 | #pragma pack(1)\r | |
19 | \r | |
20 | /** The EARM_OBJECT_ID enum describes the Object IDs\r | |
21 | in the ARM Namespace\r | |
22 | */\r | |
23 | typedef enum ArmObjectID {\r | |
f413d9be SM |
24 | EArmObjReserved, ///< 0 - Reserved\r |
25 | EArmObjBootArchInfo, ///< 1 - Boot Architecture Info\r | |
26 | EArmObjCpuInfo, ///< 2 - CPU Info\r | |
27 | EArmObjPowerManagementProfileInfo, ///< 3 - Power Management Profile Info\r | |
28 | EArmObjGicCInfo, ///< 4 - GIC CPU Interface Info\r | |
29 | EArmObjGicDInfo, ///< 5 - GIC Distributor Info\r | |
30 | EArmObjGicMsiFrameInfo, ///< 6 - GIC MSI Frame Info\r | |
31 | EArmObjGicRedistributorInfo, ///< 7 - GIC Redistributor Info\r | |
32 | EArmObjGicItsInfo, ///< 8 - GIC ITS Info\r | |
33 | EArmObjSerialConsolePortInfo, ///< 9 - Serial Console Port Info\r | |
34 | EArmObjSerialDebugPortInfo, ///< 10 - Serial Debug Port Info\r | |
35 | EArmObjGenericTimerInfo, ///< 11 - Generic Timer Info\r | |
36 | EArmObjPlatformGTBlockInfo, ///< 12 - Platform GT Block Info\r | |
37 | EArmObjGTBlockTimerFrameInfo, ///< 13 - Generic Timer Block Frame Info\r | |
38 | EArmObjPlatformGenericWatchdogInfo, ///< 14 - Platform Generic Watchdog\r | |
39 | EArmObjPciConfigSpaceInfo, ///< 15 - PCI Configuration Space Info\r | |
40 | EArmObjHypervisorVendorIdentity, ///< 16 - Hypervisor Vendor Id\r | |
41 | EArmObjFixedFeatureFlags, ///< 17 - Fixed feature flags for FADT\r | |
42 | EArmObjItsGroup, ///< 18 - ITS Group\r | |
43 | EArmObjNamedComponent, ///< 19 - Named Component\r | |
44 | EArmObjRootComplex, ///< 20 - Root Complex\r | |
45 | EArmObjSmmuV1SmmuV2, ///< 21 - SMMUv1 or SMMUv2\r | |
46 | EArmObjSmmuV3, ///< 22 - SMMUv3\r | |
47 | EArmObjPmcg, ///< 23 - PMCG\r | |
48 | EArmObjGicItsIdentifierArray, ///< 24 - GIC ITS Identifier Array\r | |
49 | EArmObjIdMappingArray, ///< 25 - ID Mapping Array\r | |
50 | EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array\r | |
51 | EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info\r | |
52 | EArmObjCacheInfo, ///< 28 - Cache Info\r | |
b2bbe3df | 53 | EArmObjReserved29, ///< 29 - Reserved\r |
f413d9be SM |
54 | EArmObjCmRef, ///< 30 - CM Object Reference\r |
55 | EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info\r | |
56 | EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi\r | |
57 | EArmObjDeviceHandlePci, ///< 33 - Device Handle Pci\r | |
58 | EArmObjGenericInitiatorAffinityInfo, ///< 34 - Generic Initiator Affinity\r | |
bade7f42 | 59 | EArmObjSerialPortInfo, ///< 35 - Generic Serial Port Info\r |
37568365 | 60 | EArmObjCmn600Info, ///< 36 - CMN-600 Info\r |
f17ef10e | 61 | EArmObjLpiInfo, ///< 37 - Lpi Info\r |
ce306e48 PG |
62 | EArmObjPciAddressMapInfo, ///< 38 - Pci Address Map Info\r |
63 | EArmObjPciInterruptMapInfo, ///< 39 - Pci Interrupt Map Info\r | |
de200b7e SM |
64 | EArmObjRmr, ///< 40 - Reserved Memory Range Node\r |
65 | EArmObjMemoryRangeDescriptor, ///< 41 - Memory Range Descriptor\r | |
26147c77 SM |
66 | EArmObjMax\r |
67 | } EARM_OBJECT_ID;\r | |
68 | \r | |
69 | /** A structure that describes the\r | |
70 | ARM Boot Architecture flags.\r | |
c606f472 SM |
71 | \r |
72 | ID: EArmObjBootArchInfo\r | |
26147c77 SM |
73 | */\r |
74 | typedef struct CmArmBootArchInfo {\r | |
75 | /** This is the ARM_BOOT_ARCH flags field of the FADT Table\r | |
76 | described in the ACPI Table Specification.\r | |
77 | */\r | |
731c67e1 | 78 | UINT16 BootArchFlags;\r |
26147c77 SM |
79 | } CM_ARM_BOOT_ARCH_INFO;\r |
80 | \r | |
26147c77 SM |
81 | /** A structure that describes the\r |
82 | Power Management Profile Information for the Platform.\r | |
c606f472 SM |
83 | \r |
84 | ID: EArmObjPowerManagementProfileInfo\r | |
26147c77 SM |
85 | */\r |
86 | typedef struct CmArmPowerManagementProfileInfo {\r | |
87 | /** This is the Preferred_PM_Profile field of the FADT Table\r | |
88 | described in the ACPI Specification\r | |
89 | */\r | |
731c67e1 | 90 | UINT8 PowerManagementProfile;\r |
26147c77 SM |
91 | } CM_ARM_POWER_MANAGEMENT_PROFILE_INFO;\r |
92 | \r | |
93 | /** A structure that describes the\r | |
94 | GIC CPU Interface for the Platform.\r | |
c606f472 SM |
95 | \r |
96 | ID: EArmObjGicCInfo\r | |
26147c77 SM |
97 | */\r |
98 | typedef struct CmArmGicCInfo {\r | |
99 | /// The GIC CPU Interface number.\r | |
731c67e1 | 100 | UINT32 CPUInterfaceNumber;\r |
26147c77 SM |
101 | \r |
102 | /** The ACPI Processor UID. This must match the\r | |
103 | _UID of the CPU Device object information described\r | |
104 | in the DSDT/SSDT for the CPU.\r | |
105 | */\r | |
731c67e1 | 106 | UINT32 AcpiProcessorUid;\r |
26147c77 SM |
107 | \r |
108 | /** The flags field as described by the GICC structure\r | |
109 | in the ACPI Specification.\r | |
110 | */\r | |
731c67e1 | 111 | UINT32 Flags;\r |
26147c77 SM |
112 | \r |
113 | /** The parking protocol version field as described by\r | |
114 | the GICC structure in the ACPI Specification.\r | |
115 | */\r | |
731c67e1 | 116 | UINT32 ParkingProtocolVersion;\r |
26147c77 SM |
117 | \r |
118 | /** The Performance Interrupt field as described by\r | |
119 | the GICC structure in the ACPI Specification.\r | |
120 | */\r | |
731c67e1 | 121 | UINT32 PerformanceInterruptGsiv;\r |
26147c77 SM |
122 | \r |
123 | /** The CPU Parked address field as described by\r | |
124 | the GICC structure in the ACPI Specification.\r | |
125 | */\r | |
731c67e1 | 126 | UINT64 ParkedAddress;\r |
26147c77 SM |
127 | \r |
128 | /** The base address for the GIC CPU Interface\r | |
129 | as described by the GICC structure in the\r | |
130 | ACPI Specification.\r | |
131 | */\r | |
731c67e1 | 132 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
133 | \r |
134 | /** The base address for GICV interface\r | |
135 | as described by the GICC structure in the\r | |
136 | ACPI Specification.\r | |
137 | */\r | |
731c67e1 | 138 | UINT64 GICV;\r |
26147c77 SM |
139 | \r |
140 | /** The base address for GICH interface\r | |
141 | as described by the GICC structure in the\r | |
142 | ACPI Specification.\r | |
143 | */\r | |
731c67e1 | 144 | UINT64 GICH;\r |
26147c77 SM |
145 | \r |
146 | /** The GICV maintenance interrupt\r | |
147 | as described by the GICC structure in the\r | |
148 | ACPI Specification.\r | |
149 | */\r | |
731c67e1 | 150 | UINT32 VGICMaintenanceInterrupt;\r |
26147c77 SM |
151 | \r |
152 | /** The base address for GICR interface\r | |
153 | as described by the GICC structure in the\r | |
154 | ACPI Specification.\r | |
155 | */\r | |
731c67e1 | 156 | UINT64 GICRBaseAddress;\r |
26147c77 SM |
157 | \r |
158 | /** The MPIDR for the CPU\r | |
159 | as described by the GICC structure in the\r | |
160 | ACPI Specification.\r | |
161 | */\r | |
731c67e1 | 162 | UINT64 MPIDR;\r |
26147c77 SM |
163 | \r |
164 | /** The Processor Power Efficiency class\r | |
165 | as described by the GICC structure in the\r | |
166 | ACPI Specification.\r | |
167 | */\r | |
731c67e1 | 168 | UINT8 ProcessorPowerEfficiencyClass;\r |
5506701f KK |
169 | \r |
170 | /** Statistical Profiling Extension buffer overflow GSIV. Zero if\r | |
171 | unsupported by this processor. This field was introduced in\r | |
172 | ACPI 6.3 (MADT revision 5) and is therefore ignored when\r | |
173 | generating MADT revision 4 or lower.\r | |
174 | */\r | |
731c67e1 | 175 | UINT16 SpeOverflowInterrupt;\r |
f413d9be SM |
176 | \r |
177 | /** The proximity domain to which the logical processor belongs.\r | |
178 | This field is used to populate the GICC affinity structure\r | |
179 | in the SRAT table.\r | |
180 | */\r | |
731c67e1 | 181 | UINT32 ProximityDomain;\r |
f413d9be SM |
182 | \r |
183 | /** The clock domain to which the logical processor belongs.\r | |
184 | This field is used to populate the GICC affinity structure\r | |
185 | in the SRAT table.\r | |
186 | */\r | |
731c67e1 | 187 | UINT32 ClockDomain;\r |
f413d9be SM |
188 | \r |
189 | /** The GICC Affinity flags field as described by the GICC Affinity structure\r | |
190 | in the SRAT table.\r | |
191 | */\r | |
731c67e1 | 192 | UINT32 AffinityFlags;\r |
26147c77 SM |
193 | } CM_ARM_GICC_INFO;\r |
194 | \r | |
195 | /** A structure that describes the\r | |
196 | GIC Distributor information for the Platform.\r | |
c606f472 SM |
197 | \r |
198 | ID: EArmObjGicDInfo\r | |
26147c77 SM |
199 | */\r |
200 | typedef struct CmArmGicDInfo {\r | |
26147c77 | 201 | /// The Physical Base address for the GIC Distributor.\r |
731c67e1 | 202 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
203 | \r |
204 | /** The global system interrupt\r | |
205 | number where this GIC Distributor's\r | |
206 | interrupt inputs start.\r | |
207 | */\r | |
731c67e1 | 208 | UINT32 SystemVectorBase;\r |
26147c77 SM |
209 | \r |
210 | /** The GIC version as described\r | |
211 | by the GICD structure in the\r | |
212 | ACPI Specification.\r | |
213 | */\r | |
731c67e1 | 214 | UINT8 GicVersion;\r |
26147c77 SM |
215 | } CM_ARM_GICD_INFO;\r |
216 | \r | |
217 | /** A structure that describes the\r | |
218 | GIC MSI Frame information for the Platform.\r | |
c606f472 SM |
219 | \r |
220 | ID: EArmObjGicMsiFrameInfo\r | |
26147c77 SM |
221 | */\r |
222 | typedef struct CmArmGicMsiFrameInfo {\r | |
223 | /// The GIC MSI Frame ID\r | |
731c67e1 | 224 | UINT32 GicMsiFrameId;\r |
26147c77 SM |
225 | \r |
226 | /// The Physical base address for the MSI Frame\r | |
731c67e1 | 227 | UINT64 PhysicalBaseAddress;\r |
26147c77 SM |
228 | \r |
229 | /** The GIC MSI Frame flags\r | |
230 | as described by the GIC MSI frame\r | |
231 | structure in the ACPI Specification.\r | |
232 | */\r | |
731c67e1 | 233 | UINT32 Flags;\r |
26147c77 SM |
234 | \r |
235 | /// SPI Count used by this frame\r | |
731c67e1 | 236 | UINT16 SPICount;\r |
26147c77 SM |
237 | \r |
238 | /// SPI Base used by this frame\r | |
731c67e1 | 239 | UINT16 SPIBase;\r |
26147c77 SM |
240 | } CM_ARM_GIC_MSI_FRAME_INFO;\r |
241 | \r | |
242 | /** A structure that describes the\r | |
243 | GIC Redistributor information for the Platform.\r | |
c606f472 SM |
244 | \r |
245 | ID: EArmObjGicRedistributorInfo\r | |
26147c77 SM |
246 | */\r |
247 | typedef struct CmArmGicRedistInfo {\r | |
248 | /** The physical address of a page range\r | |
249 | containing all GIC Redistributors.\r | |
250 | */\r | |
731c67e1 | 251 | UINT64 DiscoveryRangeBaseAddress;\r |
26147c77 SM |
252 | \r |
253 | /// Length of the GIC Redistributor Discovery page range\r | |
731c67e1 | 254 | UINT32 DiscoveryRangeLength;\r |
26147c77 SM |
255 | } CM_ARM_GIC_REDIST_INFO;\r |
256 | \r | |
257 | /** A structure that describes the\r | |
258 | GIC Interrupt Translation Service information for the Platform.\r | |
c606f472 SM |
259 | \r |
260 | ID: EArmObjGicItsInfo\r | |
26147c77 SM |
261 | */\r |
262 | typedef struct CmArmGicItsInfo {\r | |
263 | /// The GIC ITS ID\r | |
731c67e1 | 264 | UINT32 GicItsId;\r |
26147c77 SM |
265 | \r |
266 | /// The physical address for the Interrupt Translation Service\r | |
731c67e1 | 267 | UINT64 PhysicalBaseAddress;\r |
f413d9be SM |
268 | \r |
269 | /** The proximity domain to which the logical processor belongs.\r | |
270 | This field is used to populate the GIC ITS affinity structure\r | |
271 | in the SRAT table.\r | |
272 | */\r | |
731c67e1 | 273 | UINT32 ProximityDomain;\r |
26147c77 SM |
274 | } CM_ARM_GIC_ITS_INFO;\r |
275 | \r | |
276 | /** A structure that describes the\r | |
277 | Serial Port information for the Platform.\r | |
c606f472 SM |
278 | \r |
279 | ID: EArmObjSerialConsolePortInfo or\r | |
bade7f42 PG |
280 | EArmObjSerialDebugPortInfo or\r |
281 | EArmObjSerialPortInfo\r | |
26147c77 SM |
282 | */\r |
283 | typedef struct CmArmSerialPortInfo {\r | |
284 | /// The physical base address for the serial port\r | |
731c67e1 | 285 | UINT64 BaseAddress;\r |
26147c77 SM |
286 | \r |
287 | /// The serial port interrupt\r | |
731c67e1 | 288 | UINT32 Interrupt;\r |
26147c77 SM |
289 | \r |
290 | /// The serial port baud rate\r | |
731c67e1 | 291 | UINT64 BaudRate;\r |
26147c77 SM |
292 | \r |
293 | /// The serial port clock\r | |
731c67e1 | 294 | UINT32 Clock;\r |
26147c77 SM |
295 | \r |
296 | /// Serial Port subtype\r | |
731c67e1 | 297 | UINT16 PortSubtype;\r |
bade7f42 PG |
298 | \r |
299 | /// The Base address length\r | |
731c67e1 | 300 | UINT64 BaseAddressLength;\r |
c8cf71ec JG |
301 | \r |
302 | /// The access size\r | |
731c67e1 | 303 | UINT8 AccessSize;\r |
26147c77 SM |
304 | } CM_ARM_SERIAL_PORT_INFO;\r |
305 | \r | |
306 | /** A structure that describes the\r | |
307 | Generic Timer information for the Platform.\r | |
c606f472 SM |
308 | \r |
309 | ID: EArmObjGenericTimerInfo\r | |
26147c77 SM |
310 | */\r |
311 | typedef struct CmArmGenericTimerInfo {\r | |
312 | /// The physical base address for the counter control frame\r | |
731c67e1 | 313 | UINT64 CounterControlBaseAddress;\r |
26147c77 SM |
314 | \r |
315 | /// The physical base address for the counter read frame\r | |
731c67e1 | 316 | UINT64 CounterReadBaseAddress;\r |
26147c77 SM |
317 | \r |
318 | /// The secure PL1 timer interrupt\r | |
731c67e1 | 319 | UINT32 SecurePL1TimerGSIV;\r |
26147c77 SM |
320 | \r |
321 | /// The secure PL1 timer flags\r | |
731c67e1 | 322 | UINT32 SecurePL1TimerFlags;\r |
26147c77 SM |
323 | \r |
324 | /// The non-secure PL1 timer interrupt\r | |
731c67e1 | 325 | UINT32 NonSecurePL1TimerGSIV;\r |
26147c77 SM |
326 | \r |
327 | /// The non-secure PL1 timer flags\r | |
731c67e1 | 328 | UINT32 NonSecurePL1TimerFlags;\r |
26147c77 SM |
329 | \r |
330 | /// The virtual timer interrupt\r | |
731c67e1 | 331 | UINT32 VirtualTimerGSIV;\r |
26147c77 SM |
332 | \r |
333 | /// The virtual timer flags\r | |
731c67e1 | 334 | UINT32 VirtualTimerFlags;\r |
26147c77 SM |
335 | \r |
336 | /// The non-secure PL2 timer interrupt\r | |
731c67e1 | 337 | UINT32 NonSecurePL2TimerGSIV;\r |
26147c77 SM |
338 | \r |
339 | /// The non-secure PL2 timer flags\r | |
731c67e1 | 340 | UINT32 NonSecurePL2TimerFlags;\r |
e8015f2f PG |
341 | \r |
342 | /// GSIV for the virtual EL2 timer\r | |
731c67e1 | 343 | UINT32 VirtualPL2TimerGSIV;\r |
e8015f2f PG |
344 | \r |
345 | /// Flags for the virtual EL2 timer\r | |
731c67e1 | 346 | UINT32 VirtualPL2TimerFlags;\r |
26147c77 SM |
347 | } CM_ARM_GENERIC_TIMER_INFO;\r |
348 | \r | |
349 | /** A structure that describes the\r | |
350 | Platform Generic Block Timer Frame information for the Platform.\r | |
c606f472 SM |
351 | \r |
352 | ID: EArmObjGTBlockTimerFrameInfo\r | |
26147c77 SM |
353 | */\r |
354 | typedef struct CmArmGTBlockTimerFrameInfo {\r | |
355 | /// The Generic Timer frame number\r | |
731c67e1 | 356 | UINT8 FrameNumber;\r |
26147c77 SM |
357 | \r |
358 | /// The physical base address for the CntBase block\r | |
731c67e1 | 359 | UINT64 PhysicalAddressCntBase;\r |
26147c77 SM |
360 | \r |
361 | /// The physical base address for the CntEL0Base block\r | |
731c67e1 | 362 | UINT64 PhysicalAddressCntEL0Base;\r |
26147c77 SM |
363 | \r |
364 | /// The physical timer interrupt\r | |
731c67e1 | 365 | UINT32 PhysicalTimerGSIV;\r |
26147c77 SM |
366 | \r |
367 | /** The physical timer flags as described by the GT Block\r | |
368 | Timer frame Structure in the ACPI Specification.\r | |
369 | */\r | |
731c67e1 | 370 | UINT32 PhysicalTimerFlags;\r |
26147c77 SM |
371 | \r |
372 | /// The virtual timer interrupt\r | |
731c67e1 | 373 | UINT32 VirtualTimerGSIV;\r |
26147c77 SM |
374 | \r |
375 | /** The virtual timer flags as described by the GT Block\r | |
376 | Timer frame Structure in the ACPI Specification.\r | |
377 | */\r | |
731c67e1 | 378 | UINT32 VirtualTimerFlags;\r |
26147c77 SM |
379 | \r |
380 | /** The common timer flags as described by the GT Block\r | |
381 | Timer frame Structure in the ACPI Specification.\r | |
382 | */\r | |
731c67e1 | 383 | UINT32 CommonFlags;\r |
26147c77 SM |
384 | } CM_ARM_GTBLOCK_TIMER_FRAME_INFO;\r |
385 | \r | |
386 | /** A structure that describes the\r | |
387 | Platform Generic Block Timer information for the Platform.\r | |
c606f472 SM |
388 | \r |
389 | ID: EArmObjPlatformGTBlockInfo\r | |
26147c77 SM |
390 | */\r |
391 | typedef struct CmArmGTBlockInfo {\r | |
392 | /// The physical base address for the GT Block Timer structure\r | |
731c67e1 | 393 | UINT64 GTBlockPhysicalAddress;\r |
26147c77 SM |
394 | \r |
395 | /// The number of timer frames implemented in the GT Block\r | |
731c67e1 | 396 | UINT32 GTBlockTimerFrameCount;\r |
26147c77 SM |
397 | \r |
398 | /// Reference token for the GT Block timer frame list\r | |
731c67e1 | 399 | CM_OBJECT_TOKEN GTBlockTimerFrameToken;\r |
26147c77 SM |
400 | } CM_ARM_GTBLOCK_INFO;\r |
401 | \r | |
402 | /** A structure that describes the\r | |
f09dbf20 | 403 | Arm Generic Watchdog information for the Platform.\r |
c606f472 SM |
404 | \r |
405 | ID: EArmObjPlatformGenericWatchdogInfo\r | |
26147c77 SM |
406 | */\r |
407 | typedef struct CmArmGenericWatchdogInfo {\r | |
f09dbf20 | 408 | /// The physical base address of the Arm Watchdog control frame\r |
731c67e1 | 409 | UINT64 ControlFrameAddress;\r |
26147c77 | 410 | \r |
f09dbf20 | 411 | /// The physical base address of the Arm Watchdog refresh frame\r |
731c67e1 | 412 | UINT64 RefreshFrameAddress;\r |
26147c77 SM |
413 | \r |
414 | /// The watchdog interrupt\r | |
731c67e1 | 415 | UINT32 TimerGSIV;\r |
26147c77 | 416 | \r |
f09dbf20 | 417 | /** The flags for the watchdog as described by the Arm watchdog\r |
26147c77 SM |
418 | structure in the ACPI specification.\r |
419 | */\r | |
731c67e1 | 420 | UINT32 Flags;\r |
26147c77 SM |
421 | } CM_ARM_GENERIC_WATCHDOG_INFO;\r |
422 | \r | |
423 | /** A structure that describes the\r | |
424 | PCI Configuration Space information for the Platform.\r | |
c606f472 SM |
425 | \r |
426 | ID: EArmObjPciConfigSpaceInfo\r | |
26147c77 SM |
427 | */\r |
428 | typedef struct CmArmPciConfigSpaceInfo {\r | |
429 | /// The physical base address for the PCI segment\r | |
ce306e48 | 430 | UINT64 BaseAddress;\r |
26147c77 SM |
431 | \r |
432 | /// The PCI segment group number\r | |
ce306e48 | 433 | UINT16 PciSegmentGroupNumber;\r |
26147c77 SM |
434 | \r |
435 | /// The start bus number\r | |
ce306e48 | 436 | UINT8 StartBusNumber;\r |
26147c77 SM |
437 | \r |
438 | /// The end bus number\r | |
ce306e48 PG |
439 | UINT8 EndBusNumber;\r |
440 | \r | |
441 | /// Optional field: Reference Token for address mapping.\r | |
442 | /// Token identifying a CM_ARM_OBJ_REF structure.\r | |
443 | CM_OBJECT_TOKEN AddressMapToken;\r | |
444 | \r | |
445 | /// Optional field: Reference Token for interrupt mapping.\r | |
446 | /// Token identifying a CM_ARM_OBJ_REF structure.\r | |
447 | CM_OBJECT_TOKEN InterruptMapToken;\r | |
26147c77 SM |
448 | } CM_ARM_PCI_CONFIG_SPACE_INFO;\r |
449 | \r | |
450 | /** A structure that describes the\r | |
451 | Hypervisor Vendor ID information for the Platform.\r | |
c606f472 SM |
452 | \r |
453 | ID: EArmObjHypervisorVendorIdentity\r | |
26147c77 SM |
454 | */\r |
455 | typedef struct CmArmHypervisorVendorId {\r | |
456 | /// The hypervisor Vendor ID\r | |
731c67e1 | 457 | UINT64 HypervisorVendorId;\r |
26147c77 SM |
458 | } CM_ARM_HYPERVISOR_VENDOR_ID;\r |
459 | \r | |
460 | /** A structure that describes the\r | |
461 | Fixed feature flags for the Platform.\r | |
c606f472 SM |
462 | \r |
463 | ID: EArmObjFixedFeatureFlags\r | |
26147c77 SM |
464 | */\r |
465 | typedef struct CmArmFixedFeatureFlags {\r | |
466 | /// The Fixed feature flags\r | |
731c67e1 | 467 | UINT32 Flags;\r |
26147c77 SM |
468 | } CM_ARM_FIXED_FEATURE_FLAGS;\r |
469 | \r | |
470 | /** A structure that describes the\r | |
471 | ITS Group node for the Platform.\r | |
c606f472 SM |
472 | \r |
473 | ID: EArmObjItsGroup\r | |
26147c77 SM |
474 | */\r |
475 | typedef struct CmArmItsGroupNode {\r | |
c606f472 | 476 | /// An unique token used to identify this object\r |
731c67e1 | 477 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 478 | /// The number of ITS identifiers in the ITS node\r |
731c67e1 | 479 | UINT32 ItsIdCount;\r |
26147c77 | 480 | /// Reference token for the ITS identifier array\r |
731c67e1 | 481 | CM_OBJECT_TOKEN ItsIdToken;\r |
de200b7e SM |
482 | \r |
483 | /// Unique identifier for this node.\r | |
484 | UINT32 Identifier;\r | |
26147c77 SM |
485 | } CM_ARM_ITS_GROUP_NODE;\r |
486 | \r | |
26147c77 SM |
487 | /** A structure that describes the\r |
488 | Named component node for the Platform.\r | |
c606f472 SM |
489 | \r |
490 | ID: EArmObjNamedComponent\r | |
26147c77 SM |
491 | */\r |
492 | typedef struct CmArmNamedComponentNode {\r | |
c606f472 | 493 | /// An unique token used to identify this object\r |
731c67e1 | 494 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 495 | /// Number of ID mappings\r |
731c67e1 | 496 | UINT32 IdMappingCount;\r |
26147c77 | 497 | /// Reference token for the ID mapping array\r |
731c67e1 | 498 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
499 | \r |
500 | /// Flags for the named component\r | |
731c67e1 | 501 | UINT32 Flags;\r |
26147c77 SM |
502 | \r |
503 | /// Memory access properties : Cache coherent attributes\r | |
731c67e1 | 504 | UINT32 CacheCoherent;\r |
26147c77 | 505 | /// Memory access properties : Allocation hints\r |
731c67e1 | 506 | UINT8 AllocationHints;\r |
26147c77 | 507 | /// Memory access properties : Memory access flags\r |
731c67e1 | 508 | UINT8 MemoryAccessFlags;\r |
26147c77 SM |
509 | \r |
510 | /// Memory access properties : Address size limit\r | |
731c67e1 MK |
511 | UINT8 AddressSizeLimit;\r |
512 | \r | |
26147c77 SM |
513 | /** ASCII Null terminated string with the full path to\r |
514 | the entry in the namespace for this object.\r | |
515 | */\r | |
731c67e1 | 516 | CHAR8 *ObjectName;\r |
de200b7e SM |
517 | \r |
518 | /// Unique identifier for this node.\r | |
519 | UINT32 Identifier;\r | |
26147c77 SM |
520 | } CM_ARM_NAMED_COMPONENT_NODE;\r |
521 | \r | |
522 | /** A structure that describes the\r | |
523 | Root complex node for the Platform.\r | |
c606f472 SM |
524 | \r |
525 | ID: EArmObjRootComplex\r | |
26147c77 SM |
526 | */\r |
527 | typedef struct CmArmRootComplexNode {\r | |
c606f472 | 528 | /// An unique token used to identify this object\r |
731c67e1 | 529 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 530 | /// Number of ID mappings\r |
731c67e1 | 531 | UINT32 IdMappingCount;\r |
26147c77 | 532 | /// Reference token for the ID mapping array\r |
731c67e1 | 533 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
534 | \r |
535 | /// Memory access properties : Cache coherent attributes\r | |
731c67e1 | 536 | UINT32 CacheCoherent;\r |
26147c77 | 537 | /// Memory access properties : Allocation hints\r |
731c67e1 | 538 | UINT8 AllocationHints;\r |
26147c77 | 539 | /// Memory access properties : Memory access flags\r |
731c67e1 | 540 | UINT8 MemoryAccessFlags;\r |
26147c77 SM |
541 | \r |
542 | /// ATS attributes\r | |
731c67e1 | 543 | UINT32 AtsAttribute;\r |
26147c77 | 544 | /// PCI segment number\r |
731c67e1 | 545 | UINT32 PciSegmentNumber;\r |
26147c77 | 546 | /// Memory address size limit\r |
731c67e1 | 547 | UINT8 MemoryAddressSize;\r |
de200b7e SM |
548 | /// PASID capabilities\r |
549 | UINT16 PasidCapabilities;\r | |
550 | /// Flags\r | |
551 | UINT32 Flags;\r | |
552 | \r | |
553 | /// Unique identifier for this node.\r | |
554 | UINT32 Identifier;\r | |
26147c77 SM |
555 | } CM_ARM_ROOT_COMPLEX_NODE;\r |
556 | \r | |
557 | /** A structure that describes the\r | |
558 | SMMUv1 or SMMUv2 node for the Platform.\r | |
c606f472 SM |
559 | \r |
560 | ID: EArmObjSmmuV1SmmuV2\r | |
26147c77 SM |
561 | */\r |
562 | typedef struct CmArmSmmuV1SmmuV2Node {\r | |
c606f472 | 563 | /// An unique token used to identify this object\r |
731c67e1 | 564 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 565 | /// Number of ID mappings\r |
731c67e1 | 566 | UINT32 IdMappingCount;\r |
26147c77 | 567 | /// Reference token for the ID mapping array\r |
731c67e1 | 568 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
569 | \r |
570 | /// SMMU Base Address\r | |
731c67e1 | 571 | UINT64 BaseAddress;\r |
26147c77 | 572 | /// Length of the memory range covered by the SMMU\r |
731c67e1 | 573 | UINT64 Span;\r |
26147c77 | 574 | /// SMMU Model\r |
731c67e1 | 575 | UINT32 Model;\r |
26147c77 | 576 | /// SMMU flags\r |
731c67e1 | 577 | UINT32 Flags;\r |
26147c77 SM |
578 | \r |
579 | /// Number of context interrupts\r | |
731c67e1 | 580 | UINT32 ContextInterruptCount;\r |
26147c77 | 581 | /// Reference token for the context interrupt array\r |
731c67e1 | 582 | CM_OBJECT_TOKEN ContextInterruptToken;\r |
26147c77 SM |
583 | \r |
584 | /// Number of PMU interrupts\r | |
731c67e1 | 585 | UINT32 PmuInterruptCount;\r |
26147c77 | 586 | /// Reference token for the PMU interrupt array\r |
731c67e1 | 587 | CM_OBJECT_TOKEN PmuInterruptToken;\r |
26147c77 SM |
588 | \r |
589 | /// GSIV of the SMMU_NSgIrpt interrupt\r | |
731c67e1 | 590 | UINT32 SMMU_NSgIrpt;\r |
26147c77 | 591 | /// SMMU_NSgIrpt interrupt flags\r |
731c67e1 | 592 | UINT32 SMMU_NSgIrptFlags;\r |
26147c77 | 593 | /// GSIV of the SMMU_NSgCfgIrpt interrupt\r |
731c67e1 | 594 | UINT32 SMMU_NSgCfgIrpt;\r |
26147c77 | 595 | /// SMMU_NSgCfgIrpt interrupt flags\r |
731c67e1 | 596 | UINT32 SMMU_NSgCfgIrptFlags;\r |
de200b7e SM |
597 | \r |
598 | /// Unique identifier for this node.\r | |
599 | UINT32 Identifier;\r | |
26147c77 SM |
600 | } CM_ARM_SMMUV1_SMMUV2_NODE;\r |
601 | \r | |
602 | /** A structure that describes the\r | |
603 | SMMUv3 node for the Platform.\r | |
c606f472 SM |
604 | \r |
605 | ID: EArmObjSmmuV3\r | |
26147c77 SM |
606 | */\r |
607 | typedef struct CmArmSmmuV3Node {\r | |
c606f472 | 608 | /// An unique token used to identify this object\r |
731c67e1 | 609 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 610 | /// Number of ID mappings\r |
731c67e1 | 611 | UINT32 IdMappingCount;\r |
26147c77 | 612 | /// Reference token for the ID mapping array\r |
731c67e1 | 613 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
614 | \r |
615 | /// SMMU Base Address\r | |
731c67e1 | 616 | UINT64 BaseAddress;\r |
26147c77 | 617 | /// SMMU flags\r |
731c67e1 | 618 | UINT32 Flags;\r |
26147c77 | 619 | /// VATOS address\r |
731c67e1 | 620 | UINT64 VatosAddress;\r |
26147c77 | 621 | /// Model\r |
731c67e1 | 622 | UINT32 Model;\r |
26147c77 | 623 | /// GSIV of the Event interrupt if SPI based\r |
731c67e1 | 624 | UINT32 EventInterrupt;\r |
26147c77 | 625 | /// PRI Interrupt if SPI based\r |
731c67e1 | 626 | UINT32 PriInterrupt;\r |
26147c77 | 627 | /// GERR interrupt if GSIV based\r |
731c67e1 | 628 | UINT32 GerrInterrupt;\r |
26147c77 | 629 | /// Sync interrupt if GSIV based\r |
731c67e1 | 630 | UINT32 SyncInterrupt;\r |
26147c77 SM |
631 | \r |
632 | /// Proximity domain flag\r | |
731c67e1 | 633 | UINT32 ProximityDomain;\r |
26147c77 | 634 | /// Index into the array of ID mapping\r |
731c67e1 | 635 | UINT32 DeviceIdMappingIndex;\r |
de200b7e SM |
636 | \r |
637 | /// Unique identifier for this node.\r | |
638 | UINT32 Identifier;\r | |
26147c77 SM |
639 | } CM_ARM_SMMUV3_NODE;\r |
640 | \r | |
641 | /** A structure that describes the\r | |
642 | PMCG node for the Platform.\r | |
c606f472 SM |
643 | \r |
644 | ID: EArmObjPmcg\r | |
26147c77 SM |
645 | */\r |
646 | typedef struct CmArmPmcgNode {\r | |
c606f472 | 647 | /// An unique token used to identify this object\r |
731c67e1 | 648 | CM_OBJECT_TOKEN Token;\r |
26147c77 | 649 | /// Number of ID mappings\r |
731c67e1 | 650 | UINT32 IdMappingCount;\r |
26147c77 | 651 | /// Reference token for the ID mapping array\r |
731c67e1 | 652 | CM_OBJECT_TOKEN IdMappingToken;\r |
26147c77 SM |
653 | \r |
654 | /// Base Address for performance monitor counter group\r | |
731c67e1 | 655 | UINT64 BaseAddress;\r |
26147c77 | 656 | /// GSIV for the Overflow interrupt\r |
731c67e1 | 657 | UINT32 OverflowInterrupt;\r |
26147c77 | 658 | /// Page 1 Base address\r |
731c67e1 | 659 | UINT64 Page1BaseAddress;\r |
26147c77 SM |
660 | \r |
661 | /// Reference token for the IORT node associated with this node\r | |
731c67e1 | 662 | CM_OBJECT_TOKEN ReferenceToken;\r |
de200b7e SM |
663 | \r |
664 | /// Unique identifier for this node.\r | |
665 | UINT32 Identifier;\r | |
26147c77 SM |
666 | } CM_ARM_PMCG_NODE;\r |
667 | \r | |
cc00dbcb PG |
668 | /** A structure that describes the\r |
669 | GIC ITS Identifiers for an ITS Group node.\r | |
670 | \r | |
671 | ID: EArmObjGicItsIdentifierArray\r | |
672 | */\r | |
673 | typedef struct CmArmGicItsIdentifier {\r | |
674 | /// The ITS Identifier\r | |
731c67e1 | 675 | UINT32 ItsId;\r |
cc00dbcb PG |
676 | } CM_ARM_ITS_IDENTIFIER;\r |
677 | \r | |
26147c77 SM |
678 | /** A structure that describes the\r |
679 | ID Mappings for the Platform.\r | |
c606f472 SM |
680 | \r |
681 | ID: EArmObjIdMappingArray\r | |
26147c77 SM |
682 | */\r |
683 | typedef struct CmArmIdMapping {\r | |
684 | /// Input base\r | |
731c67e1 | 685 | UINT32 InputBase;\r |
26147c77 | 686 | /// Number of input IDs\r |
731c67e1 | 687 | UINT32 NumIds;\r |
26147c77 | 688 | /// Output Base\r |
731c67e1 | 689 | UINT32 OutputBase;\r |
26147c77 | 690 | /// Reference token for the output node\r |
731c67e1 | 691 | CM_OBJECT_TOKEN OutputReferenceToken;\r |
26147c77 | 692 | /// Flags\r |
731c67e1 | 693 | UINT32 Flags;\r |
26147c77 SM |
694 | } CM_ARM_ID_MAPPING;\r |
695 | \r | |
37568365 PG |
696 | /** A structure that describes the Arm\r |
697 | Generic Interrupts.\r | |
26147c77 | 698 | */\r |
37568365 | 699 | typedef struct CmArmGenericInterrupt {\r |
26147c77 SM |
700 | /// Interrupt number\r |
701 | UINT32 Interrupt;\r | |
702 | \r | |
703 | /// Flags\r | |
ce306e48 PG |
704 | /// BIT0: 0: Interrupt is Level triggered\r |
705 | /// 1: Interrupt is Edge triggered\r | |
706 | /// BIT1: 0: Interrupt is Active high\r | |
707 | /// 1: Interrupt is Active low\r | |
26147c77 | 708 | UINT32 Flags;\r |
37568365 PG |
709 | } CM_ARM_GENERIC_INTERRUPT;\r |
710 | \r | |
711 | /** A structure that describes the SMMU interrupts for the Platform.\r | |
712 | \r | |
713 | Interrupt Interrupt number.\r | |
714 | Flags Interrupt flags as defined for SMMU node.\r | |
715 | \r | |
716 | ID: EArmObjSmmuInterruptArray\r | |
717 | */\r | |
718 | typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_SMMU_INTERRUPT;\r | |
719 | \r | |
720 | /** A structure that describes the AML Extended Interrupts.\r | |
721 | \r | |
722 | Interrupt Interrupt number.\r | |
723 | Flags Interrupt flags as defined by the Interrupt\r | |
724 | Vector Flags (Byte 3) of the Extended Interrupt\r | |
725 | resource descriptor.\r | |
726 | See EFI_ACPI_EXTENDED_INTERRUPT_FLAG_xxx in Acpi10.h\r | |
37568365 PG |
727 | */\r |
728 | typedef CM_ARM_GENERIC_INTERRUPT CM_ARM_EXTENDED_INTERRUPT;\r | |
26147c77 | 729 | \r |
77db1156 KK |
730 | /** A structure that describes the Processor Hierarchy Node (Type 0) in PPTT\r |
731 | \r | |
732 | ID: EArmObjProcHierarchyInfo\r | |
733 | */\r | |
734 | typedef struct CmArmProcHierarchyInfo {\r | |
735 | /// A unique token used to identify this object\r | |
731c67e1 | 736 | CM_OBJECT_TOKEN Token;\r |
77db1156 | 737 | /// Processor structure flags (ACPI 6.3 - January 2019, PPTT, Table 5-155)\r |
731c67e1 | 738 | UINT32 Flags;\r |
77db1156 KK |
739 | /// Token for the parent CM_ARM_PROC_HIERARCHY_INFO object in the processor\r |
740 | /// topology. A value of CM_NULL_TOKEN means this node has no parent.\r | |
731c67e1 | 741 | CM_OBJECT_TOKEN ParentToken;\r |
77db1156 KK |
742 | /// Token of the associated CM_ARM_GICC_INFO object which has the\r |
743 | /// corresponding ACPI Processor ID. A value of CM_NULL_TOKEN means this\r | |
744 | /// node represents a group of associated processors and it does not have an\r | |
745 | /// associated GIC CPU interface.\r | |
731c67e1 | 746 | CM_OBJECT_TOKEN GicCToken;\r |
77db1156 | 747 | /// Number of resources private to this Node\r |
731c67e1 | 748 | UINT32 NoOfPrivateResources;\r |
77db1156 KK |
749 | /// Token of the array which contains references to the resources private to\r |
750 | /// this CM_ARM_PROC_HIERARCHY_INFO instance. This field is ignored if\r | |
e3f8605a | 751 | /// the NoOfPrivateResources is 0, in which case it is recommended to set\r |
77db1156 | 752 | /// this field to CM_NULL_TOKEN.\r |
731c67e1 | 753 | CM_OBJECT_TOKEN PrivateResourcesArrayToken;\r |
f17ef10e PG |
754 | /// Optional field: Reference Token for the Lpi state of this processor.\r |
755 | /// Token identifying a CM_ARM_OBJ_REF structure, itself referencing\r | |
756 | /// CM_ARM_LPI_INFO objects.\r | |
731c67e1 | 757 | CM_OBJECT_TOKEN LpiToken;\r |
77db1156 KK |
758 | } CM_ARM_PROC_HIERARCHY_INFO;\r |
759 | \r | |
760 | /** A structure that describes the Cache Type Structure (Type 1) in PPTT\r | |
761 | \r | |
762 | ID: EArmObjCacheInfo\r | |
763 | */\r | |
764 | typedef struct CmArmCacheInfo {\r | |
765 | /// A unique token used to identify this object\r | |
731c67e1 | 766 | CM_OBJECT_TOKEN Token;\r |
77db1156 KK |
767 | /// Reference token for the next level of cache that is private to the same\r |
768 | /// CM_ARM_PROC_HIERARCHY_INFO instance. A value of CM_NULL_TOKEN means this\r | |
769 | /// entry represents the last cache level appropriate to the processor\r | |
770 | /// hierarchy node structures using this entry.\r | |
731c67e1 | 771 | CM_OBJECT_TOKEN NextLevelOfCacheToken;\r |
77db1156 | 772 | /// Size of the cache in bytes\r |
731c67e1 | 773 | UINT32 Size;\r |
77db1156 | 774 | /// Number of sets in the cache\r |
731c67e1 | 775 | UINT32 NumberOfSets;\r |
77db1156 KK |
776 | /// Integer number of ways. The maximum associativity supported by\r |
777 | /// ACPI Cache type structure is limited to MAX_UINT8. However,\r | |
778 | /// the maximum number of ways supported by the architecture is\r | |
779 | /// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field\r | |
780 | /// is 32-bit wide.\r | |
731c67e1 | 781 | UINT32 Associativity;\r |
e81a81e5 | 782 | /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)\r |
731c67e1 | 783 | UINT8 Attributes;\r |
77db1156 | 784 | /// Line size in bytes\r |
731c67e1 | 785 | UINT16 LineSize;\r |
e81a81e5 CJ |
786 | /// Unique ID for the cache\r |
787 | UINT32 CacheId;\r | |
77db1156 KK |
788 | } CM_ARM_CACHE_INFO;\r |
789 | \r | |
77db1156 KK |
790 | /** A structure that describes a reference to another Configuration Manager\r |
791 | object.\r | |
792 | \r | |
793 | This is useful for creating an array of reference tokens. The framework\r | |
794 | can then query the configuration manager for these arrays using the\r | |
795 | object ID EArmObjCmRef.\r | |
796 | \r | |
797 | This can be used is to represent one-to-many relationships between objects.\r | |
798 | \r | |
799 | ID: EArmObjCmRef\r | |
800 | */\r | |
801 | typedef struct CmArmObjRef {\r | |
802 | /// Token of the CM object being referenced\r | |
731c67e1 | 803 | CM_OBJECT_TOKEN ReferenceToken;\r |
77db1156 KK |
804 | } CM_ARM_OBJ_REF;\r |
805 | \r | |
f413d9be SM |
806 | /** A structure that describes the Memory Affinity Structure (Type 1) in SRAT\r |
807 | \r | |
808 | ID: EArmObjMemoryAffinityInfo\r | |
809 | */\r | |
810 | typedef struct CmArmMemoryAffinityInfo {\r | |
811 | /// The proximity domain to which the "range of memory" belongs.\r | |
731c67e1 | 812 | UINT32 ProximityDomain;\r |
f413d9be SM |
813 | \r |
814 | /// Base Address\r | |
731c67e1 | 815 | UINT64 BaseAddress;\r |
f413d9be SM |
816 | \r |
817 | /// Length\r | |
731c67e1 | 818 | UINT64 Length;\r |
f413d9be SM |
819 | \r |
820 | /// Flags\r | |
731c67e1 | 821 | UINT32 Flags;\r |
f413d9be SM |
822 | } CM_ARM_MEMORY_AFFINITY_INFO;\r |
823 | \r | |
824 | /** A structure that describes the ACPI Device Handle (Type 0) in the\r | |
825 | Generic Initiator Affinity structure in SRAT\r | |
826 | \r | |
827 | ID: EArmObjDeviceHandleAcpi\r | |
828 | */\r | |
829 | typedef struct CmArmDeviceHandleAcpi {\r | |
830 | /// Hardware ID\r | |
731c67e1 | 831 | UINT64 Hid;\r |
f413d9be SM |
832 | \r |
833 | /// Unique Id\r | |
731c67e1 | 834 | UINT32 Uid;\r |
f413d9be SM |
835 | } CM_ARM_DEVICE_HANDLE_ACPI;\r |
836 | \r | |
837 | /** A structure that describes the PCI Device Handle (Type 1) in the\r | |
838 | Generic Initiator Affinity structure in SRAT\r | |
839 | \r | |
840 | ID: EArmObjDeviceHandlePci\r | |
841 | */\r | |
842 | typedef struct CmArmDeviceHandlePci {\r | |
843 | /// PCI Segment Number\r | |
731c67e1 | 844 | UINT16 SegmentNumber;\r |
f413d9be SM |
845 | \r |
846 | /// PCI Bus Number - Max 256 busses (Bits 15:8 of BDF)\r | |
731c67e1 | 847 | UINT8 BusNumber;\r |
f413d9be | 848 | \r |
e3f8605a | 849 | /// PCI Device Number - Max 32 devices (Bits 7:3 of BDF)\r |
731c67e1 | 850 | UINT8 DeviceNumber;\r |
f413d9be SM |
851 | \r |
852 | /// PCI Function Number - Max 8 functions (Bits 2:0 of BDF)\r | |
731c67e1 | 853 | UINT8 FunctionNumber;\r |
f413d9be SM |
854 | } CM_ARM_DEVICE_HANDLE_PCI;\r |
855 | \r | |
856 | /** A structure that describes the Generic Initiator Affinity structure in SRAT\r | |
857 | \r | |
858 | ID: EArmObjGenericInitiatorAffinityInfo\r | |
859 | */\r | |
860 | typedef struct CmArmGenericInitiatorAffinityInfo {\r | |
861 | /// The proximity domain to which the generic initiator belongs.\r | |
731c67e1 | 862 | UINT32 ProximityDomain;\r |
f413d9be SM |
863 | \r |
864 | /// Flags\r | |
731c67e1 | 865 | UINT32 Flags;\r |
f413d9be SM |
866 | \r |
867 | /// Device Handle Type\r | |
731c67e1 | 868 | UINT8 DeviceHandleType;\r |
f413d9be SM |
869 | \r |
870 | /// Reference Token for the Device Handle\r | |
731c67e1 | 871 | CM_OBJECT_TOKEN DeviceHandleToken;\r |
f413d9be SM |
872 | } CM_ARM_GENERIC_INITIATOR_AFFINITY_INFO;\r |
873 | \r | |
37568365 PG |
874 | /** A structure that describes the CMN-600 hardware.\r |
875 | \r | |
876 | ID: EArmObjCmn600Info\r | |
877 | */\r | |
878 | typedef struct CmArmCmn600Info {\r | |
879 | /// The PERIPHBASE address.\r | |
880 | /// Corresponds to the Configuration Node Region (CFGR) base address.\r | |
731c67e1 | 881 | UINT64 PeriphBaseAddress;\r |
37568365 PG |
882 | \r |
883 | /// The PERIPHBASE address length.\r | |
884 | /// Corresponds to the CFGR base address length.\r | |
731c67e1 | 885 | UINT64 PeriphBaseAddressLength;\r |
37568365 PG |
886 | \r |
887 | /// The ROOTNODEBASE address.\r | |
888 | /// Corresponds to the Root node (ROOT) base address.\r | |
731c67e1 | 889 | UINT64 RootNodeBaseAddress;\r |
37568365 PG |
890 | \r |
891 | /// The Debug and Trace Logic Controller (DTC) count.\r | |
892 | /// CMN-600 can have maximum 4 DTCs.\r | |
731c67e1 | 893 | UINT8 DtcCount;\r |
37568365 PG |
894 | \r |
895 | /// DTC Interrupt list.\r | |
896 | /// The first interrupt resource descriptor pertains to\r | |
897 | /// DTC[0], the second to DTC[1] and so on.\r | |
898 | /// DtcCount determines the number of DTC Interrupts that\r | |
899 | /// are populated. If DTC count is 2 then DtcInterrupt[2]\r | |
900 | /// and DtcInterrupt[3] are ignored.\r | |
901 | /// Note: The size of CM_ARM_CMN_600_INFO structure remains\r | |
902 | /// constant and does not vary with the DTC count.\r | |
731c67e1 | 903 | CM_ARM_EXTENDED_INTERRUPT DtcInterrupt[4];\r |
37568365 PG |
904 | } CM_ARM_CMN_600_INFO;\r |
905 | \r | |
f17ef10e PG |
906 | /** A structure that describes the Lpi information.\r |
907 | \r | |
908 | The Low Power Idle states are described in DSDT/SSDT and associated\r | |
909 | to cpus/clusters in the cpu topology.\r | |
910 | \r | |
911 | ID: EArmObjLpiInfo\r | |
912 | */\r | |
913 | typedef struct CmArmLpiInfo {\r | |
914 | /** Minimum Residency. Time in microseconds after which a\r | |
915 | state becomes more energy efficient than any shallower state.\r | |
916 | */\r | |
731c67e1 | 917 | UINT32 MinResidency;\r |
f17ef10e PG |
918 | \r |
919 | /** Worst case time in microseconds from a wake interrupt\r | |
920 | being asserted to the return to a running state\r | |
921 | */\r | |
731c67e1 | 922 | UINT32 WorstCaseWakeLatency;\r |
f17ef10e PG |
923 | \r |
924 | /** Flags.\r | |
925 | */\r | |
731c67e1 | 926 | UINT32 Flags;\r |
f17ef10e PG |
927 | \r |
928 | /** Architecture specific context loss flags.\r | |
929 | */\r | |
731c67e1 | 930 | UINT32 ArchFlags;\r |
f17ef10e PG |
931 | \r |
932 | /** Residency counter frequency in cycles-per-second (Hz).\r | |
933 | */\r | |
731c67e1 | 934 | UINT32 ResCntFreq;\r |
f17ef10e PG |
935 | \r |
936 | /** Every shallower power state in the parent is also enabled.\r | |
937 | */\r | |
731c67e1 | 938 | UINT32 EnableParentState;\r |
f17ef10e PG |
939 | \r |
940 | /** The EntryMethod _LPI field can be described as an integer\r | |
941 | or in a Register resource data descriptor.\r | |
942 | \r | |
943 | If IsInteger is TRUE, the IntegerEntryMethod field is used.\r | |
944 | If IsInteger is FALSE, the RegisterEntryMethod field is used.\r | |
945 | */\r | |
731c67e1 | 946 | BOOLEAN IsInteger;\r |
f17ef10e PG |
947 | \r |
948 | /** EntryMethod described as an Integer.\r | |
949 | */\r | |
731c67e1 | 950 | UINT64 IntegerEntryMethod;\r |
f17ef10e PG |
951 | \r |
952 | /** EntryMethod described as a EFI_ACPI_GENERIC_REGISTER_DESCRIPTOR.\r | |
953 | */\r | |
731c67e1 | 954 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE RegisterEntryMethod;\r |
f17ef10e PG |
955 | \r |
956 | /** Residency counter register.\r | |
957 | */\r | |
731c67e1 | 958 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE ResidencyCounterRegister;\r |
f17ef10e PG |
959 | \r |
960 | /** Usage counter register.\r | |
961 | */\r | |
731c67e1 | 962 | EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE UsageCounterRegister;\r |
f17ef10e PG |
963 | \r |
964 | /** String representing the Lpi state\r | |
965 | */\r | |
731c67e1 | 966 | CHAR8 StateName[16];\r |
f17ef10e PG |
967 | } CM_ARM_LPI_INFO;\r |
968 | \r | |
ce306e48 PG |
969 | /** A structure that describes a PCI Address Map.\r |
970 | \r | |
971 | The memory-ranges used by the PCI bus are described by this object.\r | |
972 | \r | |
973 | ID: EArmObjPciAddressMapInfo\r | |
974 | */\r | |
975 | typedef struct CmArmPciAddressMapInfo {\r | |
976 | /** Pci address space code\r | |
977 | \r | |
978 | Available values are:\r | |
979 | - 0: Configuration Space\r | |
980 | - 1: I/O Space\r | |
981 | - 2: 32-bit-address Memory Space\r | |
982 | - 3: 64-bit-address Memory Space\r | |
983 | */\r | |
984 | UINT8 SpaceCode;\r | |
985 | \r | |
986 | /// PCI address\r | |
987 | UINT64 PciAddress;\r | |
988 | \r | |
989 | /// Cpu address\r | |
990 | UINT64 CpuAddress;\r | |
991 | \r | |
992 | /// Address size\r | |
993 | UINT64 AddressSize;\r | |
994 | } CM_ARM_PCI_ADDRESS_MAP_INFO;\r | |
995 | \r | |
996 | /** A structure that describes a PCI Interrupt Map.\r | |
997 | \r | |
998 | The legacy PCI interrupts used by PCI devices are described by this object.\r | |
999 | \r | |
1000 | Cf Devicetree Specification - Release v0.3\r | |
1001 | s2.4.3 "Interrupt Nexus Properties"\r | |
1002 | \r | |
1003 | ID: EArmObjPciInterruptMapInfo\r | |
1004 | */\r | |
1005 | typedef struct CmArmPciInterruptMapInfo {\r | |
1006 | /// Pci Bus.\r | |
1007 | /// Value on 8 bits (max 255).\r | |
1008 | UINT8 PciBus;\r | |
1009 | \r | |
1010 | /// Pci Bus.\r | |
1011 | /// Value on 5 bits (max 31).\r | |
1012 | UINT8 PciDevice;\r | |
1013 | \r | |
1014 | /** PCI interrupt\r | |
1015 | \r | |
1016 | ACPI bindings are used:\r | |
1017 | Cf. ACPI 6.4, s6.2.13 _PRT (PCI Routing Table):\r | |
1018 | "0-INTA, 1-INTB, 2-INTC, 3-INTD"\r | |
1019 | \r | |
1020 | Device-tree bindings are shifted by 1:\r | |
1021 | "INTA=1, INTB=2, INTC=3, INTD=4"\r | |
1022 | */\r | |
1023 | UINT8 PciInterrupt;\r | |
1024 | \r | |
1025 | /** Interrupt controller interrupt.\r | |
1026 | \r | |
1027 | Cf Devicetree Specification - Release v0.3\r | |
1028 | s2.4.3 "Interrupt Nexus Properties": "parent interrupt specifier"\r | |
1029 | */\r | |
1030 | CM_ARM_GENERIC_INTERRUPT IntcInterrupt;\r | |
1031 | } CM_ARM_PCI_INTERRUPT_MAP_INFO;\r | |
1032 | \r | |
de200b7e SM |
1033 | /** A structure that describes the\r |
1034 | RMR node for the Platform.\r | |
1035 | \r | |
1036 | ID: EArmObjRmr\r | |
1037 | */\r | |
1038 | typedef struct CmArmRmrNode {\r | |
1039 | /// An unique token used to identify this object\r | |
1040 | CM_OBJECT_TOKEN Token;\r | |
1041 | /// Number of ID mappings\r | |
1042 | UINT32 IdMappingCount;\r | |
1043 | /// Reference token for the ID mapping array\r | |
1044 | CM_OBJECT_TOKEN IdMappingToken;\r | |
1045 | \r | |
1046 | /// Unique identifier for this node.\r | |
1047 | UINT32 Identifier;\r | |
1048 | \r | |
1049 | /// Reserved Memory Range flags.\r | |
1050 | UINT32 Flags;\r | |
1051 | \r | |
1052 | /// Memory range descriptor count.\r | |
1053 | UINT32 MemRangeDescCount;\r | |
1054 | /// Reference token for the Memory Range descriptor array\r | |
1055 | CM_OBJECT_TOKEN MemRangeDescToken;\r | |
1056 | } CM_ARM_RMR_NODE;\r | |
1057 | \r | |
1058 | /** A structure that describes the\r | |
1059 | Memory Range descriptor.\r | |
1060 | \r | |
1061 | ID: EArmObjMemoryRangeDescriptor\r | |
1062 | */\r | |
1063 | typedef struct CmArmRmrDescriptor {\r | |
1064 | /// Base address of Reserved Memory Range,\r | |
1065 | /// aligned to a page size of 64K.\r | |
1066 | UINT64 BaseAddress;\r | |
1067 | \r | |
1068 | /// Length of the Reserved Memory range.\r | |
1069 | /// Must be a multiple of the page size of 64K.\r | |
1070 | UINT64 Length;\r | |
1071 | } CM_ARM_MEMORY_RANGE_DESCRIPTOR;\r | |
1072 | \r | |
26147c77 SM |
1073 | #pragma pack()\r |
1074 | \r | |
1075 | #endif // ARM_NAMESPACE_OBJECTS_H_\r |