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3eb9473e | 1 | TITLE Cpu.asm: Assembly code for the x64 resources\r |
2 | \r | |
3 | ;------------------------------------------------------------------------------\r | |
4 | ;*\r | |
5 | ;* Copyright (c) 2005 - 2007, Intel Corporation \r | |
6 | ;* All rights reserved. This program and the accompanying materials \r | |
7 | ;* are licensed and made available under the terms and conditions of the BSD License \r | |
8 | ;* which accompanies this distribution. The full text of the license may be found at \r | |
9 | ;* http://opensource.org/licenses/bsd-license.php \r | |
10 | ;* \r | |
11 | ;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | ;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | ;* \r | |
14 | ;* Module Name:\r | |
15 | ;*\r | |
16 | ;* Cpu.asm\r | |
17 | ;* \r | |
18 | ;* Abstract:\r | |
19 | ;* \r | |
20 | ;------------------------------------------------------------------------------\r | |
21 | \r | |
22 | text SEGMENT\r | |
23 | \r | |
24 | \r | |
25 | ;------------------------------------------------------------------------------\r | |
26 | ; VOID\r | |
27 | ; EfiHalt (\r | |
28 | ; VOID\r | |
29 | ; )\r | |
30 | ;------------------------------------------------------------------------------\r | |
31 | EfiHalt PROC PUBLIC\r | |
32 | hlt\r | |
33 | ret\r | |
34 | EfiHalt ENDP\r | |
35 | \r | |
36 | \r | |
37 | ;------------------------------------------------------------------------------\r | |
38 | ; VOID\r | |
39 | ; EfiWbinvd (\r | |
40 | ; VOID\r | |
41 | ; )\r | |
42 | ;------------------------------------------------------------------------------\r | |
43 | EfiWbinvd PROC PUBLIC\r | |
44 | wbinvd\r | |
45 | ret\r | |
46 | EfiWbinvd ENDP\r | |
47 | \r | |
48 | \r | |
49 | ;------------------------------------------------------------------------------\r | |
50 | ; VOID\r | |
51 | ; EfiInvd (\r | |
52 | ; VOID\r | |
53 | ; )\r | |
54 | ;------------------------------------------------------------------------------\r | |
55 | EfiInvd PROC PUBLIC\r | |
56 | invd\r | |
57 | ret\r | |
58 | EfiInvd ENDP\r | |
59 | \r | |
60 | ;------------------------------------------------------------------------------\r | |
61 | ; VOID\r | |
62 | ; EfiCpuid (\r | |
63 | ; IN UINT32 RegisterInEax, // rcx \r | |
64 | ; OUT EFI_CPUID_REGISTER *Reg OPTIONAL // rdx \r | |
65 | ; )\r | |
66 | ;------------------------------------------------------------------------------\r | |
67 | EfiCpuid PROC PUBLIC\r | |
68 | push rbx\r | |
69 | \r | |
70 | mov r8, rdx ; r8 = *Reg\r | |
71 | mov rax, rcx ; RegisterInEax\r | |
72 | cpuid\r | |
73 | cmp r8, 0\r | |
74 | je _Exit\r | |
75 | mov [r8 + 0], eax ; Reg->RegEax\r | |
76 | mov [r8 + 4], ebx ; Reg->RegEbx\r | |
77 | mov [r8 + 8], ecx ; Reg->RegEcx\r | |
78 | mov [r8 + 12], edx ; Reg->RegEdx\r | |
79 | \r | |
80 | _Exit:\r | |
81 | pop rbx\r | |
82 | ret\r | |
83 | EfiCpuid ENDP\r | |
84 | \r | |
85 | ;------------------------------------------------------------------------------\r | |
86 | ; UINT64\r | |
87 | ; EfiReadMsr (\r | |
88 | ; IN UINT32 Index, // rcx\r | |
89 | ; )\r | |
90 | ;------------------------------------------------------------------------------\r | |
91 | EfiReadMsr PROC PUBLIC \r | |
92 | rdmsr\r | |
93 | sal rdx, 32 ; edx:eax -> rax\r | |
94 | or rax, rdx ; rax = edx:eax\r | |
95 | ret\r | |
96 | EfiReadMsr ENDP\r | |
97 | \r | |
98 | ;------------------------------------------------------------------------------\r | |
99 | ; VOID\r | |
100 | ; EfiWriteMsr (\r | |
101 | ; IN UINT32 Index, // rcx\r | |
102 | ; IN UINT64 Value // rdx\r | |
103 | ; )\r | |
104 | ;------------------------------------------------------------------------------\r | |
105 | EfiWriteMsr PROC PUBLIC\r | |
106 | mov rax, rdx ; rdx = Value\r | |
107 | sar rdx, 32 ; convert rdx to edx upper 32-bits \r | |
108 | wrmsr ; wrmsr[ecx] result = edx:eax\r | |
109 | ret\r | |
110 | EfiWriteMsr ENDP\r | |
111 | \r | |
112 | \r | |
113 | ;------------------------------------------------------------------------------\r | |
114 | ; UINT64\r | |
115 | ; EfiReadTsc (\r | |
116 | ; VOID\r | |
117 | ; );\r | |
118 | ;------------------------------------------------------------------------------\r | |
119 | EfiReadTsc PROC PUBLIC\r | |
120 | rdtsc\r | |
121 | shl rax, 32\r | |
122 | shrd rax, rdx, 32\r | |
123 | ret\r | |
124 | EfiReadTsc ENDP\r | |
125 | \r | |
126 | ;------------------------------------------------------------------------------\r | |
127 | ; VOID\r | |
128 | ; EfiDisableCache (\r | |
129 | ; VOID\r | |
130 | ; );\r | |
131 | ;------------------------------------------------------------------------------\r | |
132 | EfiDisableCache PROC PUBLIC\r | |
133 | ; added a check to see if cache is already disabled. If it is, then skip.\r | |
134 | mov rax, cr0\r | |
135 | and rax, 060000000h \r | |
136 | cmp rax, 0\r | |
137 | jne @f\r | |
138 | wbinvd\r | |
139 | mov rax, cr0\r | |
140 | or rax, 060000000h \r | |
141 | mov cr0, rax\r | |
142 | @@:\r | |
143 | ret\r | |
144 | EfiDisableCache ENDP\r | |
145 | \r | |
146 | ;------------------------------------------------------------------------------\r | |
147 | ; VOID\r | |
148 | ; EfiEnableCache (\r | |
149 | ; VOID\r | |
150 | ; );\r | |
151 | ;------------------------------------------------------------------------------\r | |
152 | EfiEnableCache PROC PUBLIC\r | |
153 | invd\r | |
154 | mov rax, cr0\r | |
155 | and rax, 09fffffffh \r | |
156 | mov cr0, rax\r | |
157 | ret\r | |
158 | EfiEnableCache ENDP\r | |
159 | \r | |
160 | ;------------------------------------------------------------------------------\r | |
161 | ; UINTN\r | |
162 | ; EfiGetEflags (\r | |
163 | ; VOID\r | |
164 | ; );\r | |
165 | ;------------------------------------------------------------------------------\r | |
166 | EfiGetEflags PROC PUBLIC\r | |
167 | pushfq\r | |
168 | pop rax\r | |
169 | ret\r | |
170 | EfiGetEflags ENDP\r | |
171 | \r | |
172 | ;------------------------------------------------------------------------------\r | |
173 | ; VOID\r | |
174 | ; EfiDisableInterrupts (\r | |
175 | ; VOID\r | |
176 | ; );\r | |
177 | ;------------------------------------------------------------------------------\r | |
178 | EfiDisableInterrupts PROC PUBLIC\r | |
179 | cli\r | |
180 | ret\r | |
181 | EfiDisableInterrupts ENDP\r | |
182 | \r | |
183 | ;------------------------------------------------------------------------------\r | |
184 | ; VOID\r | |
185 | ; EfiEnableInterrupts (\r | |
186 | ; VOID\r | |
187 | ; );\r | |
188 | ;------------------------------------------------------------------------------\r | |
189 | EfiEnableInterrupts PROC PUBLIC\r | |
190 | sti\r | |
191 | ret\r | |
192 | EfiEnableInterrupts ENDP\r | |
193 | ;------------------------------------------------------------------------------\r | |
194 | ; VOID\r | |
195 | ; EfiCpuidExt (\r | |
196 | ; IN UINT32 RegisterInEax,\r | |
197 | ; IN UINT32 CacheLevel,\r | |
198 | ; OUT EFI_CPUID_REGISTER *Regs \r | |
199 | ; )\r | |
200 | ;------------------------------------------------------------------------------\r | |
201 | EfiCpuidExt PROC PUBLIC\r | |
202 | push rbx\r | |
203 | mov rax, rcx ; rax = RegisterInEax\r | |
204 | mov rcx, rdx ; rcx = CacheLevel\r | |
205 | \r | |
206 | cpuid\r | |
207 | mov [r8 + 0 ], eax ; Reg->RegEax\r | |
208 | mov [r8 + 4 ], ebx ; Reg->RegEbx\r | |
209 | mov [r8 + 8 ], ecx ; Reg->RegEcx\r | |
210 | mov [r8 + 12], edx ; Reg->RegEdx\r | |
211 | \r | |
212 | pop rbx\r | |
213 | ret\r | |
214 | EfiCpuidExt ENDP\r | |
215 | END\r |