[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Cpu / Pentium / Include / CpuIA32.h

/*++\r
\r
Copyright (c) 2004 - 2006, Intel Corporation                                                         \r
All rights reserved. This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
\r
  CpuIA32.h\r
\r
Abstract:\r
\r
--*/\r
\r
#ifndef _CPU_IA32_H\r
#define _CPU_IA32_H\r
\r
#include "Tiano.h"\r
\r
#define IA32API __cdecl\r
\r
typedef struct {\r
  UINT32  RegEax;\r
  UINT32  RegEbx;\r
  UINT32  RegEcx;\r
  UINT32  RegEdx;\r
} EFI_CPUID_REGISTER;\r
\r
typedef struct {\r
  UINT32  HeaderVersion;\r
  UINT32  UpdateRevision;\r
  UINT32  Date;\r
  UINT32  ProcessorId;\r
  UINT32  Checksum;\r
  UINT32  LoaderRevision;\r
  UINT32  ProcessorFlags;\r
  UINT32  DataSize;\r
  UINT32  TotalSize;\r
  UINT8   Reserved[12];\r
} EFI_CPU_MICROCODE_HEADER;\r
\r
typedef struct {\r
  UINT32  ExtendedSignatureCount;\r
  UINT32  ExtendedTableChecksum;  \r
  UINT8   Reserved[12];\r
} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
\r
typedef struct {\r
  UINT32  ProcessorSignature;\r
  UINT32  ProcessorFlag;\r
  UINT32  ProcessorChecksum;\r
} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
\r
typedef struct {\r
  UINT32  Stepping       : 4;\r
  UINT32  Model          : 4;\r
  UINT32  Family         : 4;\r
  UINT32  Type           : 2;\r
  UINT32  Reserved1      : 2;\r
  UINT32  ExtendedModel  : 4;\r
  UINT32  ExtendedFamily : 8;\r
  UINT32  Reserved2      : 4;\r
} EFI_CPU_VERSION;\r
\r
#define EFI_CPUID_SIGNATURE                   0x0\r
#define EFI_CPUID_VERSION_INFO                0x1\r
#define EFI_CPUID_CACHE_INFO                  0x2\r
#define EFI_CPUID_SERIAL_NUMBER               0x3\r
#define EFI_CPUID_EXTENDED_FUNCTION           0x80000000\r
#define EFI_CPUID_EXTENDED_CPU_SIG            0x80000001\r
#define EFI_CPUID_BRAND_STRING1               0x80000002\r
#define EFI_CPUID_BRAND_STRING2               0x80000003\r
#define EFI_CPUID_BRAND_STRING3               0x80000004\r
\r
#define EFI_MSR_IA32_PLATFORM_ID              0x17\r
#define EFI_MSR_IA32_APIC_BASE                0x1B\r
#define EFI_MSR_EBC_HARD_POWERON              0x2A\r
#define EFI_MSR_EBC_SOFT_POWERON              0x2B\r
#define BINIT_DRIVER_DISABLE                  0x40\r
#define INTERNAL_MCERR_DISABLE                0x20\r
#define INITIATOR_MCERR_DISABLE               0x10\r
#define EFI_MSR_EBC_FREQUENCY_ID              0x2C\r
#define EFI_MSR_IA32_BIOS_UPDT_TRIG           0x79\r
#define EFI_MSR_IA32_BIOS_SIGN_ID             0x8B\r
#define EFI_MSR_PSB_CLOCK_STATUS              0xCD\r
#define EFI_APIC_GLOBAL_ENABLE                0x800\r
#define EFI_MSR_IA32_MISC_ENABLE              0x1A0\r
#define LIMIT_CPUID_MAXVAL_ENABLE_BIT         0x00400000\r
#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT  0x00000008\r
#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT      0x00000004\r
#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002\r
#define FAST_STRING_ENABLE_BIT                0x00000001\r
\r
#define EFI_CACHE_VARIABLE_MTRR_BASE          0x200\r
#define EFI_CACHE_VARIABLE_MTRR_END           0x20F\r
#define EFI_CACHE_IA32_MTRR_DEF_TYPE          0x2FF\r
#define EFI_CACHE_MTRR_VALID                  0x800\r
#define EFI_CACHE_FIXED_MTRR_VALID            0x400\r
#define EFI_CACHE_VALID_ADDRESS               0xFFFFFF000\r
#define EFI_MSR_VALID_MASK                    0xFFFFFFFFF\r
#define EFI_CACHE_VALID_EXTENDED_ADDRESS      0xFFFFFFFFFF000\r
#define EFI_MSR_VALID_EXTENDED_MASK           0xFFFFFFFFFFFFF\r
\r
#define EFI_IA32_MTRR_FIX64K_00000            0x250\r
#define EFI_IA32_MTRR_FIX16K_80000            0x258\r
#define EFI_IA32_MTRR_FIX16K_A0000            0x259\r
#define EFI_IA32_MTRR_FIX4K_C0000             0x268\r
#define EFI_IA32_MTRR_FIX4K_C8000             0x269\r
#define EFI_IA32_MTRR_FIX4K_D0000             0x26A\r
#define EFI_IA32_MTRR_FIX4K_D8000             0x26B\r
#define EFI_IA32_MTRR_FIX4K_E0000             0x26C\r
#define EFI_IA32_MTRR_FIX4K_E8000             0x26D\r
#define EFI_IA32_MTRR_FIX4K_F0000             0x26E\r
#define EFI_IA32_MTRR_FIX4K_F8000             0x26F\r
\r
#define EFI_IA32_MCG_CAP                      0x179\r
#define EFI_IA32_MCG_CTL                      0x17B\r
#define EFI_IA32_MC0_CTL                      0x400\r
#define EFI_IA32_MC0_STATUS                   0x401\r
\r
#define EFI_IA32_PERF_STATUS                  0x198\r
#define EFI_IA32_PERF_CTL                     0x199\r
\r
#define EFI_CACHE_UNCACHEABLE                 0\r
#define EFI_CACHE_WRITECOMBINING              1\r
#define EFI_CACHE_WRITETHROUGH                4\r
#define EFI_CACHE_WRITEPROTECTED              5\r
#define EFI_CACHE_WRITEBACK                   6\r
\r
//\r
// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number\r
//\r
#define EfiMakeCpuVersion(f, m, s)         \\r
  (((UINT32) (f) << 16) | ((UINT32) (m) << 8) | ((UINT32) (s)))\r
\r
VOID\r
IA32API\r
EfiHalt (\r
  VOID\r
  );\r
\r
/*++                                                                                                                               \r
Routine Description:                                                \r
  Halt the Cpu    \r
Arguments:                \r
   None                                                          \r
Returns:                                                            \r
   None                                                \r
--*/\r
VOID\r
IA32API\r
EfiWbinvd (\r
  VOID\r
  );\r
\r
/*++                                                                                                                               \r
Routine Description:                                                \r
  Write back and invalidate the Cpu cache\r
Arguments:                \r
   None                                                          \r
Returns:                                                            \r
   None                                                \r
--*/\r
VOID\r
IA32API\r
EfiInvd (\r
  VOID\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Invalidate the Cpu cache\r
Arguments:                \r
   None                                                          \r
Returns:                                                            \r
   None                                                \r
--*/\r
VOID\r
IA32API\r
EfiCpuid (\r
  IN  UINT32                 RegisterInEax,\r
  OUT EFI_CPUID_REGISTER     *Regs\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Get the Cpu info by excute the CPUID instruction\r
Arguments:                \r
   RegisterInEax: -The input value to put into register EAX\r
   Regs:          -The Output value                      \r
Returns:                                                            \r
   None                                                \r
--*/\r
\r
VOID\r
IA32API\r
EfiCpuidExt (\r
  IN  UINT32                 RegisterInEax,\r
  IN  UINT32                 CacheLevel,\r
  OUT EFI_CPUID_REGISTER     *Regs\r
  )\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  When RegisterInEax != 4, the functionality is the same as EfiCpuid.\r
  When RegisterInEax == 4, the function return the deterministic cache\r
  parameters by excuting the CPUID instruction\r
Arguments:                \r
   RegisterInEax: - The input value to put into register EAX\r
   CacheLevel:      - The deterministic cache level\r
   Regs:          - The Output value                      \r
Returns:                                                            \r
   None                                                \r
--*/\r
;\r
\r
UINT64\r
IA32API\r
EfiReadMsr (\r
  IN UINT32     Index\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Read Cpu MSR\r
Arguments:                \r
  Index: -The index value to select the register\r
                       \r
Returns:                                                            \r
   Return the read data                                                \r
--*/\r
VOID\r
IA32API\r
EfiWriteMsr (\r
  IN UINT32     Index,\r
  IN UINT64     Value\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Write Cpu MSR\r
Arguments:                \r
  Index: -The index value to select the register\r
  Value: -The value to write to the selected register                      \r
Returns:                                                            \r
   None                                                \r
--*/\r
UINT64\r
IA32API\r
EfiReadTsc (\r
  VOID\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Read Time stamp\r
Arguments:                \r
  None                 \r
Returns:                                                            \r
   Return the read data                                                \r
--*/\r
VOID\r
IA32API\r
EfiDisableCache (\r
  VOID\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Writing back and invalidate the cache,then diable it\r
Arguments:                \r
  None                 \r
Returns:                                                            \r
  None                                               \r
--*/\r
VOID\r
IA32API\r
EfiEnableCache (\r
  VOID\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Invalidate the cache,then Enable it\r
Arguments:                \r
  None                 \r
Returns:                                                            \r
  None                                               \r
--*/\r
UINT32\r
IA32API\r
EfiGetEflags (\r
  VOID\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Get Eflags\r
Arguments:                \r
  None                 \r
Returns:                                                            \r
  Return the Eflags value                                               \r
--*/\r
VOID\r
IA32API\r
EfiDisableInterrupts (\r
  VOID\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Disable Interrupts\r
Arguments:                \r
  None                 \r
Returns:                                                            \r
  None\r
--*/\r
VOID\r
IA32API\r
EfiEnableInterrupts (\r
  VOID\r
  );\r
\r
/*++                                                                                                                          \r
Routine Description:                                                \r
  Enable Interrupts\r
Arguments:                \r
  None                 \r
Returns:                                                            \r
  None                                               \r
--*/\r
\r
\r
VOID\r
IA32API\r
EfiCpuVersion (\r
  IN   UINT16  *FamilyId,    OPTIONAL\r
  IN   UINT8   *Model,       OPTIONAL\r
  IN   UINT8   *SteppingId,  OPTIONAL\r
  IN   UINT8   *Processor    OPTIONAL\r
  )\r
/*++\r
\r
Routine Description:\r
  Extract CPU detail version infomation\r
\r
Arguments:\r
  FamilyId   - FamilyId, including ExtendedFamilyId\r
  Model      - Model, including ExtendedModel\r
  SteppingId - SteppingId\r
  Processor  - Processor\r
\r
--*/\r
;\r
\r
#endif\r
Commit	Line	Data
3eb9473e	1	/*++\r
	2	\r
	3	Copyright (c) 2004 - 2006, Intel Corporation \r
	4	All rights reserved. This program and the accompanying materials \r
	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	\r
	14	CpuIA32.h\r
	15	\r
	16	Abstract:\r
	17	\r
	18	--*/\r
	19	\r
	20	#ifndef _CPU_IA32_H\r
	21	#define _CPU_IA32_H\r
	22	\r
	23	#include "Tiano.h"\r
	24	\r
	25	#define IA32API __cdecl\r
	26	\r
	27	typedef struct {\r
	28	UINT32 RegEax;\r
	29	UINT32 RegEbx;\r
	30	UINT32 RegEcx;\r
	31	UINT32 RegEdx;\r
	32	} EFI_CPUID_REGISTER;\r
	33	\r
	34	typedef struct {\r
	35	UINT32 HeaderVersion;\r
	36	UINT32 UpdateRevision;\r
	37	UINT32 Date;\r
	38	UINT32 ProcessorId;\r
	39	UINT32 Checksum;\r
	40	UINT32 LoaderRevision;\r
	41	UINT32 ProcessorFlags;\r
	42	UINT32 DataSize;\r
	43	UINT32 TotalSize;\r
	44	UINT8 Reserved[12];\r
	45	} EFI_CPU_MICROCODE_HEADER;\r
	46	\r
	47	typedef struct {\r
	48	UINT32 ExtendedSignatureCount;\r
	49	UINT32 ExtendedTableChecksum; \r
	50	UINT8 Reserved[12];\r
	51	} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
	52	\r
	53	typedef struct {\r
	54	UINT32 ProcessorSignature;\r
	55	UINT32 ProcessorFlag;\r
	56	UINT32 ProcessorChecksum;\r
	57	} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
	58	\r
	59	typedef struct {\r
	60	UINT32 Stepping : 4;\r
	61	UINT32 Model : 4;\r
	62	UINT32 Family : 4;\r
	63	UINT32 Type : 2;\r
	64	UINT32 Reserved1 : 2;\r
65	UINT32 ExtendedModel : 4;\r
66	UINT32 ExtendedFamily : 8;\r
67	UINT32 Reserved2 : 4;\r
68	} EFI_CPU_VERSION;\r
69	\r
70	#define EFI_CPUID_SIGNATURE 0x0\r
71	#define EFI_CPUID_VERSION_INFO 0x1\r
72	#define EFI_CPUID_CACHE_INFO 0x2\r
73	#define EFI_CPUID_SERIAL_NUMBER 0x3\r
74	#define EFI_CPUID_EXTENDED_FUNCTION 0x80000000\r
75	#define EFI_CPUID_EXTENDED_CPU_SIG 0x80000001\r
76	#define EFI_CPUID_BRAND_STRING1 0x80000002\r
77	#define EFI_CPUID_BRAND_STRING2 0x80000003\r
78	#define EFI_CPUID_BRAND_STRING3 0x80000004\r
79	\r
80	#define EFI_MSR_IA32_PLATFORM_ID 0x17\r
81	#define EFI_MSR_IA32_APIC_BASE 0x1B\r
82	#define EFI_MSR_EBC_HARD_POWERON 0x2A\r
83	#define EFI_MSR_EBC_SOFT_POWERON 0x2B\r
84	#define BINIT_DRIVER_DISABLE 0x40\r
85	#define INTERNAL_MCERR_DISABLE 0x20\r
86	#define INITIATOR_MCERR_DISABLE 0x10\r
87	#define EFI_MSR_EBC_FREQUENCY_ID 0x2C\r
88	#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r
89	#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8B\r
90	#define EFI_MSR_PSB_CLOCK_STATUS 0xCD\r
91	#define EFI_APIC_GLOBAL_ENABLE 0x800\r
92	#define EFI_MSR_IA32_MISC_ENABLE 0x1A0\r
93	#define LIMIT_CPUID_MAXVAL_ENABLE_BIT 0x00400000\r
94	#define AUTOMATIC_THERMAL_CONTROL_ENABLE_BIT 0x00000008\r
95	#define COMPATIBLE_FPU_OPCODE_ENABLE_BIT 0x00000004\r
96	#define LOGICAL_PROCESSOR_PRIORITY_ENABLE_BIT 0x00000002\r
97	#define FAST_STRING_ENABLE_BIT 0x00000001\r
98	\r
99	#define EFI_CACHE_VARIABLE_MTRR_BASE 0x200\r
100	#define EFI_CACHE_VARIABLE_MTRR_END 0x20F\r
101	#define EFI_CACHE_IA32_MTRR_DEF_TYPE 0x2FF\r
102	#define EFI_CACHE_MTRR_VALID 0x800\r
103	#define EFI_CACHE_FIXED_MTRR_VALID 0x400\r
104	#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
105	#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
106	#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000\r
107	#define EFI_MSR_VALID_EXTENDED_MASK 0xFFFFFFFFFFFFF\r
108	\r
109	#define EFI_IA32_MTRR_FIX64K_00000 0x250\r
110	#define EFI_IA32_MTRR_FIX16K_80000 0x258\r
111	#define EFI_IA32_MTRR_FIX16K_A0000 0x259\r
112	#define EFI_IA32_MTRR_FIX4K_C0000 0x268\r
113	#define EFI_IA32_MTRR_FIX4K_C8000 0x269\r
114	#define EFI_IA32_MTRR_FIX4K_D0000 0x26A\r
115	#define EFI_IA32_MTRR_FIX4K_D8000 0x26B\r
116	#define EFI_IA32_MTRR_FIX4K_E0000 0x26C\r
117	#define EFI_IA32_MTRR_FIX4K_E8000 0x26D\r
118	#define EFI_IA32_MTRR_FIX4K_F0000 0x26E\r
119	#define EFI_IA32_MTRR_FIX4K_F8000 0x26F\r
120	\r
121	#define EFI_IA32_MCG_CAP 0x179\r
122	#define EFI_IA32_MCG_CTL 0x17B\r
123	#define EFI_IA32_MC0_CTL 0x400\r
124	#define EFI_IA32_MC0_STATUS 0x401\r
125	\r
126	#define EFI_IA32_PERF_STATUS 0x198\r
127	#define EFI_IA32_PERF_CTL 0x199\r
128	\r
129	#define EFI_CACHE_UNCACHEABLE 0\r
130	#define EFI_CACHE_WRITECOMBINING 1\r
131	#define EFI_CACHE_WRITETHROUGH 4\r
132	#define EFI_CACHE_WRITEPROTECTED 5\r
133	#define EFI_CACHE_WRITEBACK 6\r
134	\r
135	//\r
136	// Combine f(FamilyId), m(Model), s(SteppingId) to a single 32 bit number\r
137	//\r
138	#define EfiMakeCpuVersion(f, m, s) \\r
139	(((UINT32) (f) << 16) \| ((UINT32) (m) << 8) \| ((UINT32) (s)))\r
140	\r
141	VOID\r
142	IA32API\r
143	EfiHalt (\r
144	VOID\r
e00e1d46	145	);\r
3eb9473e	146	\r
	147	/*++ \r
	148	Routine Description: \r
	149	Halt the Cpu \r
	150	Arguments: \r
	151	None \r
	152	Returns: \r
	153	None \r
	154	--*/\r
	155	VOID\r
	156	IA32API\r
	157	EfiWbinvd (\r
	158	VOID\r
e00e1d46	159	);\r
3eb9473e	160	\r
	161	/*++ \r
	162	Routine Description: \r
	163	Write back and invalidate the Cpu cache\r
	164	Arguments: \r
	165	None \r
	166	Returns: \r
	167	None \r
	168	--*/\r
	169	VOID\r
	170	IA32API\r
	171	EfiInvd (\r
	172	VOID\r
e00e1d46	173	);\r
3eb9473e	174	\r
	175	/*++ \r
	176	Routine Description: \r
	177	Invalidate the Cpu cache\r
	178	Arguments: \r
	179	None \r
	180	Returns: \r
	181	None \r
	182	--*/\r
	183	VOID\r
	184	IA32API\r
	185	EfiCpuid (\r
	186	IN UINT32 RegisterInEax,\r
	187	OUT EFI_CPUID_REGISTER *Regs\r
e00e1d46	188	);\r
3eb9473e	189	\r
	190	/*++ \r
	191	Routine Description: \r
	192	Get the Cpu info by excute the CPUID instruction\r
	193	Arguments: \r
	194	RegisterInEax: -The input value to put into register EAX\r
	195	Regs: -The Output value \r
	196	Returns: \r
	197	None \r
	198	--*/\r
	199	\r
	200	VOID\r
	201	IA32API\r
	202	EfiCpuidExt (\r
	203	IN UINT32 RegisterInEax,\r
	204	IN UINT32 CacheLevel,\r
	205	OUT EFI_CPUID_REGISTER *Regs\r
	206	)\r
	207	/*++ \r
	208	Routine Description: \r
	209	When RegisterInEax != 4, the functionality is the same as EfiCpuid.\r
	210	When RegisterInEax == 4, the function return the deterministic cache\r
	211	parameters by excuting the CPUID instruction\r
	212	Arguments: \r
	213	RegisterInEax: - The input value to put into register EAX\r
	214	CacheLevel: - The deterministic cache level\r
	215	Regs: - The Output value \r
	216	Returns: \r
	217	None \r
	218	--*/\r
	219	;\r
	220	\r
	221	UINT64\r
	222	IA32API\r
	223	EfiReadMsr (\r
	224	IN UINT32 Index\r
e00e1d46	225	);\r
3eb9473e	226	\r
	227	/*++ \r
	228	Routine Description: \r
	229	Read Cpu MSR\r
	230	Arguments: \r
	231	Index: -The index value to select the register\r
	232	\r
	233	Returns: \r
	234	Return the read data \r
	235	--*/\r
	236	VOID\r
	237	IA32API\r
	238	EfiWriteMsr (\r
	239	IN UINT32 Index,\r
	240	IN UINT64 Value\r
e00e1d46	241	);\r
3eb9473e	242	\r
	243	/*++ \r
	244	Routine Description: \r
	245	Write Cpu MSR\r
	246	Arguments: \r
	247	Index: -The index value to select the register\r
	248	Value: -The value to write to the selected register \r
	249	Returns: \r
	250	None \r
	251	--*/\r
	252	UINT64\r
	253	IA32API\r
	254	EfiReadTsc (\r
	255	VOID\r
e00e1d46	256	);\r
3eb9473e	257	\r
	258	/*++ \r
	259	Routine Description: \r
	260	Read Time stamp\r
	261	Arguments: \r
	262	None \r
	263	Returns: \r
	264	Return the read data \r
	265	--*/\r
	266	VOID\r
	267	IA32API\r
	268	EfiDisableCache (\r
	269	VOID\r
e00e1d46	270	);\r
3eb9473e	271	\r
	272	/*++ \r
	273	Routine Description: \r
	274	Writing back and invalidate the cache,then diable it\r
	275	Arguments: \r
	276	None \r
	277	Returns: \r
	278	None \r
	279	--*/\r
	280	VOID\r
	281	IA32API\r
	282	EfiEnableCache (\r
	283	VOID\r
e00e1d46	284	);\r
3eb9473e	285	\r
	286	/*++ \r
	287	Routine Description: \r
	288	Invalidate the cache,then Enable it\r
	289	Arguments: \r
	290	None \r
	291	Returns: \r
	292	None \r
	293	--*/\r
	294	UINT32\r
	295	IA32API\r
	296	EfiGetEflags (\r
	297	VOID\r
e00e1d46	298	);\r
3eb9473e	299	\r
	300	/*++ \r
	301	Routine Description: \r
	302	Get Eflags\r
	303	Arguments: \r
	304	None \r
	305	Returns: \r
	306	Return the Eflags value \r
	307	--*/\r
	308	VOID\r
	309	IA32API\r
	310	EfiDisableInterrupts (\r
	311	VOID\r
e00e1d46	312	);\r
3eb9473e	313	\r
	314	/*++ \r
	315	Routine Description: \r
	316	Disable Interrupts\r
	317	Arguments: \r
	318	None \r
	319	Returns: \r
	320	None\r
	321	--*/\r
	322	VOID\r
	323	IA32API\r
	324	EfiEnableInterrupts (\r
	325	VOID\r
e00e1d46	326	);\r
3eb9473e	327	\r
	328	/*++ \r
	329	Routine Description: \r
	330	Enable Interrupts\r
	331	Arguments: \r
	332	None \r
	333	Returns: \r
	334	None \r
	335	--*/\r
	336	\r
	337	\r
	338	VOID\r
	339	IA32API\r
	340	EfiCpuVersion (\r
	341	IN UINT16 *FamilyId, OPTIONAL\r
	342	IN UINT8 *Model, OPTIONAL\r
	343	IN UINT8 *SteppingId, OPTIONAL\r
	344	IN UINT8 *Processor OPTIONAL\r
	345	)\r
	346	/*++\r
	347	\r
	348	Routine Description:\r
	349	Extract CPU detail version infomation\r
	350	\r
	351	Arguments:\r
	352	FamilyId - FamilyId, including ExtendedFamilyId\r
	353	Model - Model, including ExtendedModel\r
	354	SteppingId - SteppingId\r
	355	Processor - Processor\r
	356	\r
	357	--*/\r
	358	;\r
	359	\r
	360	#endif\r