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1 | /*++\r |
| 2 | \r |
| 3 | Copyright (c) 2005, Intel Corporation\r |
| 4 | All rights reserved. This program and the accompanying materials\r |
| 5 | are licensed and made available under the terms and conditions of the BSD License\r |
| 6 | which accompanies this distribution. The full text of the license may be found at\r |
| 7 | http://opensource.org/licenses/bsd-license.php\r |
| 8 | \r |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 11 | \r |
| 12 | \r |
| 13 | Module Name:\r |
| 14 | \r |
| 15 | CpuSaveState.h\r |
| 16 | \r |
| 17 | Abstract:\r |
| 18 | \r |
| 19 | Define data structures used by EFI_SMM_CPU_SAVE_STATE protocol.\r |
| 20 | \r |
| 21 | Revision History\r |
| 22 | \r |
| 23 | ++*/\r |
| 24 | \r |
| 25 | #ifndef _CPUSAVESTATE_H_\r |
| 26 | #define _CPUSAVESTATE_H_\r |
| 27 | \r |
| 28 | typedef unsigned char ASM_UINT8;\r |
| 29 | typedef ASM_UINT8 ASM_BOOL;\r |
| 30 | typedef unsigned short ASM_UINT16;\r |
| 31 | typedef unsigned long ASM_UINT32;\r |
| 32 | \r |
| 33 | #ifdef _H2INC\r |
| 34 | typedef double ASM_UINT64;\r |
| 35 | #else\r |
| 6a7c450c |
36 | typedef UINT64 ASM_UINT64;\r |
| 3eb9473e |
37 | #endif\r |
| 38 | \r |
| 6a7c450c |
39 | #ifndef __GNUC__\r |
| 3eb9473e |
40 | #pragma pack (push)\r |
| 41 | #pragma pack (1)\r |
| 6a7c450c |
42 | #endif\r |
| 3eb9473e |
43 | \r |
| 44 | typedef struct _EFI_SMM_CPU_STATE32 {\r |
| 45 | ASM_UINT8 Reserved1[0xf8]; // fe00h\r |
| 46 | ASM_UINT32 SMBASE; // fef8h\r |
| 47 | ASM_UINT32 SMMRevId; // fefch\r |
| 48 | ASM_UINT16 IORestart; // ff00h\r |
| 49 | ASM_UINT16 AutoHALTRestart; // ff02h\r |
| 50 | ASM_UINT32 IEDBASE; // ff04h\r |
| 51 | ASM_UINT8 Reserved2[0x98]; // ff08h\r |
| 52 | ASM_UINT32 IOMemAddr; // ffa0h\r |
| 53 | ASM_UINT32 IOMisc; // ffa4h\r |
| 54 | ASM_UINT32 _ES;\r |
| 55 | ASM_UINT32 _CS;\r |
| 56 | ASM_UINT32 _SS;\r |
| 57 | ASM_UINT32 _DS;\r |
| 58 | ASM_UINT32 _FS;\r |
| 59 | ASM_UINT32 _GS;\r |
| 60 | ASM_UINT32 _LDTBase;\r |
| 61 | ASM_UINT32 _TR;\r |
| 62 | ASM_UINT32 _DR7;\r |
| 63 | ASM_UINT32 _DR6;\r |
| 64 | ASM_UINT32 _EAX;\r |
| 65 | ASM_UINT32 _ECX;\r |
| 66 | ASM_UINT32 _EDX;\r |
| 67 | ASM_UINT32 _EBX;\r |
| 68 | ASM_UINT32 _ESP;\r |
| 69 | ASM_UINT32 _EBP;\r |
| 70 | ASM_UINT32 _ESI;\r |
| 71 | ASM_UINT32 _EDI;\r |
| 72 | ASM_UINT32 _EIP;\r |
| 73 | ASM_UINT32 _EFLAGS;\r |
| 74 | ASM_UINT32 _CR3;\r |
| 75 | ASM_UINT32 _CR0;\r |
| 76 | } EFI_SMM_CPU_STATE32;\r |
| 77 | \r |
| 78 | typedef struct _EFI_SMM_CPU_STATE64 {\r |
| 79 | ASM_UINT8 Reserved1[0x1d0]; // fc00h\r |
| 80 | ASM_UINT32 GdtBaseHiDword; // fdd0h\r |
| 81 | ASM_UINT32 LdtBaseHiDword; // fdd4h\r |
| 82 | ASM_UINT32 IdtBaseHiDword; // fdd8h\r |
| 83 | ASM_UINT8 Reserved2[0xc]; // fddch\r |
| 84 | ASM_UINT64 IO_EIP; // fde8h\r |
| 85 | ASM_UINT8 Reserved3[0x50]; // fdf0h\r |
| 86 | ASM_UINT32 _CR4; // fe40h\r |
| 87 | ASM_UINT8 Reserved4[0x48]; // fe44h\r |
| 88 | ASM_UINT32 GdtBaseLoDword; // fe8ch\r |
| 89 | ASM_UINT32 GdtLimit; // fe90h\r |
| 90 | ASM_UINT32 IdtBaseLoDword; // fe94h\r |
| 91 | ASM_UINT32 IdtLimit; // fe98h\r |
| 92 | ASM_UINT32 LdtBaseLoDword; // fe9ch\r |
| 93 | ASM_UINT32 LdtLimit; // fea0h\r |
| 94 | ASM_UINT32 LdtInfo; // fea4h\r |
| 95 | ASM_UINT8 Reserved5[0x50]; // fea8h\r |
| 96 | ASM_UINT32 SMBASE; // fef8h\r |
| 97 | ASM_UINT32 SMMRevId; // fefch\r |
| 98 | ASM_UINT16 IORestart; // ff00h\r |
| 99 | ASM_UINT16 AutoHALTRestart; // ff02h\r |
| 100 | ASM_UINT32 IEDBASE; // ff04h\r |
| 101 | ASM_UINT8 Reserved6[0x14]; // ff08h\r |
| 102 | ASM_UINT64 _R15; // ff1ch\r |
| 103 | ASM_UINT64 _R14;\r |
| 104 | ASM_UINT64 _R13;\r |
| 105 | ASM_UINT64 _R12;\r |
| 106 | ASM_UINT64 _R11;\r |
| 107 | ASM_UINT64 _R10;\r |
| 108 | ASM_UINT64 _R9;\r |
| 109 | ASM_UINT64 _R8;\r |
| 110 | ASM_UINT64 _RAX; // ff5ch\r |
| 111 | ASM_UINT64 _RCX;\r |
| 112 | ASM_UINT64 _RDX;\r |
| 113 | ASM_UINT64 _RBX;\r |
| 114 | ASM_UINT64 _RSP;\r |
| 115 | ASM_UINT64 _RBP;\r |
| 116 | ASM_UINT64 _RSI;\r |
| 117 | ASM_UINT64 _RDI;\r |
| 118 | ASM_UINT64 IOMemAddr; // ff9ch\r |
| 119 | ASM_UINT32 IOMisc; // ffa4h\r |
| 120 | ASM_UINT32 _ES; // ffa8h\r |
| 121 | ASM_UINT32 _CS;\r |
| 122 | ASM_UINT32 _SS;\r |
| 123 | ASM_UINT32 _DS;\r |
| 124 | ASM_UINT32 _FS;\r |
| 125 | ASM_UINT32 _GS;\r |
| 126 | ASM_UINT32 _LDTR; // ffc0h\r |
| 127 | ASM_UINT32 _TR;\r |
| 128 | ASM_UINT64 _DR7; // ffc8h\r |
| 129 | ASM_UINT64 _DR6;\r |
| 130 | ASM_UINT64 _RIP; // ffd8h\r |
| 131 | ASM_UINT64 IA32_EFER; // ffe0h\r |
| 132 | ASM_UINT64 _RFLAGS; // ffe8h\r |
| 133 | ASM_UINT64 _CR3; // fff0h\r |
| 134 | ASM_UINT64 _CR0; // fff8h\r |
| 135 | } EFI_SMM_CPU_STATE64;\r |
| 136 | \r |
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137 | #ifndef __GNUC__\r |
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138 | #pragma warning (push)\r |
| 139 | #pragma warning (disable: 4201)\r |
| 6a7c450c |
140 | #endif\r |
| 141 | \r |
| 142 | \r |
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143 | typedef union _EFI_SMM_CPU_STATE {\r |
| 144 | struct {\r |
| 145 | ASM_UINT8 Reserved[0x200];\r |
| 146 | EFI_SMM_CPU_STATE32 x86;\r |
| 147 | };\r |
| 148 | EFI_SMM_CPU_STATE64 x64;\r |
| 149 | } EFI_SMM_CPU_STATE;\r |
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150 | \r |
| 6a7c450c |
151 | #ifndef __GNUC__\r |
| 152 | #pragma warning (pop)\r |
| 3eb9473e |
153 | #pragma pack (pop)\r |
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154 | #endif\r |
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155 | \r |
| 156 | #define EFI_SMM_MIN_REV_ID_x64 0x30006\r |
| 157 | \r |
| 158 | #endif\r |
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