projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3eb9473e | 1 | /*++\r |
| 2 | \r | |
| f57387d5 HT |
3 | Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>\r |
| 4 | This program and the accompanying materials \r | |
| 3eb9473e | 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r | |
| 7 | http://opensource.org/licenses/bsd-license.php \r | |
| 8 | \r | |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 11 | \r | |
| 12 | Module Name:\r | |
| 13 | \r | |
| 14 | PalApi.h\r | |
| 15 | \r | |
| 16 | Abstract:\r | |
| 17 | \r | |
| 18 | Main PAL API's defined in PAL specification. \r | |
| 19 | \r | |
| 20 | \r | |
| 21 | Revision History:\r | |
| 22 | \r | |
| 23 | --*/\r | |
| 24 | \r | |
| 25 | #ifndef _PALPROC_H\r | |
| 26 | #define _PALPROC_H\r | |
| 27 | \r | |
| 28 | #include "Tiano.h"\r | |
| 29 | \r | |
| 30 | #define PAL_CACHE_FLUSH 0x0001\r | |
| 31 | #define PAL_CACHE_INFO 0x0002\r | |
| 32 | #define PAL_CACHE_INIT 0x0003\r | |
| 33 | #define PAL_CACHE_SUMMARY 0x0004\r | |
| 34 | #define PAL_MEM_ATTRIB 0x0005\r | |
| 35 | #define PAL_PTCE_INFO 0x0006\r | |
| 36 | #define PAL_VM_INFO 0x0007\r | |
| 37 | #define PAL_VM_SUMMARY 0x0008\r | |
| 38 | #define PAL_BUS_GET_FEATURES 0x0009\r | |
| 39 | #define PAL_BUS_SET_FEATURES 0x000a\r | |
| 40 | #define PAL_DEBUG_INFO 0x000b\r | |
| 41 | #define PAL_FIXED_ADDR 0x000c\r | |
| 42 | #define PAL_FREQ_BASE 0x000d\r | |
| 43 | #define PAL_FREQ_RATIOS 0x000e\r | |
| 44 | #define PAL_PERF_MON_INFO 0x000f\r | |
| 45 | #define PAL_PLATFORM_ADDR 0x0010\r | |
| 46 | #define PAL_PROC_GET_FEATURES 0x0011\r | |
| 47 | #define PAL_PROC_SET_FEATURES 0x0012\r | |
| 48 | #define PAL_RSE_INFO 0x0013\r | |
| 49 | #define PAL_VERSION 0x0014\r | |
| 50 | \r | |
| 51 | #define PAL_MC_CLEAR_LOG 0x0015\r | |
| 52 | #define PAL_MC_DRAIN 0x0016\r | |
| 53 | #define PAL_MC_EXPECTED 0x0017\r | |
| 54 | #define PAL_MC_DYNAMIC_STATE 0x0018\r | |
| 55 | #define PAL_MC_ERROR_INFO 0x0019\r | |
| 56 | #define PAL_MC_RESUME 0x001a\r | |
| 57 | #define PAL_MC_REGISTER_MEM 0x001b\r | |
| 58 | #define PAL_HALT 0x001c\r | |
| 59 | #define PAL_HALT_LIGHT 0x001d\r | |
| 60 | #define PAL_COPY_INFO 0x001e\r | |
| 61 | #define PAL_SHUTDOWN 0x002c\r | |
| 62 | #define PAL_AUTH 0x0209\r | |
| 63 | #define PAL_SINGL_DISPERSAL 0x0226 // dec. 550\r | |
| 64 | #define PAL_HALT_INFO 0x0101\r | |
| 65 | #define PAL_CACHE_LINE_INIT 0x001f\r | |
| 66 | #define PAL_PMI_ENTRYPOINT 0x0020\r | |
| 67 | #define PAL_ENTER_IA_32_ENV 0x0021\r | |
| 68 | #define PAL_VM_PAGE_SIZE 0x0022\r | |
| 69 | #define PAL_MEM_FOR_TEST 0x0025\r | |
| 70 | #define PAL_CACHE_PROT_INFO 0x0026\r | |
| 71 | \r | |
| 72 | #define PAL_COPY_PAL 0x0100\r | |
| 73 | #define PAL_CACHE_READ 0x0103\r | |
| 74 | #define PAL_CACHE_WRITE 0x0104\r | |
| 75 | #define PAL_TEST_PROC 0x0102\r | |
| 76 | \r | |
| 77 | #define PAL_DEBUG_FEATURE 0x0063 // vp1\r | |
| 78 | typedef UINT64 EFI_PAL_STATUS;\r | |
| 79 | \r | |
| 80 | //\r | |
| 81 | // Return values from PAL\r | |
| 82 | //\r | |
| 83 | typedef struct {\r | |
| 84 | EFI_PAL_STATUS Status; // register r8\r | |
| 85 | UINT64 r9;\r | |
| 86 | UINT64 r10;\r | |
| 87 | UINT64 r11;\r | |
| 88 | } PAL_RETURN_REGS;\r | |
| 89 | \r | |
| 90 | //\r | |
| 91 | // PAL equates for other parameters.\r | |
| 92 | //\r | |
| 93 | #define PAL_SUCCESS 0x0\r | |
| 94 | #define PAL_CALL_ERROR 0xfffffffffffffffd\r | |
| 95 | #define PAL_CALL_UNIMPLEMENTED 0xffffffffffffffff\r | |
| 96 | #define PAL_CACHE_TYPE_I 0x1\r | |
| 97 | #define PAL_CACHE_TYPE_D 0x2\r | |
| 98 | #define PAL_CACHE_TYPE_I_AND_D 0x3\r | |
| 99 | #define PAL_CACHE_NO_INT 0x0\r | |
| 100 | #define PAL_CACHE_INT 0x2\r | |
| 101 | //\r | |
| 102 | // #define PAL_CACHE_PLAT_ACK 0x4\r | |
| 103 | //\r | |
| 104 | #define PAL_CACHE_NO_PLAT_ACK 0x0\r | |
| 105 | #define PAL_CACHE_INVALIDATE 0x1\r | |
| 106 | #define PAL_CACHE_NO_INVALIDATE 0x0\r | |
| 107 | #define PAL_CACHE_ALL_LEVELS - 0x1\r | |
| 108 | \r | |
| 109 | #define PAL_FEATURE_ENABLE 0x1\r | |
| 110 | #define PAL_ENABLE_BERR_BIT 63\r | |
| 111 | #define PAL_ENABLE_MCA_BINIT_BIT 61\r | |
| 112 | #define PAL_ENABLE_CMCI_MCA_BIT 60\r | |
| 113 | #define PAL_CACHE_DISABLE_BIT 59\r | |
| 114 | #define PAL_DISABLE_COHERENCY_BIT 58\r | |
| 115 | \r | |
| 116 | #define PAL_DIS_BUS_DATA_ERR_CHECK_BIT 63\r | |
| 117 | #define PAL_DIS_BUS_ADDR_ERR_CHECK_BIT 61\r | |
| 118 | #define PAL_DIS_BUS_INIT_EVENT_SIGNAL_BIT 60\r | |
| 119 | #define PAL_DIS_BUS_REQ_ERR_SIGNAL_BIT 58\r | |
| 120 | #define PAL_DIS_BUS_REQ_INT_ERR_SIGNAL_BIT 57\r | |
| 121 | #define PAL_DIS_BUS_REQ_ERR_CHECK_BIT 56\r | |
| 122 | #define PAL_DIS_BUS_RESP_ERR_CHECK_BIT 55\r | |
| 123 | \r | |
| 124 | #define PAL_COPY_BSP_TOKEN 0x0\r | |
| 125 | #define PAL_COPY_AP_TOKEN 0x1\r | |
| 126 | \r | |
| 127 | #define PAL_CODE_TOKEN 0x0\r | |
| 128 | #define PAL_IA32EMU_CODE_TOKEN 0x1\r | |
| 129 | \r | |
| 130 | #define PAL_INTERRUPT_BLOCK_TOKEN 0x0\r | |
| 131 | #define PAL_IO_BLOCK_TOKEN 0x1\r | |
| 132 | \r | |
| 133 | #endif\r |