[mirror_edk2.git] / EdkCompatibilityPkg / Foundation / Include / Ipf / SalApi.h

/*++\r
\r
Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials                          \r
are licensed and made available under the terms and conditions of the BSD License         \r
which accompanies this distribution.  The full text of the license may be found at        \r
http://opensource.org/licenses/bsd-license.php                                            \r
                                                                                          \r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
Module Name:\r
\r
  SalApi.h\r
\r
Abstract:\r
\r
  Main SAL API's defined in SAL 3.0 specification. \r
\r
\r
Revision History:\r
\r
--*/\r
\r
#ifndef _SAL_API_H_\r
#define _SAL_API_H_\r
\r
typedef UINTN EFI_SAL_STATUS;\r
\r
//\r
// EFI_SAL_STATUS defines\r
//\r
#define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)\r
#define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)\r
#define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)\r
#define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)\r
#define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)\r
#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
#define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)\r
#define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)\r
\r
//\r
//  Delivery Mode of IPF CPU.\r
//\r
typedef enum {\r
  INT,\r
  MPreserved1,\r
  PMI,\r
  MPreserved2,\r
  NMI,\r
  INIT,\r
  MPreserved3,\r
  ExtINT\r
} EFI_DELIVERY_MODE;\r
\r
//\r
//  Return values from SAL\r
//\r
typedef struct {\r
  EFI_SAL_STATUS  Status; // register r8\r
  UINTN           r9;\r
  UINTN           r10;\r
  UINTN           r11;\r
} SAL_RETURN_REGS;\r
\r
typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
  (\r
    IN UINT64 FunctionId,\r
    IN UINT64 Arg2,\r
    IN UINT64 Arg3,\r
    IN UINT64 Arg4,\r
    IN UINT64 Arg5,\r
    IN UINT64 Arg6,\r
    IN UINT64 Arg7,\r
    IN UINT64 Arg8\r
  );\r
\r
//\r
// SAL Procedure FunctionId definition\r
//\r
#define EFI_SAL_SET_VECTORS             0x01000000\r
#define EFI_SAL_GET_STATE_INFO          0x01000001\r
#define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002\r
#define EFI_SAL_CLEAR_STATE_INFO        0x01000003\r
#define EFI_SAL_MC_RENDEZ               0x01000004\r
#define EFI_SAL_MC_SET_PARAMS           0x01000005\r
#define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006\r
#define EFI_SAL_CACHE_FLUSH             0x01000008\r
#define EFI_SAL_CACHE_INIT              0x01000009\r
#define EFI_SAL_PCI_CONFIG_READ         0x01000010\r
#define EFI_SAL_PCI_CONFIG_WRITE        0x01000011\r
#define EFI_SAL_FREQ_BASE               0x01000012\r
#define EFI_SAL_UPDATE_PAL              0x01000020\r
\r
#define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff\r
#define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021\r
\r
//\r
// SAL Procedure parameter definitions\r
// Not much point in using typedefs or enums because all params\r
// are UINT64 and the entry point is common\r
//\r
// EFI_SAL_SET_VECTORS\r
//\r
#define EFI_SAL_SET_MCA_VECTOR          0x0\r
#define EFI_SAL_SET_INIT_VECTOR         0x1\r
#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2\r
\r
typedef struct {\r
  UINT64  Length : 32;\r
  UINT64  ChecksumValid : 1;\r
  UINT64  Reserved1 : 7;\r
  UINT64  ByteChecksum : 8;\r
  UINT64  Reserved2 : 16;\r
} SAL_SET_VECTORS_CS_N;\r
\r
//\r
// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
// EFI_SAL_CLEAR_STATE_INFO\r
//\r
#define EFI_SAL_MCA_STATE_INFO  0x0\r
#define EFI_SAL_INIT_STATE_INFO 0x1\r
#define EFI_SAL_CMC_STATE_INFO  0x2\r
#define EFI_SAL_CP_STATE_INFO   0x3\r
\r
//\r
// EFI_SAL_MC_SET_PARAMS\r
//\r
#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
#define EFI_SAL_MC_SET_CPE_PARAM    0x3\r
\r
#define EFI_SAL_MC_SET_INTR_PARAM   0x1\r
#define EFI_SAL_MC_SET_MEM_PARAM    0x2\r
\r
//\r
// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
//\r
#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
\r
//\r
// EFI_SAL_CACHE_FLUSH\r
//\r
#define EFI_SAL_FLUSH_I_CACHE       0x01\r
#define EFI_SAL_FLUSH_D_CACHE       0x02\r
#define EFI_SAL_FLUSH_BOTH_CACHE    0x03\r
#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
\r
//\r
// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
//\r
#define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1\r
#define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2\r
#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
\r
typedef struct {\r
  UINT64  Register : 8;\r
  UINT64  Function : 3;\r
  UINT64  Device : 5;\r
  UINT64  Bus : 8;\r
  UINT64  Segment : 8;\r
  UINT64  Reserved : 32;\r
} SAL_PCI_ADDRESS;\r
\r
//\r
// EFI_SAL_FREQ_BASE\r
//\r
#define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0\r
#define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1\r
#define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2\r
\r
//\r
// EFI_SAL_UPDATE_PAL\r
//\r
#define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)\r
#define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)\r
#define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)\r
#define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)\r
#define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)\r
#define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)\r
#define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)\r
#define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)\r
\r
typedef struct {\r
  UINT32  Size;\r
  UINT32  MmddyyyyDate;\r
  UINT16  Version;\r
  UINT8   Type;\r
  UINT8   Reserved[5];\r
  UINT64  FwVendorId;\r
} SAL_UPDATE_PAL_DATA_BLOCK;\r
\r
typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
  struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
  struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;\r
  UINT8                             StoreChecksum;\r
  UINT8                             Reserved[15];\r
} SAL_UPDATE_PAL_INFO_BLOCK;\r
\r
//\r
// SAL System Table Definitions\r
//\r
#pragma pack(1)\r
typedef struct {\r
  UINT32  Signature;\r
  UINT32  Length;\r
  UINT16  SalRevision;\r
  UINT16  EntryCount;\r
  UINT8   CheckSum;\r
  UINT8   Reserved[7];\r
  UINT16  SalAVersion;\r
  UINT16  SalBVersion;\r
  UINT8   OemId[32];\r
  UINT8   ProductId[32];\r
  UINT8   Reserved2[8];\r
} SAL_SYSTEM_TABLE_HEADER;\r
#pragma pack()\r
\r
#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
#define EFI_SAL_REVISION            0x0300\r
//\r
// SAL System Types\r
//\r
#define EFI_SAL_ST_ENTRY_POINT        0\r
#define EFI_SAL_ST_MEMORY_DESCRIPTOR  1\r
#define EFI_SAL_ST_PLATFORM_FEATURES  2\r
#define EFI_SAL_ST_TR_USAGE           3\r
#define EFI_SAL_ST_PTC                4\r
#define EFI_SAL_ST_AP_WAKEUP          5\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8   Type; //  Type == 0\r
  UINT8   Reserved[7];\r
  UINT64  PalProcEntry;\r
  UINT64  SalProcEntry;\r
  UINT64  SalGlobalDataPointer;\r
  UINT64  Reserved2[2];\r
} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
\r
//\r
// Not needed for Itanium-based OS boot\r
//\r
typedef struct {\r
  UINT8   Type; //  Type == 1\r
  UINT8   NeedVirtualRegistration;\r
  UINT8   MemoryAttributes;\r
  UINT8   PageAccessRights;\r
  UINT8   SupportedAttributes;\r
  UINT8   Reserved;\r
  UINT8   MemoryType;\r
  UINT8   MemoryUsage;\r
  UINT64  PhysicalMemoryAddress;\r
  UINT32  Length;\r
  UINT32  Reserved1;\r
  UINT64  OemReserved;\r
} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;\r
\r
#pragma pack()\r
//\r
// Memory Attributes\r
//\r
#define SAL_MDT_ATTRIB_WB 0x00\r
//\r
// #define SAL_MDT_ATTRIB_UC   0x02\r
//\r
#define SAL_MDT_ATTRIB_UC   0x04\r
#define SAL_MDT_ATTRIB_UCE  0x05\r
#define SAL_MDT_ATTRIB_WC   0x06\r
\r
//\r
// Supported memory Attributes\r
//\r
#define SAL_MDT_SUPPORT_WB  0x1\r
#define SAL_MDT_SUPPORT_UC  0x2\r
#define SAL_MDT_SUPPORT_UCE 0x4\r
#define SAL_MDT_SUPPORT_WC  0x8\r
\r
//\r
// Virtual address registration\r
//\r
#define SAL_MDT_NO_VA   0x00\r
#define SAL_MDT_NEED_VA 0x01\r
//\r
// MemoryType info\r
//\r
#define SAL_REGULAR_MEMORY  0x0000\r
#define SAL_MMIO_MAPPING    0x0001\r
#define SAL_SAPIC_IPI_BLOCK 0x0002\r
#define SAL_IO_PORT_MAPPING 0x0003\r
#define SAL_FIRMWARE_MEMORY 0x0004\r
#define SAL_BLACK_HOLE      0x000A\r
//\r
// Memory Usage info\r
//\r
#define SAL_MDT_USAGE_UNSPECIFIED 0x00\r
#define SAL_PAL_CODE              0x01\r
#define SAL_BOOTSERVICE_CODE      0x02\r
#define SAL_BOOTSERVICE_DATA      0x03\r
#define SAL_RUNTIMESERVICE_CODE   0x04\r
#define SAL_RUNTIMESERVICE_DATA   0x05\r
#define SAL_IA32_OPTIONROM        0x06\r
#define SAL_IA32_SYSTEMROM        0x07\r
#define SAL_PMI_CODE              0x0a\r
#define SAL_PMI_DATA              0x0b\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8 Type;                     // Type == 2\r
  UINT8 PlatformFeatures;\r
  UINT8 Reserved[14];\r
} SAL_ST_PLATFORM_FEATURES;\r
#pragma pack()\r
\r
#define SAL_PLAT_FEAT_BUS_LOCK      0x01\r
#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8   Type;                   // Type == 3\r
  UINT8   TRType;\r
  UINT8   TRNumber;\r
  UINT8   Reserved[5];\r
  UINT64  VirtualAddress;\r
  UINT64  EncodedPageSize;\r
  UINT64  Reserved1;\r
} SAL_ST_TR_DECRIPTOR;\r
#pragma pack()\r
\r
#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
#define EFI_SAL_ST_TR_USAGE_DATA        01\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT64  NumberOfProcessors;\r
  UINT64  LocalIDRegister;\r
} SAL_COHERENCE_DOMAIN_INFO;\r
#pragma pack()\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8                     Type; // Type == 4\r
  UINT8                     Reserved[3];\r
  UINT32                    NumberOfDomains;\r
  SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
#pragma pack()\r
\r
#pragma pack(1)\r
typedef struct {\r
  UINT8   Type;                   // Type == 5\r
  UINT8   WakeUpType;\r
  UINT8   Reserved[6];\r
  UINT64  ExternalInterruptVector;\r
} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
#pragma pack()\r
//\r
// FIT Entry\r
//\r
#define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24\r
#define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32\r
#define EFI_SAL_FIT_PALB_TYPE   01\r
\r
typedef struct {\r
  UINT64  Address;\r
  UINT8   Size[3];\r
  UINT8   Reserved;\r
  UINT16  Revision;\r
  UINT8   Type : 7;\r
  UINT8   CheckSumValid : 1;\r
  UINT8   CheckSum;\r
} EFI_SAL_FIT_ENTRY;\r
\r
//\r
//  SAL Common Record Header\r
//\r
typedef struct {\r
  UINT16  Length;\r
  UINT8   Data[1024];\r
} SAL_OEM_DATA;\r
\r
typedef struct {\r
  UINT8 Seconds;\r
  UINT8 Minutes;\r
  UINT8 Hours;\r
  UINT8 Reserved;\r
  UINT8 Day;\r
  UINT8 Month;\r
  UINT8 Year;\r
  UINT8 Century;\r
} SAL_TIME_STAMP;\r
\r
typedef struct {\r
  UINT64          RecordId;\r
  UINT16          Revision;\r
  UINT8           ErrorSeverity;\r
  UINT8           ValidationBits;\r
  UINT32          RecordLength;\r
  SAL_TIME_STAMP  TimeStamp;\r
  UINT8           OemPlatformId[16];\r
} SAL_RECORD_HEADER;\r
\r
typedef struct {\r
  EFI_GUID  Guid;\r
  UINT16    Revision;\r
  UINT8     ErrorRecoveryInfo;\r
  UINT8     Reserved;\r
  UINT32    SectionLength;\r
} SAL_SEC_HEADER;\r
\r
//\r
// SAL Processor Record\r
//\r
#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
  }\r
\r
#define CHECK_INFO_VALID_BIT_MASK   0x1\r
#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
#define TARGER_ID_VALID_BIT_MASK    0x8\r
#define PRECISE_IP_VALID_BIT_MASK   0x10\r
\r
typedef struct {\r
  UINT64  InfoValid : 1;\r
  UINT64  ReqValid : 1;\r
  UINT64  RespValid : 1;\r
  UINT64  TargetValid : 1;\r
  UINT64  IpValid : 1;\r
  UINT64  Reserved : 59;\r
  UINT64  Info;\r
  UINT64  Req;\r
  UINT64  Resp;\r
  UINT64  Target;\r
  UINT64  Ip;\r
} MOD_ERROR_INFO;\r
\r
typedef struct {\r
  UINT8 CpuidInfo[40];\r
  UINT8 Reserved;\r
} CPUID_INFO;\r
\r
typedef struct {\r
  UINT64  FrLow;\r
  UINT64  FrHigh;\r
} FR_STRUCT;\r
\r
#define MIN_STATE_VALID_BIT_MASK  0x1\r
#define BR_VALID_BIT_MASK         0x2\r
#define CR_VALID_BIT_MASK         0x4\r
#define AR_VALID_BIT_MASK         0x8\r
#define RR_VALID_BIT_MASK         0x10\r
#define FR_VALID_BIT_MASK         0x20\r
\r
typedef struct {\r
  UINT64    ValidFieldBits;\r
  UINT8     MinStateInfo[1024];\r
  UINT64    Br[8];\r
  UINT64    Cr[128];\r
  UINT64    Ar[128];\r
  UINT64    Rr[8];\r
  FR_STRUCT Fr[128];\r
} PSI_STATIC_STRUCT;\r
\r
#define PROC_ERROR_MAP_VALID_BIT_MASK       0x1\r
#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
#define PROC_CR_LID_VALID_BIT_MASK          0x4\r
#define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8\r
#define CPU_INFO_VALID_BIT_MASK             0x1000000\r
\r
typedef struct {\r
  SAL_SEC_HEADER    SectionHeader;\r
  UINT64            ValidationBits;\r
  UINT64            ProcErrorMap;\r
  UINT64            ProcStateParameter;\r
  UINT64            ProcCrLid;\r
  MOD_ERROR_INFO    CacheError[15];\r
  MOD_ERROR_INFO    TlbError[15];\r
  MOD_ERROR_INFO    BusError[15];\r
  MOD_ERROR_INFO    RegFileCheck[15];\r
  MOD_ERROR_INFO    MsCheck[15];\r
  CPUID_INFO        CpuInfo;\r
  PSI_STATIC_STRUCT PsiValidData;\r
} SAL_PROCESSOR_ERROR_RECORD;\r
\r
//\r
//  Sal Platform memory Error Record\r
//\r
#define SAL_MEMORY_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
  }\r
\r
#define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1\r
#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2\r
#define MEMORY_ADDR_BIT_MASK                              0x4\r
#define MEMORY_NODE_VALID_BIT_MASK                        0x8\r
#define MEMORY_CARD_VALID_BIT_MASK                        0x10\r
#define MEMORY_MODULE_VALID_BIT_MASK                      0x20\r
#define MEMORY_BANK_VALID_BIT_MASK                        0x40\r
#define MEMORY_DEVICE_VALID_BIT_MASK                      0x80\r
#define MEMORY_ROW_VALID_BIT_MASK                         0x100\r
#define MEMORY_COLUMN_VALID_BIT_MASK                      0x200\r
#define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400\r
#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800\r
#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000\r
#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000\r
#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000\r
#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000\r
#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT64          MemErrorStatus;\r
  UINT64          MemPhysicalAddress;\r
  UINT64          MemPhysicalAddressMask;\r
  UINT16          MemNode;\r
  UINT16          MemCard;\r
  UINT16          MemModule;\r
  UINT16          MemBank;\r
  UINT16          MemDevice;\r
  UINT16          MemRow;\r
  UINT16          MemColumn;\r
  UINT16          MemBitPosition;\r
  UINT64          ModRequestorId;\r
  UINT64          ModResponderId;\r
  UINT64          ModTargetId;\r
  UINT64          BusSpecificData;\r
  UINT8           MemPlatformOemId[16];\r
} SAL_MEMORY_ERROR_RECORD;\r
\r
//\r
//  PCI BUS Errors\r
//\r
#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
  }\r
\r
#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1\r
#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2\r
#define PCI_BUS_ID_VALID_BIT_MASK               0x4\r
#define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8\r
#define PCI_BUS_DATA_VALID_BIT_MASK             0x10\r
#define PCI_BUS_CMD_VALID_BIT_MASK              0x20\r
#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40\r
#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80\r
#define PCI_BUS_TARGET_VALID_BIT_MASK           0x100\r
#define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200\r
#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400\r
\r
typedef enum {\r
  Unknown,\r
  DataParityError,\r
  SystemError,\r
  MasterAbort,\r
  BusTimeout,\r
  MasterDataParityError,\r
  AddressParityError,\r
  CommandParityError\r
} PCI_BUS_ERROR_TYPE;\r
\r
typedef struct {\r
  UINT8 BusNumber;\r
  UINT8 SegmentNumber;\r
} PCI_BUS_ID;\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT64          PciBusErrorStatus;\r
  UINT16          PciBusErrorType;\r
  PCI_BUS_ID      PciBusId;\r
  UINT32          Reserved;\r
  UINT64          PciBusAddress;\r
  UINT64          PciBusData;\r
  UINT64          PciBusCommand;\r
  UINT64          PciBusRequestorId;\r
  UINT64          PciBusResponderId;\r
  UINT64          PciBusTargetId;\r
  UINT8           PciBusOemId[16];\r
} SAL_PCI_BUS_ERROR_RECORD;\r
\r
//\r
//  PCI Component Errors\r
//\r
#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
  }\r
\r
#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1\r
#define PCI_COMP_INFO_VALID_BIT_MASK            0x2\r
#define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4\r
#define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8\r
#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10\r
#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
\r
typedef struct {\r
  UINT16  VendorId;\r
  UINT16  DeviceId;\r
  UINT8   ClassCode[3];\r
  UINT8   FunctionNumber;\r
  UINT8   DeviceNumber;\r
  UINT8   BusNumber;\r
  UINT8   SegmentNumber;\r
  UINT8   Reserved[5];\r
} PCI_COMP_INFO;\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT64          PciComponentErrorStatus;\r
  PCI_COMP_INFO   PciComponentInfo;\r
  UINT32          PciComponentMemNum;\r
  UINT32          PciComponentIoNum;\r
  UINT8           PciBusOemId[16];\r
} SAL_PCI_COMPONENT_ERROR_RECORD;\r
\r
//\r
//  Sal Device Errors Info.\r
//\r
#define SAL_DEVICE_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
  }\r
\r
#define SEL_RECORD_ID_VALID_BIT_MASK      0x1;\r
#define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;\r
#define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;\r
#define SEL_EVM_REV_VALID_BIT_MASK        0x8;\r
#define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;\r
#define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;\r
#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
#define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;\r
#define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;\r
#define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT16          SelRecordId;\r
  UINT8           SelRecordType;\r
  UINT32          TimeStamp;\r
  UINT16          GeneratorId;\r
  UINT8           EvmRevision;\r
  UINT8           SensorType;\r
  UINT8           SensorNum;\r
  UINT8           EventDirType;\r
  UINT8           Data1;\r
  UINT8           Data2;\r
  UINT8           Data3;\r
} SAL_DEVICE_ERROR_RECORD;\r
\r
//\r
//  Sal SMBIOS Device Errors Info.\r
//\r
#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
  }\r
\r
#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1\r
#define SMBIOS_LENGTH_VALID_BIT_MASK      0x2\r
#define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4\r
#define SMBIOS_DATA_VALID_BIT_MASK        0x8\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT8           SmbiosEventType;\r
  UINT8           SmbiosLength;\r
  UINT8           SmbiosBcdTimeStamp[6];\r
} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
\r
//\r
//  Sal Platform Specific Errors Info.\r
//\r
#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
  { \\r
    0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
  }\r
\r
#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1\r
#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2\r
#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4\r
#define PLATFORM_TARGET_VALID_BIT_MASK          0x8\r
#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10\r
#define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20\r
#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
\r
typedef struct {\r
  SAL_SEC_HEADER  SectionHeader;\r
  UINT64          ValidationBits;\r
  UINT64          PlatformErrorStatus;\r
  UINT64          PlatformRequestorId;\r
  UINT64          PlatformResponderId;\r
  UINT64          PlatformTargetId;\r
  UINT64          PlatformBusSpecificData;\r
  UINT8           OemComponentId[16];\r
} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
\r
//\r
// Union of all the possible Sal Record Types\r
//\r
typedef union {\r
  SAL_RECORD_HEADER                   *RecordHeader;\r
  SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;\r
  SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;\r
  SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;\r
  SAL_DEVICE_ERROR_RECORD             *ImpiRecord;\r
  SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;\r
  SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;\r
  SAL_MEMORY_ERROR_RECORD             *MemoryRecord;\r
  UINT8                               *Raw;\r
} SAL_ERROR_RECORDS_POINTERS;\r
\r
#pragma pack()\r
\r
#endif\r
Commit	Line	Data
3eb9473e	1	/*++\r
3eb9473e	2	\r
f57387d5 HT	3	Copyright (c) 2004, Intel Corporation. All rights reserved.<BR>\r
f57387d5 HT	4	This program and the accompanying materials \r
3eb9473e	5	are licensed and made available under the terms and conditions of the BSD License \r
	6	which accompanies this distribution. The full text of the license may be found at \r
	7	http://opensource.org/licenses/bsd-license.php \r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	11	\r
	12	Module Name:\r
	13	\r
	14	SalApi.h\r
	15	\r
	16	Abstract:\r
	17	\r
	18	Main SAL API's defined in SAL 3.0 specification. \r
	19	\r
	20	\r
	21	Revision History:\r
	22	\r
	23	--*/\r
	24	\r
	25	#ifndef _SAL_API_H_\r
	26	#define _SAL_API_H_\r
	27	\r
	28	typedef UINTN EFI_SAL_STATUS;\r
	29	\r
	30	//\r
	31	// EFI_SAL_STATUS defines\r
	32	//\r
	33	#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
	34	#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
	35	#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
	36	#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
	37	#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
	38	#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
	39	#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
	40	#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
	41	\r
	42	//\r
	43	// Delivery Mode of IPF CPU.\r
	44	//\r
	45	typedef enum {\r
	46	INT,\r
	47	MPreserved1,\r
	48	PMI,\r
	49	MPreserved2,\r
	50	NMI,\r
	51	INIT,\r
	52	MPreserved3,\r
	53	ExtINT\r
	54	} EFI_DELIVERY_MODE;\r
	55	\r
	56	//\r
	57	// Return values from SAL\r
	58	//\r
	59	typedef struct {\r
	60	EFI_SAL_STATUS Status; // register r8\r
	61	UINTN r9;\r
	62	UINTN r10;\r
	63	UINTN r11;\r
	64	} SAL_RETURN_REGS;\r
	65	\r
	66	typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
	67	(\r
	68	IN UINT64 FunctionId,\r
69	IN UINT64 Arg2,\r
70	IN UINT64 Arg3,\r
71	IN UINT64 Arg4,\r
72	IN UINT64 Arg5,\r
73	IN UINT64 Arg6,\r
74	IN UINT64 Arg7,\r
75	IN UINT64 Arg8\r
76	);\r
77	\r
78	//\r
79	// SAL Procedure FunctionId definition\r
80	//\r
81	#define EFI_SAL_SET_VECTORS 0x01000000\r
82	#define EFI_SAL_GET_STATE_INFO 0x01000001\r
83	#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
84	#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
85	#define EFI_SAL_MC_RENDEZ 0x01000004\r
86	#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
87	#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
88	#define EFI_SAL_CACHE_FLUSH 0x01000008\r
89	#define EFI_SAL_CACHE_INIT 0x01000009\r
90	#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
91	#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
92	#define EFI_SAL_FREQ_BASE 0x01000012\r
93	#define EFI_SAL_UPDATE_PAL 0x01000020\r
94	\r
95	#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
96	#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r
97	\r
98	//\r
99	// SAL Procedure parameter definitions\r
100	// Not much point in using typedefs or enums because all params\r
101	// are UINT64 and the entry point is common\r
102	//\r
103	// EFI_SAL_SET_VECTORS\r
104	//\r
105	#define EFI_SAL_SET_MCA_VECTOR 0x0\r
106	#define EFI_SAL_SET_INIT_VECTOR 0x1\r
107	#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
108	\r
109	typedef struct {\r
110	UINT64 Length : 32;\r
111	UINT64 ChecksumValid : 1;\r
112	UINT64 Reserved1 : 7;\r
113	UINT64 ByteChecksum : 8;\r
114	UINT64 Reserved2 : 16;\r
115	} SAL_SET_VECTORS_CS_N;\r
116	\r
117	//\r
118	// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
119	// EFI_SAL_CLEAR_STATE_INFO\r
120	//\r
121	#define EFI_SAL_MCA_STATE_INFO 0x0\r
122	#define EFI_SAL_INIT_STATE_INFO 0x1\r
123	#define EFI_SAL_CMC_STATE_INFO 0x2\r
124	#define EFI_SAL_CP_STATE_INFO 0x3\r
125	\r
126	//\r
127	// EFI_SAL_MC_SET_PARAMS\r
128	//\r
129	#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
130	#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
131	#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
132	\r
133	#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
134	#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
135	\r
136	//\r
137	// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
138	//\r
139	#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
140	\r
141	//\r
142	// EFI_SAL_CACHE_FLUSH\r
143	//\r
144	#define EFI_SAL_FLUSH_I_CACHE 0x01\r
145	#define EFI_SAL_FLUSH_D_CACHE 0x02\r
146	#define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r
147	#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
148	\r
149	//\r
150	// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
151	//\r
152	#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
153	#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
154	#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
155	\r
156	typedef struct {\r
157	UINT64 Register : 8;\r
158	UINT64 Function : 3;\r
159	UINT64 Device : 5;\r
160	UINT64 Bus : 8;\r
161	UINT64 Segment : 8;\r
162	UINT64 Reserved : 32;\r
163	} SAL_PCI_ADDRESS;\r
164	\r
165	//\r
166	// EFI_SAL_FREQ_BASE\r
167	//\r
168	#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
169	#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
170	#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
171	\r
172	//\r
173	// EFI_SAL_UPDATE_PAL\r
174	//\r
175	#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
176	#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
177	#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r
178	#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r
179	#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r
180	#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
181	#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
182	#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
183	\r
184	typedef struct {\r
185	UINT32 Size;\r
186	UINT32 MmddyyyyDate;\r
187	UINT16 Version;\r
188	UINT8 Type;\r
189	UINT8 Reserved[5];\r
190	UINT64 FwVendorId;\r
191	} SAL_UPDATE_PAL_DATA_BLOCK;\r
192	\r
193	typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
194	struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
195	struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
196	UINT8 StoreChecksum;\r
197	UINT8 Reserved[15];\r
198	} SAL_UPDATE_PAL_INFO_BLOCK;\r
199	\r
200	//\r
201	// SAL System Table Definitions\r
202	//\r
203	#pragma pack(1)\r
204	typedef struct {\r
205	UINT32 Signature;\r
206	UINT32 Length;\r
207	UINT16 SalRevision;\r
208	UINT16 EntryCount;\r
209	UINT8 CheckSum;\r
210	UINT8 Reserved[7];\r
211	UINT16 SalAVersion;\r
212	UINT16 SalBVersion;\r
213	UINT8 OemId[32];\r
214	UINT8 ProductId[32];\r
215	UINT8 Reserved2[8];\r
216	} SAL_SYSTEM_TABLE_HEADER;\r
217	#pragma pack()\r
218	\r
219	#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
220	#define EFI_SAL_REVISION 0x0300\r
221	//\r
222	// SAL System Types\r
223	//\r
224	#define EFI_SAL_ST_ENTRY_POINT 0\r
225	#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r
226	#define EFI_SAL_ST_PLATFORM_FEATURES 2\r
227	#define EFI_SAL_ST_TR_USAGE 3\r
228	#define EFI_SAL_ST_PTC 4\r
229	#define EFI_SAL_ST_AP_WAKEUP 5\r
230	\r
231	#pragma pack(1)\r
232	typedef struct {\r
233	UINT8 Type; // Type == 0\r
234	UINT8 Reserved[7];\r
235	UINT64 PalProcEntry;\r
236	UINT64 SalProcEntry;\r
237	UINT64 SalGlobalDataPointer;\r
238	UINT64 Reserved2[2];\r
239	} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
240	\r
241	//\r
242	// Not needed for Itanium-based OS boot\r
243	//\r
244	typedef struct {\r
245	UINT8 Type; // Type == 1\r
246	UINT8 NeedVirtualRegistration;\r
247	UINT8 MemoryAttributes;\r
248	UINT8 PageAccessRights;\r
249	UINT8 SupportedAttributes;\r
250	UINT8 Reserved;\r
251	UINT8 MemoryType;\r
252	UINT8 MemoryUsage;\r
253	UINT64 PhysicalMemoryAddress;\r
254	UINT32 Length;\r
255	UINT32 Reserved1;\r
256	UINT64 OemReserved;\r
257	} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;\r
258	\r
259	#pragma pack()\r
260	//\r
261	// Memory Attributes\r
262	//\r
263	#define SAL_MDT_ATTRIB_WB 0x00\r
264	//\r
265	// #define SAL_MDT_ATTRIB_UC 0x02\r
266	//\r
267	#define SAL_MDT_ATTRIB_UC 0x04\r
268	#define SAL_MDT_ATTRIB_UCE 0x05\r
269	#define SAL_MDT_ATTRIB_WC 0x06\r
270	\r
271	//\r
272	// Supported memory Attributes\r
273	//\r
274	#define SAL_MDT_SUPPORT_WB 0x1\r
275	#define SAL_MDT_SUPPORT_UC 0x2\r
276	#define SAL_MDT_SUPPORT_UCE 0x4\r
277	#define SAL_MDT_SUPPORT_WC 0x8\r
278	\r
279	//\r
280	// Virtual address registration\r
281	//\r
282	#define SAL_MDT_NO_VA 0x00\r
283	#define SAL_MDT_NEED_VA 0x01\r
284	//\r
285	// MemoryType info\r
286	//\r
287	#define SAL_REGULAR_MEMORY 0x0000\r
288	#define SAL_MMIO_MAPPING 0x0001\r
289	#define SAL_SAPIC_IPI_BLOCK 0x0002\r
290	#define SAL_IO_PORT_MAPPING 0x0003\r
291	#define SAL_FIRMWARE_MEMORY 0x0004\r
292	#define SAL_BLACK_HOLE 0x000A\r
293	//\r
294	// Memory Usage info\r
295	//\r
296	#define SAL_MDT_USAGE_UNSPECIFIED 0x00\r
297	#define SAL_PAL_CODE 0x01\r
298	#define SAL_BOOTSERVICE_CODE 0x02\r
299	#define SAL_BOOTSERVICE_DATA 0x03\r
300	#define SAL_RUNTIMESERVICE_CODE 0x04\r
301	#define SAL_RUNTIMESERVICE_DATA 0x05\r
302	#define SAL_IA32_OPTIONROM 0x06\r
303	#define SAL_IA32_SYSTEMROM 0x07\r
304	#define SAL_PMI_CODE 0x0a\r
305	#define SAL_PMI_DATA 0x0b\r
306	\r
307	#pragma pack(1)\r
308	typedef struct {\r
309	UINT8 Type; // Type == 2\r
310	UINT8 PlatformFeatures;\r
311	UINT8 Reserved[14];\r
312	} SAL_ST_PLATFORM_FEATURES;\r
313	#pragma pack()\r
314	\r
315	#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
316	#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
317	#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
318	\r
319	#pragma pack(1)\r
320	typedef struct {\r
321	UINT8 Type; // Type == 3\r
322	UINT8 TRType;\r
323	UINT8 TRNumber;\r
324	UINT8 Reserved[5];\r
325	UINT64 VirtualAddress;\r
326	UINT64 EncodedPageSize;\r
327	UINT64 Reserved1;\r
328	} SAL_ST_TR_DECRIPTOR;\r
329	#pragma pack()\r
330	\r
331	#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
332	#define EFI_SAL_ST_TR_USAGE_DATA 01\r
333	\r
334	#pragma pack(1)\r
335	typedef struct {\r
336	UINT64 NumberOfProcessors;\r
337	UINT64 LocalIDRegister;\r
338	} SAL_COHERENCE_DOMAIN_INFO;\r
339	#pragma pack()\r
340	\r
341	#pragma pack(1)\r
342	typedef struct {\r
343	UINT8 Type; // Type == 4\r
344	UINT8 Reserved[3];\r
345	UINT32 NumberOfDomains;\r
346	SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
347	} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
348	#pragma pack()\r
349	\r
350	#pragma pack(1)\r
351	typedef struct {\r
352	UINT8 Type; // Type == 5\r
353	UINT8 WakeUpType;\r
354	UINT8 Reserved[6];\r
355	UINT64 ExternalInterruptVector;\r
356	} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
357	#pragma pack()\r
358	//\r
359	// FIT Entry\r
360	//\r
361	#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
362	#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
363	#define EFI_SAL_FIT_PALB_TYPE 01\r
364	\r
365	typedef struct {\r
366	UINT64 Address;\r
367	UINT8 Size[3];\r
368	UINT8 Reserved;\r
369	UINT16 Revision;\r
370	UINT8 Type : 7;\r
371	UINT8 CheckSumValid : 1;\r
372	UINT8 CheckSum;\r
373	} EFI_SAL_FIT_ENTRY;\r
374	\r
375	//\r
376	// SAL Common Record Header\r
377	//\r
378	typedef struct {\r
379	UINT16 Length;\r
380	UINT8 Data[1024];\r
381	} SAL_OEM_DATA;\r
382	\r
383	typedef struct {\r
384	UINT8 Seconds;\r
385	UINT8 Minutes;\r
386	UINT8 Hours;\r
387	UINT8 Reserved;\r
388	UINT8 Day;\r
389	UINT8 Month;\r
390	UINT8 Year;\r
391	UINT8 Century;\r
392	} SAL_TIME_STAMP;\r
393	\r
394	typedef struct {\r
395	UINT64 RecordId;\r
396	UINT16 Revision;\r
397	UINT8 ErrorSeverity;\r
398	UINT8 ValidationBits;\r
399	UINT32 RecordLength;\r
400	SAL_TIME_STAMP TimeStamp;\r
401	UINT8 OemPlatformId[16];\r
402	} SAL_RECORD_HEADER;\r
403	\r
404	typedef struct {\r
405	EFI_GUID Guid;\r
406	UINT16 Revision;\r
407	UINT8 ErrorRecoveryInfo;\r
408	UINT8 Reserved;\r
409	UINT32 SectionLength;\r
410	} SAL_SEC_HEADER;\r
411	\r
412	//\r
413	// SAL Processor Record\r
414	//\r
415	#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
416	{ \\r
7ccf38a3	417	0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
3eb9473e	418	}\r
	419	\r
	420	#define CHECK_INFO_VALID_BIT_MASK 0x1\r
	421	#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
	422	#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
	423	#define TARGER_ID_VALID_BIT_MASK 0x8\r
	424	#define PRECISE_IP_VALID_BIT_MASK 0x10\r
	425	\r
	426	typedef struct {\r
	427	UINT64 InfoValid : 1;\r
	428	UINT64 ReqValid : 1;\r
	429	UINT64 RespValid : 1;\r
	430	UINT64 TargetValid : 1;\r
	431	UINT64 IpValid : 1;\r
	432	UINT64 Reserved : 59;\r
	433	UINT64 Info;\r
	434	UINT64 Req;\r
	435	UINT64 Resp;\r
	436	UINT64 Target;\r
	437	UINT64 Ip;\r
	438	} MOD_ERROR_INFO;\r
	439	\r
	440	typedef struct {\r
	441	UINT8 CpuidInfo[40];\r
	442	UINT8 Reserved;\r
	443	} CPUID_INFO;\r
	444	\r
	445	typedef struct {\r
	446	UINT64 FrLow;\r
	447	UINT64 FrHigh;\r
	448	} FR_STRUCT;\r
	449	\r
	450	#define MIN_STATE_VALID_BIT_MASK 0x1\r
	451	#define BR_VALID_BIT_MASK 0x2\r
	452	#define CR_VALID_BIT_MASK 0x4\r
	453	#define AR_VALID_BIT_MASK 0x8\r
	454	#define RR_VALID_BIT_MASK 0x10\r
	455	#define FR_VALID_BIT_MASK 0x20\r
	456	\r
	457	typedef struct {\r
	458	UINT64 ValidFieldBits;\r
	459	UINT8 MinStateInfo[1024];\r
	460	UINT64 Br[8];\r
	461	UINT64 Cr[128];\r
	462	UINT64 Ar[128];\r
	463	UINT64 Rr[8];\r
	464	FR_STRUCT Fr[128];\r
	465	} PSI_STATIC_STRUCT;\r
	466	\r
	467	#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
	468	#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
	469	#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
	470	#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
	471	#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
	472	\r
	473	typedef struct {\r
	474	SAL_SEC_HEADER SectionHeader;\r
	475	UINT64 ValidationBits;\r
	476	UINT64 ProcErrorMap;\r
	477	UINT64 ProcStateParameter;\r
	478	UINT64 ProcCrLid;\r
	479	MOD_ERROR_INFO CacheError[15];\r
	480	MOD_ERROR_INFO TlbError[15];\r
	481	MOD_ERROR_INFO BusError[15];\r
482	MOD_ERROR_INFO RegFileCheck[15];\r
483	MOD_ERROR_INFO MsCheck[15];\r
484	CPUID_INFO CpuInfo;\r
485	PSI_STATIC_STRUCT PsiValidData;\r
486	} SAL_PROCESSOR_ERROR_RECORD;\r
487	\r
488	//\r
489	// Sal Platform memory Error Record\r
490	//\r
491	#define SAL_MEMORY_ERROR_RECORD_INFO \\r
492	{ \\r
7ccf38a3	493	0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
3eb9473e	494	}\r
	495	\r
	496	#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
	497	#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
	498	#define MEMORY_ADDR_BIT_MASK 0x4\r
	499	#define MEMORY_NODE_VALID_BIT_MASK 0x8\r
	500	#define MEMORY_CARD_VALID_BIT_MASK 0x10\r
	501	#define MEMORY_MODULE_VALID_BIT_MASK 0x20\r
	502	#define MEMORY_BANK_VALID_BIT_MASK 0x40\r
	503	#define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r
	504	#define MEMORY_ROW_VALID_BIT_MASK 0x100\r
	505	#define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r
	506	#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r
	507	#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r
	508	#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r
	509	#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r
	510	#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
	511	#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
	512	#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
	513	\r
	514	typedef struct {\r
	515	SAL_SEC_HEADER SectionHeader;\r
	516	UINT64 ValidationBits;\r
	517	UINT64 MemErrorStatus;\r
	518	UINT64 MemPhysicalAddress;\r
	519	UINT64 MemPhysicalAddressMask;\r
	520	UINT16 MemNode;\r
	521	UINT16 MemCard;\r
	522	UINT16 MemModule;\r
	523	UINT16 MemBank;\r
	524	UINT16 MemDevice;\r
	525	UINT16 MemRow;\r
	526	UINT16 MemColumn;\r
	527	UINT16 MemBitPosition;\r
	528	UINT64 ModRequestorId;\r
	529	UINT64 ModResponderId;\r
	530	UINT64 ModTargetId;\r
	531	UINT64 BusSpecificData;\r
	532	UINT8 MemPlatformOemId[16];\r
	533	} SAL_MEMORY_ERROR_RECORD;\r
	534	\r
	535	//\r
	536	// PCI BUS Errors\r
	537	//\r
	538	#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
	539	{ \\r
7ccf38a3	540	0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
3eb9473e	541	}\r
	542	\r
	543	#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
	544	#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
	545	#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
	546	#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r
	547	#define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r
	548	#define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r
	549	#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r
	550	#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r
	551	#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r
	552	#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r
	553	#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
	554	\r
	555	typedef enum {\r
	556	Unknown,\r
	557	DataParityError,\r
	558	SystemError,\r
	559	MasterAbort,\r
	560	BusTimeout,\r
	561	MasterDataParityError,\r
	562	AddressParityError,\r
	563	CommandParityError\r
	564	} PCI_BUS_ERROR_TYPE;\r
	565	\r
	566	typedef struct {\r
	567	UINT8 BusNumber;\r
	568	UINT8 SegmentNumber;\r
	569	} PCI_BUS_ID;\r
	570	\r
	571	typedef struct {\r
	572	SAL_SEC_HEADER SectionHeader;\r
	573	UINT64 ValidationBits;\r
	574	UINT64 PciBusErrorStatus;\r
	575	UINT16 PciBusErrorType;\r
	576	PCI_BUS_ID PciBusId;\r
	577	UINT32 Reserved;\r
	578	UINT64 PciBusAddress;\r
	579	UINT64 PciBusData;\r
	580	UINT64 PciBusCommand;\r
	581	UINT64 PciBusRequestorId;\r
	582	UINT64 PciBusResponderId;\r
	583	UINT64 PciBusTargetId;\r
	584	UINT8 PciBusOemId[16];\r
	585	} SAL_PCI_BUS_ERROR_RECORD;\r
	586	\r
	587	//\r
	588	// PCI Component Errors\r
	589	//\r
	590	#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
	591	{ \\r
7ccf38a3	592	0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
3eb9473e	593	}\r
	594	\r
	595	#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
	596	#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
	597	#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
	598	#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
	599	#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
	600	#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
	601	\r
	602	typedef struct {\r
	603	UINT16 VendorId;\r
	604	UINT16 DeviceId;\r
	605	UINT8 ClassCode[3];\r
	606	UINT8 FunctionNumber;\r
	607	UINT8 DeviceNumber;\r
	608	UINT8 BusNumber;\r
	609	UINT8 SegmentNumber;\r
	610	UINT8 Reserved[5];\r
	611	} PCI_COMP_INFO;\r
	612	\r
	613	typedef struct {\r
	614	SAL_SEC_HEADER SectionHeader;\r
	615	UINT64 ValidationBits;\r
	616	UINT64 PciComponentErrorStatus;\r
	617	PCI_COMP_INFO PciComponentInfo;\r
	618	UINT32 PciComponentMemNum;\r
	619	UINT32 PciComponentIoNum;\r
	620	UINT8 PciBusOemId[16];\r
	621	} SAL_PCI_COMPONENT_ERROR_RECORD;\r
	622	\r
	623	//\r
	624	// Sal Device Errors Info.\r
	625	//\r
	626	#define SAL_DEVICE_ERROR_RECORD_INFO \\r
	627	{ \\r
7ccf38a3	628	0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
3eb9473e	629	}\r
	630	\r
	631	#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
	632	#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
	633	#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
	634	#define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r
	635	#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r
	636	#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r
	637	#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
	638	#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
	639	#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
	640	#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
	641	\r
	642	typedef struct {\r
	643	SAL_SEC_HEADER SectionHeader;\r
	644	UINT64 ValidationBits;\r
	645	UINT16 SelRecordId;\r
	646	UINT8 SelRecordType;\r
	647	UINT32 TimeStamp;\r
	648	UINT16 GeneratorId;\r
	649	UINT8 EvmRevision;\r
	650	UINT8 SensorType;\r
	651	UINT8 SensorNum;\r
	652	UINT8 EventDirType;\r
	653	UINT8 Data1;\r
	654	UINT8 Data2;\r
	655	UINT8 Data3;\r
	656	} SAL_DEVICE_ERROR_RECORD;\r
	657	\r
	658	//\r
	659	// Sal SMBIOS Device Errors Info.\r
	660	//\r
	661	#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
	662	{ \\r
7ccf38a3	663	0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
3eb9473e	664	}\r
	665	\r
	666	#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
	667	#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
	668	#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
	669	#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
	670	\r
	671	typedef struct {\r
	672	SAL_SEC_HEADER SectionHeader;\r
	673	UINT64 ValidationBits;\r
	674	UINT8 SmbiosEventType;\r
	675	UINT8 SmbiosLength;\r
	676	UINT8 SmbiosBcdTimeStamp[6];\r
	677	} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
	678	\r
	679	//\r
	680	// Sal Platform Specific Errors Info.\r
	681	//\r
	682	#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
	683	{ \\r
7ccf38a3	684	0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81} \\r
3eb9473e	685	}\r
	686	\r
	687	#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
	688	#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
	689	#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
	690	#define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r
	691	#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r
	692	#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
	693	#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
	694	#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
	695	\r
	696	typedef struct {\r
	697	SAL_SEC_HEADER SectionHeader;\r
	698	UINT64 ValidationBits;\r
	699	UINT64 PlatformErrorStatus;\r
	700	UINT64 PlatformRequestorId;\r
	701	UINT64 PlatformResponderId;\r
	702	UINT64 PlatformTargetId;\r
	703	UINT64 PlatformBusSpecificData;\r
	704	UINT8 OemComponentId[16];\r
	705	} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
	706	\r
	707	//\r
	708	// Union of all the possible Sal Record Types\r
	709	//\r
	710	typedef union {\r
	711	SAL_RECORD_HEADER *RecordHeader;\r
	712	SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
	713	SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
	714	SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
	715	SAL_DEVICE_ERROR_RECORD *ImpiRecord;\r
	716	SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
	717	SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
	718	SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
	719	UINT8 *Raw;\r
	720	} SAL_ERROR_RECORDS_POINTERS;\r
	721	\r
	722	#pragma pack()\r
	723	\r
	724	#endif\r