projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 3eb9473e | 1 | /*++\r |
| 2 | \r | |
| 2c7e5c2f HT |
3 | Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>\r |
| 4 | This program and the accompanying materials \r | |
| 3eb9473e | 5 | are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | which accompanies this distribution. The full text of the license may be found at \r | |
| 7 | http://opensource.org/licenses/bsd-license.php \r | |
| 8 | \r | |
| 9 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 10 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 11 | \r | |
| 12 | \r | |
| 13 | Module Name:\r | |
| 14 | \r | |
| 15 | EdkIIGluePciCf8Lib.h\r | |
| 16 | \r | |
| 17 | Abstract: \r | |
| 18 | \r | |
| 19 | Public header file for Pci Cf8 Lib\r | |
| 20 | \r | |
| 21 | --*/\r | |
| 22 | \r | |
| 23 | #ifndef __EDKII_GLUE_PCI_CF8_LIB_H__\r | |
| 24 | #define __EDKII_GLUE_PCI_CF8_LIB_H__\r | |
| 25 | \r | |
| 26 | \r | |
| 27 | /**\r | |
| 28 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
| 29 | address that can be passed to the PCI Library functions.\r | |
| 30 | \r | |
| 31 | Computes an address that is compatible with the PCI Library functions. The\r | |
| 32 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
| 33 | the generation of the address.\r | |
| 34 | \r | |
| 35 | @param Bus PCI Bus number. Range 0..255.\r | |
| 36 | @param Device PCI Device number. Range 0..31.\r | |
| 37 | @param Function PCI Function number. Range 0..7.\r | |
| 38 | @param Register PCI Register number. Range 0..255.\r | |
| 39 | \r | |
| 40 | @return The encode PCI address.\r | |
| 41 | \r | |
| 42 | **/\r | |
| 43 | #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
| 44 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
| 45 | \r | |
| 46 | /**\r | |
| 47 | Reads an 8-bit PCI configuration register.\r | |
| 48 | \r | |
| 49 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
| 50 | This function must guarantee that all PCI read and write operations are\r | |
| 51 | serialized.\r | |
| 52 | \r | |
| 53 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 54 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 55 | \r | |
| 56 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 57 | Register.\r | |
| 58 | \r | |
| 59 | @return The read value from the PCI configuration register.\r | |
| 60 | \r | |
| 61 | **/\r | |
| 62 | UINT8\r | |
| 63 | EFIAPI\r | |
| 64 | PciCf8Read8 (\r | |
| 65 | IN UINTN Address\r | |
| 66 | );\r | |
| 67 | \r | |
| 68 | /**\r | |
| 69 | Writes an 8-bit PCI configuration register.\r | |
| 70 | \r | |
| 71 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
| 72 | value specified by Value. Value is returned. This function must guarantee\r | |
| 73 | that all PCI read and write operations are serialized.\r | |
| 74 | \r | |
| 75 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 76 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 77 | \r | |
| 78 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 79 | Register.\r | |
| 80 | @param Value The value to write.\r | |
| 81 | \r | |
| 82 | @return The value written to the PCI configuration register.\r | |
| 83 | \r | |
| 84 | **/\r | |
| 85 | UINT8\r | |
| 86 | EFIAPI\r | |
| 87 | PciCf8Write8 (\r | |
| 88 | IN UINTN Address,\r | |
| 89 | IN UINT8 Data\r | |
| 90 | );\r | |
| 91 | \r | |
| 92 | /**\r | |
| 93 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
| 94 | an 8-bit value.\r | |
| 95 | \r | |
| 96 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 97 | bitwise inclusive OR between the read result and the value specified by\r | |
| 98 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 99 | specified by Address. The value written to the PCI configuration register is\r | |
| 100 | returned. This function must guarantee that all PCI read and write operations\r | |
| 101 | are serialized.\r | |
| 102 | \r | |
| 103 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 104 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 105 | \r | |
| 106 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 107 | Register.\r | |
| 108 | @param OrData The value to OR with the PCI configuration register.\r | |
| 109 | \r | |
| 110 | @return The value written back to the PCI configuration register.\r | |
| 111 | \r | |
| 112 | **/\r | |
| 113 | UINT8\r | |
| 114 | EFIAPI\r | |
| 115 | PciCf8Or8 (\r | |
| 116 | IN UINTN Address,\r | |
| 117 | IN UINT8 OrData\r | |
| 118 | );\r | |
| 119 | \r | |
| 120 | /**\r | |
| 121 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 122 | value.\r | |
| 123 | \r | |
| 124 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 125 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 126 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 127 | Address. The value written to the PCI configuration register is returned.\r | |
| 128 | This function must guarantee that all PCI read and write operations are\r | |
| 129 | serialized.\r | |
| 130 | \r | |
| 131 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 132 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 133 | \r | |
| 134 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 135 | Register.\r | |
| 136 | @param AndData The value to AND with the PCI configuration register.\r | |
| 137 | \r | |
| 138 | @return The value written back to the PCI configuration register.\r | |
| 139 | \r | |
| 140 | **/\r | |
| 141 | UINT8\r | |
| 142 | EFIAPI\r | |
| 143 | PciCf8And8 (\r | |
| 144 | IN UINTN Address,\r | |
| 145 | IN UINT8 AndData\r | |
| 146 | );\r | |
| 147 | \r | |
| 148 | /**\r | |
| 149 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 150 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
| 151 | \r | |
| 152 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 153 | bitwise AND between the read result and the value specified by AndData,\r | |
| 154 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
| 155 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
| 156 | configuration register specified by Address. The value written to the PCI\r | |
| 157 | configuration register is returned. This function must guarantee that all PCI\r | |
| 158 | read and write operations are serialized.\r | |
| 159 | \r | |
| 160 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 161 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 162 | \r | |
| 163 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 164 | Register.\r | |
| 165 | @param AndData The value to AND with the PCI configuration register.\r | |
| 166 | @param OrData The value to OR with the result of the AND operation.\r | |
| 167 | \r | |
| 168 | @return The value written back to the PCI configuration register.\r | |
| 169 | \r | |
| 170 | **/\r | |
| 171 | UINT8\r | |
| 172 | EFIAPI\r | |
| 173 | PciCf8AndThenOr8 (\r | |
| 174 | IN UINTN Address,\r | |
| 175 | IN UINT8 AndData,\r | |
| 176 | IN UINT8 OrData\r | |
| 177 | );\r | |
| 178 | \r | |
| 179 | /**\r | |
| 180 | Reads a bit field of a PCI configuration register.\r | |
| 181 | \r | |
| 182 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
| 183 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 184 | returned.\r | |
| 185 | \r | |
| 186 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 187 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 188 | If StartBit is greater than 7, then ASSERT().\r | |
| 189 | If EndBit is greater than 7, then ASSERT().\r | |
| 190 | If EndBit is less than StartBit, then ASSERT().\r | |
| 191 | \r | |
| 192 | @param Address PCI configuration register to read.\r | |
| 193 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 194 | Range 0..7.\r | |
| 195 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 196 | Range 0..7.\r | |
| 197 | \r | |
| 198 | @return The value of the bit field read from the PCI configuration register.\r | |
| 199 | \r | |
| 200 | **/\r | |
| 201 | UINT8\r | |
| 202 | EFIAPI\r | |
| 203 | PciCf8BitFieldRead8 (\r | |
| 204 | IN UINTN Address,\r | |
| 205 | IN UINTN StartBit,\r | |
| 206 | IN UINTN EndBit\r | |
| 207 | );\r | |
| 208 | \r | |
| 209 | /**\r | |
| 210 | Writes a bit field to a PCI configuration register.\r | |
| 211 | \r | |
| 212 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 213 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 214 | destination PCI configuration register are preserved. The new value of the\r | |
| 215 | 8-bit register is returned.\r | |
| 216 | \r | |
| 217 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 218 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 219 | If StartBit is greater than 7, then ASSERT().\r | |
| 220 | If EndBit is greater than 7, then ASSERT().\r | |
| 221 | If EndBit is less than StartBit, then ASSERT().\r | |
| 222 | \r | |
| 223 | @param Address PCI configuration register to write.\r | |
| 224 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 225 | Range 0..7.\r | |
| 226 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 227 | Range 0..7.\r | |
| 228 | @param Value New value of the bit field.\r | |
| 229 | \r | |
| 230 | @return The value written back to the PCI configuration register.\r | |
| 231 | \r | |
| 232 | **/\r | |
| 233 | UINT8\r | |
| 234 | EFIAPI\r | |
| 235 | PciCf8BitFieldWrite8 (\r | |
| 236 | IN UINTN Address,\r | |
| 237 | IN UINTN StartBit,\r | |
| 238 | IN UINTN EndBit,\r | |
| 239 | IN UINT8 Value\r | |
| 240 | );\r | |
| 241 | \r | |
| 242 | /**\r | |
| 243 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
| 244 | writes the result back to the bit field in the 8-bit port.\r | |
| 245 | \r | |
| 246 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 247 | bitwise inclusive OR between the read result and the value specified by\r | |
| 248 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 249 | specified by Address. The value written to the PCI configuration register is\r | |
| 250 | returned. This function must guarantee that all PCI read and write operations\r | |
| 251 | are serialized. Extra left bits in OrData are stripped.\r | |
| 252 | \r | |
| 253 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 254 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 255 | If StartBit is greater than 7, then ASSERT().\r | |
| 256 | If EndBit is greater than 7, then ASSERT().\r | |
| 257 | If EndBit is less than StartBit, then ASSERT().\r | |
| 258 | \r | |
| 259 | @param Address PCI configuration register to write.\r | |
| 260 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 261 | Range 0..7.\r | |
| 262 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 263 | Range 0..7.\r | |
| 264 | @param OrData The value to OR with the PCI configuration register.\r | |
| 265 | \r | |
| 266 | @return The value written back to the PCI configuration register.\r | |
| 267 | \r | |
| 268 | **/\r | |
| 269 | UINT8\r | |
| 270 | EFIAPI\r | |
| 271 | PciCf8BitFieldOr8 (\r | |
| 272 | IN UINTN Address,\r | |
| 273 | IN UINTN StartBit,\r | |
| 274 | IN UINTN EndBit,\r | |
| 275 | IN UINT8 OrData\r | |
| 276 | );\r | |
| 277 | \r | |
| 278 | /**\r | |
| 279 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
| 280 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
| 281 | \r | |
| 282 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 283 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 284 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 285 | Address. The value written to the PCI configuration register is returned.\r | |
| 286 | This function must guarantee that all PCI read and write operations are\r | |
| 287 | serialized. Extra left bits in AndData are stripped.\r | |
| 288 | \r | |
| 289 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 290 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 291 | If StartBit is greater than 7, then ASSERT().\r | |
| 292 | If EndBit is greater than 7, then ASSERT().\r | |
| 293 | If EndBit is less than StartBit, then ASSERT().\r | |
| 294 | \r | |
| 295 | @param Address PCI configuration register to write.\r | |
| 296 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 297 | Range 0..7.\r | |
| 298 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 299 | Range 0..7.\r | |
| 300 | @param AndData The value to AND with the PCI configuration register.\r | |
| 301 | \r | |
| 302 | @return The value written back to the PCI configuration register.\r | |
| 303 | \r | |
| 304 | **/\r | |
| 305 | UINT8\r | |
| 306 | EFIAPI\r | |
| 307 | PciCf8BitFieldAnd8 (\r | |
| 308 | IN UINTN Address,\r | |
| 309 | IN UINTN StartBit,\r | |
| 310 | IN UINTN EndBit,\r | |
| 311 | IN UINT8 AndData\r | |
| 312 | );\r | |
| 313 | \r | |
| 314 | /**\r | |
| 315 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
| 316 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
| 317 | 8-bit port.\r | |
| 318 | \r | |
| 319 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 320 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
| 321 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
| 322 | configuration register specified by Address. The value written to the PCI\r | |
| 323 | configuration register is returned. This function must guarantee that all PCI\r | |
| 324 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 325 | OrData are stripped.\r | |
| 326 | \r | |
| 327 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 328 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 329 | If StartBit is greater than 7, then ASSERT().\r | |
| 330 | If EndBit is greater than 7, then ASSERT().\r | |
| 331 | If EndBit is less than StartBit, then ASSERT().\r | |
| 332 | \r | |
| 333 | @param Address PCI configuration register to write.\r | |
| 334 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 335 | Range 0..7.\r | |
| 336 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 337 | Range 0..7.\r | |
| 338 | @param AndData The value to AND with the PCI configuration register.\r | |
| 339 | @param OrData The value to OR with the result of the AND operation.\r | |
| 340 | \r | |
| 341 | @return The value written back to the PCI configuration register.\r | |
| 342 | \r | |
| 343 | **/\r | |
| 344 | UINT8\r | |
| 345 | EFIAPI\r | |
| 346 | PciCf8BitFieldAndThenOr8 (\r | |
| 347 | IN UINTN Address,\r | |
| 348 | IN UINTN StartBit,\r | |
| 349 | IN UINTN EndBit,\r | |
| 350 | IN UINT8 AndData,\r | |
| 351 | IN UINT8 OrData\r | |
| 352 | );\r | |
| 353 | \r | |
| 354 | /**\r | |
| 355 | Reads a 16-bit PCI configuration register.\r | |
| 356 | \r | |
| 357 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
| 358 | This function must guarantee that all PCI read and write operations are\r | |
| 359 | serialized.\r | |
| 360 | \r | |
| 361 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 362 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 363 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 364 | \r | |
| 365 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 366 | Register.\r | |
| 367 | \r | |
| 368 | @return The read value from the PCI configuration register.\r | |
| 369 | \r | |
| 370 | **/\r | |
| 371 | UINT16\r | |
| 372 | EFIAPI\r | |
| 373 | PciCf8Read16 (\r | |
| 374 | IN UINTN Address\r | |
| 375 | );\r | |
| 376 | \r | |
| 377 | /**\r | |
| 378 | Writes a 16-bit PCI configuration register.\r | |
| 379 | \r | |
| 380 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
| 381 | value specified by Value. Value is returned. This function must guarantee\r | |
| 382 | that all PCI read and write operations are serialized.\r | |
| 383 | \r | |
| 384 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 385 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 386 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 387 | \r | |
| 388 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 389 | Register.\r | |
| 390 | @param Value The value to write.\r | |
| 391 | \r | |
| 392 | @return The value written to the PCI configuration register.\r | |
| 393 | \r | |
| 394 | **/\r | |
| 395 | UINT16\r | |
| 396 | EFIAPI\r | |
| 397 | PciCf8Write16 (\r | |
| 398 | IN UINTN Address,\r | |
| 399 | IN UINT16 Data\r | |
| 400 | );\r | |
| 401 | \r | |
| 402 | /**\r | |
| 403 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
| 404 | a 16-bit value.\r | |
| 405 | \r | |
| 406 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 407 | bitwise inclusive OR between the read result and the value specified by\r | |
| 408 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 409 | specified by Address. The value written to the PCI configuration register is\r | |
| 410 | returned. This function must guarantee that all PCI read and write operations\r | |
| 411 | are serialized.\r | |
| 412 | \r | |
| 413 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 414 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 415 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 416 | \r | |
| 417 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 418 | Register.\r | |
| 419 | @param OrData The value to OR with the PCI configuration register.\r | |
| 420 | \r | |
| 421 | @return The value written back to the PCI configuration register.\r | |
| 422 | \r | |
| 423 | **/\r | |
| 424 | UINT16\r | |
| 425 | EFIAPI\r | |
| 426 | PciCf8Or16 (\r | |
| 427 | IN UINTN Address,\r | |
| 428 | IN UINT16 OrData\r | |
| 429 | );\r | |
| 430 | \r | |
| 431 | /**\r | |
| 432 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 433 | value.\r | |
| 434 | \r | |
| 435 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 436 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 437 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 438 | Address. The value written to the PCI configuration register is returned.\r | |
| 439 | This function must guarantee that all PCI read and write operations are\r | |
| 440 | serialized.\r | |
| 441 | \r | |
| 442 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 443 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 444 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 445 | \r | |
| 446 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 447 | Register.\r | |
| 448 | @param AndData The value to AND with the PCI configuration register.\r | |
| 449 | \r | |
| 450 | @return The value written back to the PCI configuration register.\r | |
| 451 | \r | |
| 452 | **/\r | |
| 453 | UINT16\r | |
| 454 | EFIAPI\r | |
| 455 | PciCf8And16 (\r | |
| 456 | IN UINTN Address,\r | |
| 457 | IN UINT16 AndData\r | |
| 458 | );\r | |
| 459 | \r | |
| 460 | /**\r | |
| 461 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 462 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
| 463 | \r | |
| 464 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 465 | bitwise AND between the read result and the value specified by AndData,\r | |
| 466 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
| 467 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
| 468 | configuration register specified by Address. The value written to the PCI\r | |
| 469 | configuration register is returned. This function must guarantee that all PCI\r | |
| 470 | read and write operations are serialized.\r | |
| 471 | \r | |
| 472 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 473 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 474 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 475 | \r | |
| 476 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 477 | Register.\r | |
| 478 | @param AndData The value to AND with the PCI configuration register.\r | |
| 479 | @param OrData The value to OR with the result of the AND operation.\r | |
| 480 | \r | |
| 481 | @return The value written back to the PCI configuration register.\r | |
| 482 | \r | |
| 483 | **/\r | |
| 484 | UINT16\r | |
| 485 | EFIAPI\r | |
| 486 | PciCf8AndThenOr16 (\r | |
| 487 | IN UINTN Address,\r | |
| 488 | IN UINT16 AndData,\r | |
| 489 | IN UINT16 OrData\r | |
| 490 | );\r | |
| 491 | \r | |
| 492 | /**\r | |
| 493 | Reads a bit field of a PCI configuration register.\r | |
| 494 | \r | |
| 495 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
| 496 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 497 | returned.\r | |
| 498 | \r | |
| 499 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 500 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 501 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 502 | If StartBit is greater than 15, then ASSERT().\r | |
| 503 | If EndBit is greater than 15, then ASSERT().\r | |
| 504 | If EndBit is less than StartBit, then ASSERT().\r | |
| 505 | \r | |
| 506 | @param Address PCI configuration register to read.\r | |
| 507 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 508 | Range 0..15.\r | |
| 509 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 510 | Range 0..15.\r | |
| 511 | \r | |
| 512 | @return The value of the bit field read from the PCI configuration register.\r | |
| 513 | \r | |
| 514 | **/\r | |
| 515 | UINT16\r | |
| 516 | EFIAPI\r | |
| 517 | PciCf8BitFieldRead16 (\r | |
| 518 | IN UINTN Address,\r | |
| 519 | IN UINTN StartBit,\r | |
| 520 | IN UINTN EndBit\r | |
| 521 | );\r | |
| 522 | \r | |
| 523 | /**\r | |
| 524 | Writes a bit field to a PCI configuration register.\r | |
| 525 | \r | |
| 526 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 527 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 528 | destination PCI configuration register are preserved. The new value of the\r | |
| 529 | 16-bit register is returned.\r | |
| 530 | \r | |
| 531 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 532 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 533 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 534 | If StartBit is greater than 15, then ASSERT().\r | |
| 535 | If EndBit is greater than 15, then ASSERT().\r | |
| 536 | If EndBit is less than StartBit, then ASSERT().\r | |
| 537 | \r | |
| 538 | @param Address PCI configuration register to write.\r | |
| 539 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 540 | Range 0..15.\r | |
| 541 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 542 | Range 0..15.\r | |
| 543 | @param Value New value of the bit field.\r | |
| 544 | \r | |
| 545 | @return The value written back to the PCI configuration register.\r | |
| 546 | \r | |
| 547 | **/\r | |
| 548 | UINT16\r | |
| 549 | EFIAPI\r | |
| 550 | PciCf8BitFieldWrite16 (\r | |
| 551 | IN UINTN Address,\r | |
| 552 | IN UINTN StartBit,\r | |
| 553 | IN UINTN EndBit,\r | |
| 554 | IN UINT16 Value\r | |
| 555 | );\r | |
| 556 | \r | |
| 557 | /**\r | |
| 558 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
| 559 | writes the result back to the bit field in the 16-bit port.\r | |
| 560 | \r | |
| 561 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 562 | bitwise inclusive OR between the read result and the value specified by\r | |
| 563 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 564 | specified by Address. The value written to the PCI configuration register is\r | |
| 565 | returned. This function must guarantee that all PCI read and write operations\r | |
| 566 | are serialized. Extra left bits in OrData are stripped.\r | |
| 567 | \r | |
| 568 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 569 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 570 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 571 | If StartBit is greater than 15, then ASSERT().\r | |
| 572 | If EndBit is greater than 15, then ASSERT().\r | |
| 573 | If EndBit is less than StartBit, then ASSERT().\r | |
| 574 | \r | |
| 575 | @param Address PCI configuration register to write.\r | |
| 576 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 577 | Range 0..15.\r | |
| 578 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 579 | Range 0..15.\r | |
| 580 | @param OrData The value to OR with the PCI configuration register.\r | |
| 581 | \r | |
| 582 | @return The value written back to the PCI configuration register.\r | |
| 583 | \r | |
| 584 | **/\r | |
| 585 | UINT16\r | |
| 586 | EFIAPI\r | |
| 587 | PciCf8BitFieldOr16 (\r | |
| 588 | IN UINTN Address,\r | |
| 589 | IN UINTN StartBit,\r | |
| 590 | IN UINTN EndBit,\r | |
| 591 | IN UINT16 OrData\r | |
| 592 | );\r | |
| 593 | \r | |
| 594 | /**\r | |
| 595 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
| 596 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
| 597 | \r | |
| 598 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 599 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 600 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 601 | Address. The value written to the PCI configuration register is returned.\r | |
| 602 | This function must guarantee that all PCI read and write operations are\r | |
| 603 | serialized. Extra left bits in AndData are stripped.\r | |
| 604 | \r | |
| 605 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 606 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 607 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 608 | If StartBit is greater than 15, then ASSERT().\r | |
| 609 | If EndBit is greater than 15, then ASSERT().\r | |
| 610 | If EndBit is less than StartBit, then ASSERT().\r | |
| 611 | \r | |
| 612 | @param Address PCI configuration register to write.\r | |
| 613 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 614 | Range 0..15.\r | |
| 615 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 616 | Range 0..15.\r | |
| 617 | @param AndData The value to AND with the PCI configuration register.\r | |
| 618 | \r | |
| 619 | @return The value written back to the PCI configuration register.\r | |
| 620 | \r | |
| 621 | **/\r | |
| 622 | UINT16\r | |
| 623 | EFIAPI\r | |
| 624 | PciCf8BitFieldAnd16 (\r | |
| 625 | IN UINTN Address,\r | |
| 626 | IN UINTN StartBit,\r | |
| 627 | IN UINTN EndBit,\r | |
| 628 | IN UINT16 AndData\r | |
| 629 | );\r | |
| 630 | \r | |
| 631 | /**\r | |
| 632 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
| 633 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
| 634 | 16-bit port.\r | |
| 635 | \r | |
| 636 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 637 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
| 638 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
| 639 | configuration register specified by Address. The value written to the PCI\r | |
| 640 | configuration register is returned. This function must guarantee that all PCI\r | |
| 641 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 642 | OrData are stripped.\r | |
| 643 | \r | |
| 644 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 645 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 646 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 647 | If StartBit is greater than 15, then ASSERT().\r | |
| 648 | If EndBit is greater than 15, then ASSERT().\r | |
| 649 | If EndBit is less than StartBit, then ASSERT().\r | |
| 650 | \r | |
| 651 | @param Address PCI configuration register to write.\r | |
| 652 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 653 | Range 0..15.\r | |
| 654 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 655 | Range 0..15.\r | |
| 656 | @param AndData The value to AND with the PCI configuration register.\r | |
| 657 | @param OrData The value to OR with the result of the AND operation.\r | |
| 658 | \r | |
| 659 | @return The value written back to the PCI configuration register.\r | |
| 660 | \r | |
| 661 | **/\r | |
| 662 | UINT16\r | |
| 663 | EFIAPI\r | |
| 664 | PciCf8BitFieldAndThenOr16 (\r | |
| 665 | IN UINTN Address,\r | |
| 666 | IN UINTN StartBit,\r | |
| 667 | IN UINTN EndBit,\r | |
| 668 | IN UINT16 AndData,\r | |
| 669 | IN UINT16 OrData\r | |
| 670 | );\r | |
| 671 | \r | |
| 672 | /**\r | |
| 673 | Reads a 32-bit PCI configuration register.\r | |
| 674 | \r | |
| 675 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
| 676 | This function must guarantee that all PCI read and write operations are\r | |
| 677 | serialized.\r | |
| 678 | \r | |
| 679 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 680 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 681 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 682 | \r | |
| 683 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 684 | Register.\r | |
| 685 | \r | |
| 686 | @return The read value from the PCI configuration register.\r | |
| 687 | \r | |
| 688 | **/\r | |
| 689 | UINT32\r | |
| 690 | EFIAPI\r | |
| 691 | PciCf8Read32 (\r | |
| 692 | IN UINTN Address\r | |
| 693 | );\r | |
| 694 | \r | |
| 695 | /**\r | |
| 696 | Writes a 32-bit PCI configuration register.\r | |
| 697 | \r | |
| 698 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
| 699 | value specified by Value. Value is returned. This function must guarantee\r | |
| 700 | that all PCI read and write operations are serialized.\r | |
| 701 | \r | |
| 702 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 703 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 704 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 705 | \r | |
| 706 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 707 | Register.\r | |
| 708 | @param Value The value to write.\r | |
| 709 | \r | |
| 710 | @return The value written to the PCI configuration register.\r | |
| 711 | \r | |
| 712 | **/\r | |
| 713 | UINT32\r | |
| 714 | EFIAPI\r | |
| 715 | PciCf8Write32 (\r | |
| 716 | IN UINTN Address,\r | |
| 717 | IN UINT32 Data\r | |
| 718 | );\r | |
| 719 | \r | |
| 720 | /**\r | |
| 721 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
| 722 | a 32-bit value.\r | |
| 723 | \r | |
| 724 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 725 | bitwise inclusive OR between the read result and the value specified by\r | |
| 726 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 727 | specified by Address. The value written to the PCI configuration register is\r | |
| 728 | returned. This function must guarantee that all PCI read and write operations\r | |
| 729 | are serialized.\r | |
| 730 | \r | |
| 731 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 732 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 733 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 734 | \r | |
| 735 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 736 | Register.\r | |
| 737 | @param OrData The value to OR with the PCI configuration register.\r | |
| 738 | \r | |
| 739 | @return The value written back to the PCI configuration register.\r | |
| 740 | \r | |
| 741 | **/\r | |
| 742 | UINT32\r | |
| 743 | EFIAPI\r | |
| 744 | PciCf8Or32 (\r | |
| 745 | IN UINTN Address,\r | |
| 746 | IN UINT32 OrData\r | |
| 747 | );\r | |
| 748 | \r | |
| 749 | /**\r | |
| 750 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 751 | value.\r | |
| 752 | \r | |
| 753 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 754 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 755 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 756 | Address. The value written to the PCI configuration register is returned.\r | |
| 757 | This function must guarantee that all PCI read and write operations are\r | |
| 758 | serialized.\r | |
| 759 | \r | |
| 760 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 761 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 762 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 763 | \r | |
| 764 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 765 | Register.\r | |
| 766 | @param AndData The value to AND with the PCI configuration register.\r | |
| 767 | \r | |
| 768 | @return The value written back to the PCI configuration register.\r | |
| 769 | \r | |
| 770 | **/\r | |
| 771 | UINT32\r | |
| 772 | EFIAPI\r | |
| 773 | PciCf8And32 (\r | |
| 774 | IN UINTN Address,\r | |
| 775 | IN UINT32 AndData\r | |
| 776 | );\r | |
| 777 | \r | |
| 778 | /**\r | |
| 779 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 780 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
| 781 | \r | |
| 782 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 783 | bitwise AND between the read result and the value specified by AndData,\r | |
| 784 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
| 785 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
| 786 | configuration register specified by Address. The value written to the PCI\r | |
| 787 | configuration register is returned. This function must guarantee that all PCI\r | |
| 788 | read and write operations are serialized.\r | |
| 789 | \r | |
| 790 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 791 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 792 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 793 | \r | |
| 794 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
| 795 | Register.\r | |
| 796 | @param AndData The value to AND with the PCI configuration register.\r | |
| 797 | @param OrData The value to OR with the result of the AND operation.\r | |
| 798 | \r | |
| 799 | @return The value written back to the PCI configuration register.\r | |
| 800 | \r | |
| 801 | **/\r | |
| 802 | UINT32\r | |
| 803 | EFIAPI\r | |
| 804 | PciCf8AndThenOr32 (\r | |
| 805 | IN UINTN Address,\r | |
| 806 | IN UINT32 AndData,\r | |
| 807 | IN UINT32 OrData\r | |
| 808 | );\r | |
| 809 | \r | |
| 810 | /**\r | |
| 811 | Reads a bit field of a PCI configuration register.\r | |
| 812 | \r | |
| 813 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
| 814 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 815 | returned.\r | |
| 816 | \r | |
| 817 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 818 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 819 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 820 | If StartBit is greater than 31, then ASSERT().\r | |
| 821 | If EndBit is greater than 31, then ASSERT().\r | |
| 822 | If EndBit is less than StartBit, then ASSERT().\r | |
| 823 | \r | |
| 824 | @param Address PCI configuration register to read.\r | |
| 825 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 826 | Range 0..31.\r | |
| 827 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 828 | Range 0..31.\r | |
| 829 | \r | |
| 830 | @return The value of the bit field read from the PCI configuration register.\r | |
| 831 | \r | |
| 832 | **/\r | |
| 833 | UINT32\r | |
| 834 | EFIAPI\r | |
| 835 | PciCf8BitFieldRead32 (\r | |
| 836 | IN UINTN Address,\r | |
| 837 | IN UINTN StartBit,\r | |
| 838 | IN UINTN EndBit\r | |
| 839 | );\r | |
| 840 | \r | |
| 841 | /**\r | |
| 842 | Writes a bit field to a PCI configuration register.\r | |
| 843 | \r | |
| 844 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 845 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 846 | destination PCI configuration register are preserved. The new value of the\r | |
| 847 | 32-bit register is returned.\r | |
| 848 | \r | |
| 849 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 850 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 851 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 852 | If StartBit is greater than 31, then ASSERT().\r | |
| 853 | If EndBit is greater than 31, then ASSERT().\r | |
| 854 | If EndBit is less than StartBit, then ASSERT().\r | |
| 855 | \r | |
| 856 | @param Address PCI configuration register to write.\r | |
| 857 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 858 | Range 0..31.\r | |
| 859 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 860 | Range 0..31.\r | |
| 861 | @param Value New value of the bit field.\r | |
| 862 | \r | |
| 863 | @return The value written back to the PCI configuration register.\r | |
| 864 | \r | |
| 865 | **/\r | |
| 866 | UINT32\r | |
| 867 | EFIAPI\r | |
| 868 | PciCf8BitFieldWrite32 (\r | |
| 869 | IN UINTN Address,\r | |
| 870 | IN UINTN StartBit,\r | |
| 871 | IN UINTN EndBit,\r | |
| 872 | IN UINT32 Value\r | |
| 873 | );\r | |
| 874 | \r | |
| 875 | /**\r | |
| 876 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
| 877 | writes the result back to the bit field in the 32-bit port.\r | |
| 878 | \r | |
| 879 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 880 | bitwise inclusive OR between the read result and the value specified by\r | |
| 881 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 882 | specified by Address. The value written to the PCI configuration register is\r | |
| 883 | returned. This function must guarantee that all PCI read and write operations\r | |
| 884 | are serialized. Extra left bits in OrData are stripped.\r | |
| 885 | \r | |
| 886 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 887 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 888 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 889 | If StartBit is greater than 31, then ASSERT().\r | |
| 890 | If EndBit is greater than 31, then ASSERT().\r | |
| 891 | If EndBit is less than StartBit, then ASSERT().\r | |
| 892 | \r | |
| 893 | @param Address PCI configuration register to write.\r | |
| 894 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 895 | Range 0..31.\r | |
| 896 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 897 | Range 0..31.\r | |
| 898 | @param OrData The value to OR with the PCI configuration register.\r | |
| 899 | \r | |
| 900 | @return The value written back to the PCI configuration register.\r | |
| 901 | \r | |
| 902 | **/\r | |
| 903 | UINT32\r | |
| 904 | EFIAPI\r | |
| 905 | PciCf8BitFieldOr32 (\r | |
| 906 | IN UINTN Address,\r | |
| 907 | IN UINTN StartBit,\r | |
| 908 | IN UINTN EndBit,\r | |
| 909 | IN UINT32 OrData\r | |
| 910 | );\r | |
| 911 | \r | |
| 912 | /**\r | |
| 913 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
| 914 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
| 915 | \r | |
| 916 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 917 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 918 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 919 | Address. The value written to the PCI configuration register is returned.\r | |
| 920 | This function must guarantee that all PCI read and write operations are\r | |
| 921 | serialized. Extra left bits in AndData are stripped.\r | |
| 922 | \r | |
| 923 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 924 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 925 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 926 | If StartBit is greater than 31, then ASSERT().\r | |
| 927 | If EndBit is greater than 31, then ASSERT().\r | |
| 928 | If EndBit is less than StartBit, then ASSERT().\r | |
| 929 | \r | |
| 930 | @param Address PCI configuration register to write.\r | |
| 931 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 932 | Range 0..31.\r | |
| 933 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 934 | Range 0..31.\r | |
| 935 | @param AndData The value to AND with the PCI configuration register.\r | |
| 936 | \r | |
| 937 | @return The value written back to the PCI configuration register.\r | |
| 938 | \r | |
| 939 | **/\r | |
| 940 | UINT32\r | |
| 941 | EFIAPI\r | |
| 942 | PciCf8BitFieldAnd32 (\r | |
| 943 | IN UINTN Address,\r | |
| 944 | IN UINTN StartBit,\r | |
| 945 | IN UINTN EndBit,\r | |
| 946 | IN UINT32 AndData\r | |
| 947 | );\r | |
| 948 | \r | |
| 949 | /**\r | |
| 950 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
| 951 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
| 952 | 32-bit port.\r | |
| 953 | \r | |
| 954 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 955 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
| 956 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
| 957 | configuration register specified by Address. The value written to the PCI\r | |
| 958 | configuration register is returned. This function must guarantee that all PCI\r | |
| 959 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 960 | OrData are stripped.\r | |
| 961 | \r | |
| 962 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 963 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 964 | If the register specified by Address >= 0x100, then ASSERT().\r | |
| 965 | If StartBit is greater than 31, then ASSERT().\r | |
| 966 | If EndBit is greater than 31, then ASSERT().\r | |
| 967 | If EndBit is less than StartBit, then ASSERT().\r | |
| 968 | \r | |
| 969 | @param Address PCI configuration register to write.\r | |
| 970 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 971 | Range 0..31.\r | |
| 972 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 973 | Range 0..31.\r | |
| 974 | @param AndData The value to AND with the PCI configuration register.\r | |
| 975 | @param OrData The value to OR with the result of the AND operation.\r | |
| 976 | \r | |
| 977 | @return The value written back to the PCI configuration register.\r | |
| 978 | \r | |
| 979 | **/\r | |
| 980 | UINT32\r | |
| 981 | EFIAPI\r | |
| 982 | PciCf8BitFieldAndThenOr32 (\r | |
| 983 | IN UINTN Address,\r | |
| 984 | IN UINTN StartBit,\r | |
| 985 | IN UINTN EndBit,\r | |
| 986 | IN UINT32 AndData,\r | |
| 987 | IN UINT32 OrData\r | |
| 988 | );\r | |
| 989 | \r | |
| 990 | /**\r | |
| 991 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
| 992 | \r | |
| 993 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
| 994 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
| 995 | configuration registers from a single PCI function to be read. Size is\r | |
| 996 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
| 997 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
| 998 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
| 999 | end of the range.\r | |
| 1000 | \r | |
| 1001 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1002 | If the register specified by StartAddress >= 0x100, then ASSERT().\r | |
| 1003 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r | |
| 1004 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1005 | \r | |
| 1006 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
| 1007 | Function and Register.\r | |
| 1008 | @param Size Size in bytes of the transfer.\r | |
| 1009 | @param Buffer Pointer to a buffer receiving the data read.\r | |
| 1010 | \r | |
| 1011 | @return Size\r | |
| 1012 | \r | |
| 1013 | **/\r | |
| 1014 | UINTN\r | |
| 1015 | EFIAPI\r | |
| 1016 | PciCf8ReadBuffer (\r | |
| 1017 | IN UINTN StartAddress,\r | |
| 1018 | IN UINTN Size,\r | |
| 1019 | OUT VOID *Buffer\r | |
| 1020 | );\r | |
| 1021 | \r | |
| 1022 | /**\r | |
| 1023 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
| 1024 | configuration space.\r | |
| 1025 | \r | |
| 1026 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
| 1027 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
| 1028 | configuration registers from a single PCI function to be written. Size is\r | |
| 1029 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
| 1030 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
| 1031 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
| 1032 | and the end of the range.\r | |
| 1033 | \r | |
| 1034 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1035 | If the register specified by StartAddress >= 0x100, then ASSERT().\r | |
| 1036 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r | |
| 1037 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1038 | \r | |
| 1039 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
| 1040 | Function and Register.\r | |
| 1041 | @param Size Size in bytes of the transfer.\r | |
| 1042 | @param Buffer Pointer to a buffer containing the data to write.\r | |
| 1043 | \r | |
| 1044 | @return Size\r | |
| 1045 | \r | |
| 1046 | **/\r | |
| 1047 | UINTN\r | |
| 1048 | EFIAPI\r | |
| 1049 | PciCf8WriteBuffer (\r | |
| 1050 | IN UINTN StartAddress,\r | |
| 1051 | IN UINTN Size,\r | |
| 1052 | IN VOID *Buffer\r | |
| 1053 | );\r | |
| 1054 | \r | |
| 1055 | #endif\r |