| b341712e |
1 | #/*++\r |
| 2 | #\r |
| 3 | #Copyright (c) 2006, Intel Corporation \r |
| 4 | #All rights reserved. This program and the accompanying materials \r |
| 5 | #are licensed and made available under the terms and conditions of the BSD License \r |
| 6 | #which accompanies this distribution. The full text of the license may be found at \r |
| 7 | #http://opensource.org/licenses/bsd-license.php \r |
| 8 | # \r |
| 9 | #THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r |
| 10 | #WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r |
| 11 | #\r |
| 12 | #Module Name:\r |
| 13 | #\r |
| 14 | # RShiftU64.c\r |
| 15 | #\r |
| 16 | #Abstract:\r |
| 17 | #\r |
| 18 | # 64-bit right shift function for IA-32\r |
| 19 | #\r |
| 20 | #--*/\r |
| 21 | #\r |
| 22 | ##include "Tiano.h"\r |
| 23 | #\r |
| 24 | #include "EfiBind.h"\r |
| 25 | #---------------------------------------------------------------------------\r |
| 26 | .686: \r |
| 27 | #.MODEL flat,C\r |
| 28 | .code: \r |
| 29 | \r |
| 30 | #---------------------------------------------------------------------------\r |
| 31 | .globl ASM_PFX(RShiftU64)\r |
| 32 | #UINT64\r |
| 33 | #RShiftU64 (\r |
| 34 | # IN UINT64 Operand,\r |
| 35 | # IN UINTN Count\r |
| 36 | # )\r |
| 37 | #/*++\r |
| 38 | #\r |
| 39 | #Routine Description:\r |
| 40 | # This routine allows a 64 bit value to be right shifted by 32 bits and returns the \r |
| 41 | # shifted value.\r |
| 42 | # Count is valid up 63. (Only Bits 0-5 is valid for Count)\r |
| 43 | #Arguments:\r |
| 44 | # Operand - Value to be shifted\r |
| 45 | # Count - Number of times to shift right.\r |
| 46 | # \r |
| 47 | #Returns:\r |
| 48 | #\r |
| 49 | # Value shifted right identified by the Count.\r |
| 50 | #\r |
| 51 | #--*/\r |
| 52 | ASM_PFX(RShiftU64):\r |
| 53 | \r |
| 54 | movl 4(%esp), %eax # dword ptr Operand[0]\r |
| 55 | movl 8(%esp), %edx # dword ptr Operand[4]\r |
| 56 | \r |
| 57 | #\r |
| 58 | # CL is valid from 0 - 31. shld will move EDX:EAX by CL times but EDX is not touched\r |
| 59 | # For CL of 32 - 63, it will be shifted 0 - 31 so we will move edx to eax later. \r |
| 60 | #\r |
| 61 | movl 0xC(%esp), %ecx # Count\r |
| 62 | andl $63, %ecx\r |
| 63 | shrd %cl, %edx, %eax\r |
| 64 | shrb %cl, %edx\r |
| 65 | \r |
| 66 | cmpl $32, %ecx\r |
| 67 | jc _RShiftU64_Done\r |
| 68 | \r |
| 69 | #\r |
| 70 | # Since Count is 32 - 63, edx will have been shifted by 0 - 31 \r |
| 71 | # If shifted by 32 or more, set upper 32 bits to zero.\r |
| 72 | #\r |
| 73 | movl %edx, %eax\r |
| 74 | xorl %edx, %edx\r |
| 75 | \r |
| 76 | _RShiftU64_Done: \r |
| 77 | \r |
| 78 | ret\r |
| 79 | #RShiftU64 ENDP\r |
| 80 | \r |
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